JPH10229138A - Nonvolatile memory element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent static damage of a second insulating film from being caused and moreover, to enable write and erase in a control gate(CG) voltage by a method wherein a plurality of grooves are formed in the surface of a floating gate(FG). SOLUTION: Three grooves 202 are formed in the surface of an FG 201 of a nonvolatile memory element. Therefore, the total extension of the lower parts of steps in the grooves 202, in which an electric field is easy to concentrate, in the surface of the FG 201 is increased as many as the number of the grooves 202. Accordingly, the degree of the concentration of the electric field in the low parts of the steps due to application of a voltage is relaxed in comparison with the degree of the concentration of an electric field in the lower parts of steps in grooves in the surface of a conventional FG with one recess part provided in the central part thereof. Moreover, in the case where each roundness is given to the square parts extending from the bottoms of the grooves 202 to the sidewalls of the grooves 202, the degree of the concentration of the electric field is further relaxed. Furthermore, as the opposed area between the FG-CG of the memory element is made wider than the opposed area between the FG-CG of a nonvolatile memory element having the conventional FG, a CG voltage V CG for obtaining a prescribed FG voltage FG is further reduced. Accordingly, the static damage of a second insulating film 106 between the CG-FG can be prevent from being caused.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory device, and more particularly, to a semiconductor device, in which a floating gate and a control gate are stacked on a semiconductor substrate, and a source / drain is provided on both sides of the control gate on the surface of the semiconductor substrate. The present invention relates to a floating gate type nonvolatile memory element.

[0002]

2. Description of the Related Art FIG. 5A is a plan view of a floating gate (hereinafter referred to as FG) type nonvolatile memory element, and FIG. 5B is a sectional view taken along the line AA 'in FIG. It is sectional drawing. The FG type nonvolatile memory element shown in these figures is arranged in an active region 103 separated by an element isolation region 102 on the surface side of a semiconductor substrate 101. This non-volatile memory element has a semiconductor substrate 10
In order from the first side, a first insulating film 104, an FG 105, a second insulating film 106, and a control gate (hereinafter, referred to as CG)
107 are stacked. CG10
The source 108 and the drain 109 are provided on the surface of the active region 103 of the semiconductor substrate 101 on both sides of the semiconductor substrate 101.

In the FG type nonvolatile memory element having the above structure, when a positive voltage is applied to the CG 107, the first insulating film 104
, Electrons are injected from the semiconductor substrate 101 to the FG 105 and accumulated. On the other hand, when a negative voltage is applied to the CG 107, the charges accumulated in the FG 105 are released to the semiconductor substrate 101 via the first oxide film 104 again. Also,
The nonvolatile memory element having the above configuration includes CG107, FG10
5 and the source 108 / drain 109 are formed in a self-aligned manner, so that they are more suitable for miniaturization than a FLOTOX (Floating Gate Tunnel Oxide) type non-volatile memory element having an overlapping portion between the FG and the drain. .

However, in the nonvolatile memory element having the above configuration, when injecting / emitting electrons into / from the FG 105 as described above, it is necessary to apply a high CG voltage VCG of about 20 V. For this reason, in the semiconductor memory device constituted by this nonvolatile memory element, the influence of the voltage application easily affects other unselected cells sharing the word line / bit line with the selected cell. This is due to a malfunction or a write /
This is a factor that causes a read failure.

Therefore, as shown in the sectional view of FIG.
There has been proposed an FG113 structure including a main part 111 and a sidewall 112 arranged so as to surround the main part 111. When the FG 113 is formed, the FG 113 is formed by forming a sidewall 112 on a side wall of the FG main portion 111 and an insulating film (not shown) on the upper surface thereof, and then removing the insulating film.

In the nonvolatile memory element having the above configuration, FG1
13 is provided with a concave portion on the surface of the FG11.
3 and the CG 107 have an increased facing area, and the FG 113-C
The capacity CFC between G107 increases. Here, the FG voltage V
FG is represented by VFG = VCG × {CFC / (CSF + CFC)}. For this reason, the capacitance C
By increasing the FC, the CG voltage VCG for obtaining the predetermined FG voltage VFG can be reduced, and it is possible to suppress the malfunction in the nonvolatile memory element.

[0007]

However, in the nonvolatile memory element having the structure shown in FIG. 6, the electric field tends to concentrate on the lower part a of the step on the surface of the FG 113. In particular, this FG1
13 is a side wall 11 around the FG main portion 111.
2, the portion of the second insulating film 106 covering the lower part a of the step is sharpened in a square shape, and the electric field is more easily concentrated. This causes electrostatic breakdown of the second insulating film 106 between the FG 113 and the CG 107.

Further, with the recent miniaturization of semiconductor devices, there is a demand for further lowering the driving voltage. Therefore, an object of the present invention is to provide a nonvolatile memory element suitable for miniaturization, which can prevent electrostatic breakdown of the second insulating film 106 and can be written and erased with a CG voltage.

[0009]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and has FG and CG on a semiconductor substrate.
Wherein the source / drain is provided on the surface side of the semiconductor substrate on both sides of the CG, wherein at least two grooves are provided on the surface of the FG.

According to the nonvolatile memory element, since at least two grooves are provided on the FG surface, the total extension of the lower part of the step where the electric field tends to concentrate on the FG surface increases by the number of grooves. Therefore, the concentration of the electric field at the lower part of the step due to the application of the voltage is reduced as compared with the conventional FG in which one concave portion is provided in the center. Moreover, the conventional F
Since the facing area between FG and CG is wider than that of G, the CG voltage for obtaining a predetermined FG voltage is further reduced.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. Note that the same components as those in the above-described conventional technology are denoted by the same reference numerals, and description thereof will be simplified or omitted.

FIG. 1A is a plan view showing an embodiment of a nonvolatile memory element to which the present invention is applied.
FIG. 2B is a sectional view taken along the line AA ′ in FIG. 1A, that is, a sectional view in the channel width direction. The difference between the nonvolatile memory element shown in these figures and the nonvolatile memory element described in the related art is that the first insulating film 1 is formed on the semiconductor substrate 101.
04 is provided through the FG 201. That is, the FG20 of the nonvolatile memory element shown in this embodiment
1 has three grooves 2 on its surface over the channel length direction.
02 is provided. For this reason, the second insulating film 106 covering the FG 201 is provided along the inner wall in the groove 202, and the CG 107 is provided so as to fill the groove 202. A source 108 and a drain 109 are provided on the surface of the active region 103 of the semiconductor substrate 101 on both sides of the CG 107.

FIG. 2 is a process chart showing an example of a procedure for manufacturing the nonvolatile memory element. The detailed configuration of the nonvolatile memory element will be described below in the order of manufacturing steps with reference to FIG. First, as shown in FIG. 2A, an element isolation region 102 is formed on the surface side of a semiconductor substrate 101 made of single crystal silicon by a LOCOS method, and each active region 103 on the surface side of the semiconductor substrate 101 is separated. Thereafter, by performing ion implantation and activation heat treatment, the active region 103 is formed.
A well diffusion layer (not shown) is formed on the surface of the semiconductor substrate 101, impurities for adjusting a threshold voltage are introduced, and the conductivity type and impurity concentration on the surface of the semiconductor substrate 101 are adjusted.

Next, a first insulating film 104 made of silicon oxide is formed on the exposed surface layer of the semiconductor substrate 101 by subjecting the surface of the semiconductor substrate 101 to a thermal oxidation treatment. The first insulating film 104 has a thickness (for example, about 2 nm to 3 nm) that allows holes to tunnel with electrons. Thereafter, an FG forming layer 201a made of conductive polysilicon is formed on the element isolation region 102 and the first insulating film 104 to a thickness of about 1.0 μm. This FG
The formation layer 201a is formed by introducing impurities into doped polysilicon formed by a CVD method or polysilicon formed by a CVD method.

Next, as shown in FIG. 2B, a resist pattern 203 is formed on the FG forming layer 201a. Thereafter, a groove 202 having a depth of about 0.5 μm is formed on the surface of the FG forming layer 201a by etching using the resist pattern 203 as a mask. This groove 202
Are formed so as to be arranged three in the channel length direction of the obtained FG. In the final stage of the etching, the corner from the etching bottom to the etching side wall may be rounded by switching from anisotropic etching to isotropic etching.

Next, after removing the resist pattern 203, as shown in FIG. 2C, the FG forming layer 201a is formed.
A new resist pattern 204 is formed thereon. Thereafter, patterning in the channel width direction of the FG forming layer 201a is performed by etching using the resist pattern 204 as a mask.

Next, after the resist pattern 204 is removed, as shown in FIG. 2D, the surface of the FG forming layer 201a is covered with the second insulating film 106. This second insulating film 106
Means silicon oxide film / silicon nitride film /
A three-layer structure of a silicon oxide film may be used. In this case, first, the exposed surface of the FG formation layer 201a is oxidized by a thermal oxidation treatment in a steam atmosphere to form a silicon oxide film. Next, a silicon nitride film having a thickness of about 10 nm is formed on the silicon oxide film by a CVD method. Thereafter, the exposed surface of the silicon nitride film is oxidized by further performing a thermal oxidation treatment in a steam atmosphere to form a silicon oxide film.

Next, as shown in FIG. 2 (5), a CG forming layer 107a made of conductive polysilicon is formed on the semiconductor substrate 101 so as to cover the second insulating film 106. The CG forming layer 107a is formed in the same manner as the FG forming layer 201a. Thereafter, etching is performed using a resist pattern (not shown) as a mask, and the CG forming layer 107a, the second insulating film 106, and the FG
The formation layer 201a is patterned in the channel length direction. Thereby, the first insulating film 1 is formed on the semiconductor substrate 101.
The FG 201 is provided via the first insulating film 104, and the CG 107 is provided on the FG 201 via the second insulating film 106.

After that, the resist pattern is removed, ion implantation is performed using the CG 107 as a mask, and activation heat treatment is performed. As a result, the source / drain (see FIG. (Not shown).

As described above, the nonvolatile memory element shown in FIG. 1 is formed. This nonvolatile memory element is FG2
By providing three grooves 202 on the surface of the FG 201
The lower part of the step a in the groove 202 where the electric field tends to concentrate on the surface
Is increased by the number of grooves 202. Therefore,
Compared with the conventional FG in which one concave portion is provided in the center, the degree of concentration of the electric field below the step due to the application of the voltage is reduced. Further, when the corners from the bottom to the side walls of the groove 202 are rounded, the degree of concentration of charges is further reduced. Moreover, since the facing area between the FG and the CG is larger than that of the conventional nonvolatile memory element having the FG, the CG voltage VCG for obtaining the predetermined FG voltage VFG is further reduced.

FIG. 3 is a plan view of another nonvolatile memory element to which the present invention is applied. The difference between the nonvolatile memory element shown in this figure and the nonvolatile memory element described with reference to FIG. 1 lies in the arrangement of grooves provided on the FG surface. That is, the nonvolatile memory element FG3 shown in FIG.
01 surface, two grooves 20 are formed over the channel width direction.
2 are provided. Other configurations are the same as those of the nonvolatile memory element described with reference to FIG.

Even with the nonvolatile memory element having such a configuration, the same effect as that of the nonvolatile memory element described with reference to FIG. 1 can be obtained.

FIG. 4 is a plan view of still another nonvolatile memory element to which the present invention is applied. In the nonvolatile memory element shown in this figure, three grooves 202 are provided on the surface of the FG 401 over the channel length direction, and two grooves 202 are provided over the channel width direction. Other configurations are the same as those of the nonvolatile memory element described with reference to FIG.
This is the same as the non-volatile memory element described with reference to FIG.

In the non-volatile element having the above-mentioned structure,
The grooves 202 and 30 are smaller than the nonvolatile memory elements shown in FIG.
The total extension of the lower part of the step in 2 can be further lengthened. Therefore, the capability of alleviating the electric field is higher than that of the nonvolatile memory element shown in FIGS. And FG
Since the facing area between 401 and CG 107 is also wider than that of the nonvolatile memory element shown in FIGS. 1 and 3, the CG voltage VCG for obtaining a predetermined FG voltage VFG can be further reduced.

The FG of each of the above embodiments was formed by etching the surface of the FG forming layer. However, the FG in the nonvolatile memory element of the present invention may be formed by covering the plurality of first FG layers patterned in an island shape with the second FG layer. In this case, a groove is formed between the first FG layers. Since the surface of the FG thus formed is formed of the surface on which the second FG layer is formed, the bottom of the step in the groove is formed into a round shape, and the electric field is easily alleviated.

The capacitance between FG and CG can be adjusted by the depth of the groove. Therefore, the depth of the groove is set so as to obtain a predetermined CG voltage.

[0027]

As described above, according to the nonvolatile memory element of the present invention, in the nonvolatile memory element having the source / drain provided on the surface side of the semiconductor substrate on both sides of the CGNO, at least two nonvolatile memory elements are provided on the FG surface. By providing the groove, it is possible to further reduce the CG voltage by increasing the capacitance between the FG and the CG while alleviating the partial charge concentration on the FG surface. Therefore, it is possible to obtain a nonvolatile memory element that can prevent electrostatic breakdown of the second insulating film between CG and FG and that can perform writing and erasing with a lower CG voltage.

[Brief description of the drawings]

FIG. 1 is a structural diagram of a nonvolatile memory element to which the present invention is applied.

FIG. 2 is a manufacturing process diagram of a nonvolatile memory element to which the present invention is applied.

FIG. 3 is a plan view of another nonvolatile memory element to which the present invention is applied.

FIG. 4 is a plan view of still another nonvolatile memory element to which the present invention is applied.

FIG. 5 is a structural diagram of a nonvolatile memory element to which a conventional technique is applied.

FIG. 6 is a cross-sectional view of another nonvolatile memory element to which a conventional technique is applied.

[Explanation of symbols]

101 semiconductor substrate 104 first insulating film 106
Second insulating film 107 CG (control gate) 108 source 109 drain 201, 301, 401 FG (floating gate) 202 groove

Claims (1)

[Claims] A semiconductor substrate and a first substrate on the semiconductor substrate;
A floating gate provided via an insulating film, a control gate provided on the floating gate via a second insulating film, and a source / drain provided on the surface side of the semiconductor substrate on both sides of the control gate Wherein at least two grooves are provided on the surface of the floating gate.