JP2000260966A - Non-volatile semiconductor storage device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the thickness of an inter-gate insulating film by providing a gate electrode of a peripheral circuit transistor with a laminating structure, comprising first and second conductive layers starting from a substrate side, allowing a floating gate electrode of a memory transistor to be a first conductive layer, and providing a control gate electrode with a laminating structure which comprises third and second conductive layers starting from the substrate side. SOLUTION: A gate electrode of power-source voltage transistor 127 and high breakdown voltage transistor 126 of a peripheral circuit region comprise a laminating body of conductive polysilicon layers 118 and 120, and tungsten silicide layers 119 and 121. A floating gate electrode 112 of a memory transistor comprises a conductive polysilicon layer, and the control gate electrode 126 comprises a laminating body of a conductive polysilicon layer 123 and tungsten silicide layer 124. So, at formation of an insulating film of the lower part of a peripheral circuit transistor by oxidation, no effect of oxidation is applied on a silicon nitride film of an inter-gate insulating film of the memory transistor. Thus, a silicon nitride film of high quality and thin film is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a nonvolatile semiconductor memory device and a method for manufacturing the nonvolatile semiconductor memory device.
In particular, the gate electrode of the peripheral circuit transistor has a laminated structure of the first and second conductive layers from the substrate side, the floating gate electrode of the memory transistor is formed of the first conductive layer, and the control gate electrode of the memory transistor is the substrate side. And a stacked gate type nonvolatile semiconductor memory device having a stacked structure of a third and a second conductive layer, whereby the thickness of the inter-gate insulating film between the floating gate electrode and the control gate electrode can be reduced. It relates to the manufacturing method.

[0002]

2. Description of the Related Art As a nonvolatile semiconductor memory device capable of electrically writing and erasing data, a nonvolatile semiconductor memory device is provided on a region between a source region and a drain region on a surface of a semiconductor substrate.
Nonvolatile semiconductor having a field effect transistor in which a floating gate electrode is provided via a first gate insulating film, and a control gate electrode which is capacitively connected to the floating gate electrode via a second gate insulating film is further formed thereon Storage devices are known.

When information is written to this storage element,
The control gate electrode is set to a positive high potential to form a channel on the substrate surface, and a positive voltage is applied to the drain region. At this time, electrons traveling in the channel receive energy due to the high electric field generated on the channel, and are injected into the floating gate electrode through the potential barrier formed by the first gate insulating film. The state where electrons are injected into the floating gate electrode in this manner is referred to as a write state. On the other hand, erase of written information is performed by discharging electrons from the floating gate electrode by FN tunnel current.

With the recent increase in the degree of integration of semiconductor devices,
In such a nonvolatile semiconductor memory device, there is an increasing demand for a reduction in the cell size and a reduction in the write voltage. For this purpose, it is necessary to reduce the gate length and reduce the thickness of the tunnel oxide film and the inter-gate insulating film.

Conventionally, the following is known as a technique for improving the performance of a nonvolatile semiconductor memory device by controlling (or reducing) the thickness of an inter-gate insulating film.

(1) JP-A-5-63206 discloses that
A method for manufacturing a nonvolatile semiconductor memory device as shown in FIG. 7 is described. This manufacturing method uses the silicon substrate 201
A field oxide film 202, a first oxide film 203, a floating gate electrode 204, a second oxide film 205, and a control gate electrode 206 are sequentially formed thereon, and then a gate portion and a peripheral circuit of the memory cell nonvolatile semiconductor memory device are formed. Patterning the control gate electrode 206 while leaving a portion covering the
Further, a source / drain region is formed by introducing an impurity into the memory cell portion. Thereafter, a first interlayer insulating film 210 is formed, and patterning is performed so as to expose only the peripheral circuit portion. 3 to form an oxide film 212, a gate electrode 213, and source / drain regions 215.216.

In this manufacturing method, the source / source of the memory cell portion is
The source / drain regions 215 and 216 in the peripheral circuit portion and the source / drain regions 208 and 209 in the memory cell portion are formed under different conditions without separately providing a PR process for forming the drain regions 208 and 209. In addition, the oxide film 205 on the floating gate electrode 204 in the memory cell portion and the gate oxide film 212 of the transistor in the peripheral circuit portion can be controlled to desired thicknesses.

(2) Japanese Patent Application Laid-Open No. 9-107086 discloses that an ONO film is used as an inter-gate interlayer film (inter-gate insulating film). A non-volatile semiconductor memory device and a method of manufacturing the same in which a gate insulating film of a MISFET for a peripheral circuit is formed to have an optimum thickness by changing the film thickness in the same step.

According to this manufacturing method, the thickness of the interlayer film between the gates can be reduced, so that the characteristics of the semiconductor device can be improved and the size of the memory cell can be reduced.

(3) Japanese Patent Application Laid-Open No. Hei 10-92957 discloses that oxygen atoms are selectively introduced into at least two or more regions of a semiconductor substrate by ion implantation under different conditions. Forming an oxygen-introducing layer on the substrate, converting the oxygen-introducing layer to an oxide film, and using the oxide film as a gate oxide film, wherein at least two or more types of MOS field effect transistors having different gate insulating film thicknesses. And a step of forming a semiconductor device.

In this manufacturing method, at least two types of MOS having gate insulating films having different thicknesses on the same substrate are used.
In forming a semiconductor device including a die element, a gate insulating film is formed without being affected by contamination of organic substances or the like, and a semiconductor device having excellent characteristics without variation between elements is manufactured.

(4) Further, as related to the present invention, the following stacked-gate type nonvolatile semiconductor memory device is known. Hereinafter, this nonvolatile semiconductor memory device and its conventional manufacturing method will be described with reference to the drawings. FIG. 8A is a sectional view in the word line direction of a conventional stacked gate type EPROM having a high breakdown voltage transistor 324 and a power supply voltage transistor 325 in a peripheral circuit region and a memory cell transistor in a memory cell region. FIG. 8B is a structural cross-sectional view of the memory cell region of FIG.

The gate electrodes of the high breakdown voltage transistor 324 and the power supply voltage transistor 325 formed in the peripheral circuit area of the EPROM have a second conductive layer 318 made of conductive polysilicon and a third conductive layer made of tungsten.
Are laminated.

The memory cell transistor 326 formed in the memory cell region has a floating gate electrode 307,
An inter-gate insulating film 308 formed on the floating gate electrode 307 and a control gate electrode 327 formed on the inter-gate insulating film 308. Further, the floating gate electrode 307 is formed of a first conductive layer made of conductive polysilicon, and the control gate electrode 327 is formed of a second conductive layer 321 made of conductive polysilicon and a third conductive layer made of tungsten silicide. It has a structure in which the layers 322 are stacked.

The EPROM is composed of a semiconductor substrate 30
1 has a structure in which the lower peripheral region of each gate electrode is electrically connected to a lower wiring layer (not shown) and a connection plug formed in an interlayer insulating film (not shown), but these are not shown for convenience. are doing.

First, as shown in FIG. 9A, a field oxide film 302 and an oxide film 303 'are formed on an N-type silicon semiconductor substrate 301 by an ordinary method.

Next, as shown in FIG. 9B, a P for a memory transistor is formed in a region where a memory transistor will be formed in the future (referred to as a “memory transistor forming region”).
After forming the P well 304 into which the type impurity is introduced, the oxide film is peeled off, and a first insulating film (tunnel oxide film) 303 is newly formed. Further, as shown in FIG. 9C, for example, polysilicon doped with phosphorus in-situ is deposited by a CVD method to form a first conductive film 305.

Next, as shown in FIG. 10D, resist patterning 306 for determining the width of the floating gate electrode of the memory transistor in the word line direction is performed, and the first conductive film 305 is etched. After forming the first conductive layer 307 of the floating gate electrode, FIG.
The structure shown in (e) is obtained.

Next, as shown in FIG. 10F, a silicon oxide film having a thickness of about 8 nm is formed on the first conductive film 305 and the first conductive layer 307 by, for example, the HTO method. A silicon nitride film having a thickness of about 10 nm is formed on the silicon oxide film by a CVD method, and a silicon oxide film is formed on the silicon nitride film by an HTO method to form a three-layer inter-gate insulation. Membrane 308
To form

Thereafter, as shown in FIG. 11G, a memory transistor forming region is formed by resist patterning 309.
11H, the inter-gate insulating film 308 in the region where the peripheral circuit transistor is to be formed in the future (referred to as “peripheral circuit transistor forming region”), as shown in FIG.
The conductive film 305 and the tunnel oxide film 303 are selectively removed, and the resist film is stripped.

Next, a new oxide film 310 'is formed with a thickness of about 20 nm by, for example, the HTO method. As described above, the structure shown in FIG.

Next, a well 311 for a power supply voltage transistor and a well 312 for a high breakdown voltage transistor are formed in a peripheral circuit transistor formation region of the semiconductor substrate 301 by a conventional method. Further, after the gate oxide film 310 'in the region F where the power supply voltage transistor is formed is peeled off, the gate oxide film 310 is formed again. At this time, the gate oxide film 313 of the high breakdown voltage transistor is formed by the combined oxidation of the oxide film 310 ′ and the oxide film 310.

In this manner, as shown in FIG. 12 (j), the gate oxide film 310 of the power supply voltage transistor and the gate oxide film 313 of the high voltage transistor can be separately formed with a desired film thickness.

Next, as shown in FIG. 12K, for example, phosphorus-doped polysilicon is deposited on the entire surface by a CVD method to form a second conductive film 314. Further, on the second conductive film 314, for example, by a CVD method,
A third conductive film 315 made of tungsten silicide is stacked.

Next, as shown in FIG. 12 (l), a resist patterning 320 for forming a gate electrode of a peripheral circuit transistor (both a high withstand voltage transistor and a power supply voltage transistor) is first performed. Then, gate electrodes (318 and 319 and 316 and 317) of the peripheral circuit transistor are formed.

Thereafter, as shown in FIG. 13 (m), after performing resist patterning 323 for forming a gate electrode of the memory transistor, predetermined processing is performed.
The control gate electrodes (321, 32) of the memory transistors
2) is formed. The control gate electrode includes the second and third
Of the conductive layer. G at this time
FIG. 13N shows a cross-sectional view in the −G ′ direction.

As described above, as shown in FIG. 8, the high breakdown voltage transistor 326 and the power supply voltage transistor 327 are provided in the peripheral transistor formation region, and the floating gate electrode 3 made of the first conductive layer is provided in the memory transistor formation region.
07 and a stacked gate non-volatile semiconductor memory device in which a memory transistor including a control gate electrode 327 having a stacked structure of second and third conductive layers is formed with the ONO film 308 interposed therebetween. . As described above, the steps of forming the source / drain regions and the like of the semiconductor substrate and the drawings are omitted.

As described above, in the nonvolatile semiconductor memory device shown in FIG. 8, the peripheral circuit transistor and the memory transistor can be formed on the same semiconductor substrate in the same step. Further, in order to improve the performance of the nonvolatile semiconductor memory device such as lowering the write voltage, the memory transistor has a structure including a floating gate electrode and a control gate electrode via an ONO film, and a gate of a peripheral circuit transistor is provided. The electrode and the control gate electrode of the memory transistor have a stacked structure of a conductive polysilicon layer and a tungsten silicide layer.

[0029]

As described above, in a nonvolatile semiconductor memory device, a silicon oxide film / silicon nitride film / silicon nitride film is used as an inter-gate insulating film in order to improve its performance.
A three-layer laminated film of a silicon oxide film (a so-called ONO film) is generally used. The use of such a laminated film reduces the probability of existence of defects such as pinholes by forming a laminated film, and reduces the effective film thickness by sandwiching a silicon nitride film having a high relative dielectric constant between silicon oxide films. Because you can.

Usually, the bottom (substrate side) silicon oxide film is formed by oxidizing the polysilicon of the floating gate electrode or by using High Temperature Ch.
electronic Deposited Oxidatio
By the n method (hereinafter, referred to as “HTO method”), the silicon nitride film is formed into a Chemical Vapor Depo.
The top silicon oxide film (on the silicon nitride film) is formed by a sition method (hereinafter, referred to as a “CVD method”), or by oxidation of silicon nitride or an HTO method. In the inter-gate insulating film (ONO film), the top silicon oxide film prevents injection of Hole from the control gate electrode, and the bottom silicon oxide film prevents electrons from leaking from the floating gate electrode.

Therefore, when thinning the inter-gate insulating film, there is a limit to thinning the top and bottom silicon oxide films, and it is desirable to make the silicon nitride film between the silicon oxide films as thin as possible. Become.

However, the methods described in the above (1) to (3) are for controlling the thickness of the gate (inter) insulating film made of silicon oxide, and for reducing the thickness of the silicon nitride film. Not a technology. Therefore, there is a need for a technique for forming a silicon nitride film as an ONO film, which is an inter-gate insulating film, as thin as possible.

Further, the manufacturing method (4) also has the following problem. That is, in the above process (4), the gate insulating film formed below the peripheral circuit transistor is oxidized. However, at this time,
This oxidation is added to the inter-gate insulating film, and the silicon nitride film, which is the intermediate film of the ONO film, is completely or locally oxidized to the first conductive polysilicon film, which is the base film. It may be oxidized.

As described above, there is a demand for reducing the thickness of the silicon nitride film. If the thickness of the silicon nitride film is reduced, the oxidation resistance of the silicon nitride film is reduced, and the silicon nitride film is more easily oxidized. That is, according to the manufacturing method (4) described above, the lower limit of the thickness of the silicon nitride film is determined by the oxidation resistance of the silicon nitride film, and the lower limit cannot be obtained.

In order to solve such a problem, the present invention has improved the above-mentioned manufacturing method (4), and the gate insulating film (particularly, silicon nitride film) is not oxidized. It is an object of the present invention to provide a non-volatile semiconductor memory device capable of thinning an inter-insulating film and a method of manufacturing the same.

[0036]

In order to achieve the above object,
The present invention relates to (1) a stacked-gate nonvolatile semiconductor memory device having a peripheral circuit transistor and a memory transistor formed on the same substrate, wherein the peripheral circuit transistor is provided on a substrate via an insulating film. Formed
The memory transistor includes at least one gate electrode having a stacked structure of a first conductive layer and a third conductive layer from a substrate side, and the memory transistor includes a first conductive layer formed over a substrate with an insulating film interposed therebetween. Having a floating gate electrode and a control gate electrode formed on the floating gate electrode via an inter-gate insulating film and having a stacked structure of a second conductive layer and a third conductive layer from the substrate side. Provided is a semiconductor memory device.

In the nonvolatile semiconductor memory device of the present invention, it is preferable that the peripheral circuit transistor has a gate electrode of a high breakdown voltage transistor and a gate electrode of a power supply voltage transistor.

Further, it is preferable that the gate electrode of the high breakdown voltage transistor, the gate electrode of the power supply voltage transistor, and the floating gate electrode of the memory transistor are formed on an insulating film having a predetermined thickness.

In this case, it is more preferable that the gate electrode of the high breakdown voltage transistor is formed on an insulating film having a thickness larger than that of the insulating film below the gate electrode of the power supply voltage transistor.

Further, in the nonvolatile semiconductor memory device according to the present invention, the first conductive layer is made of conductive polysilicon, the second conductive layer is made of conductive polysilicon, and the third conductive layer is made of conductive polysilicon. The conductive layer is preferably made of a metal, a metal alloy or a metal silicide.

Further, it is preferable that the inter-gate insulating film has a laminated structure including a silicon oxide film, a silicon nitride film and a silicon oxide film.

(2) The nonvolatile semiconductor memory device of the present invention is a stacked-gate nonvolatile semiconductor memory device having a peripheral circuit transistor and a memory transistor on the same substrate, wherein the first conductive type substrate A field oxide film formed on the first conductivity type substrate; and a second conductivity type formed in a peripheral circuit transistor forming region defined by the field oxide film on the first conductivity type substrate. A first well, a second well of a second conductivity type formed in a memory transistor formation region defined by the field oxide film of the first conductivity type substrate, and an insulating layer on the first well; A gate electrode of a peripheral circuit transistor formed from a substrate side and having a stacked structure of a first conductive layer and a third conductive layer from the substrate side; and an insulating film on the second well. A floating gate electrode of a memory transistor having a first conductive layer formed by forming a second conductive layer and a third conductive layer on the floating gate electrode with an inter-gate insulating film interposed therebetween. It is preferable to include a control gate electrode of a memory transistor having a stacked structure.

In the nonvolatile semiconductor memory device of the present invention, it is preferable that the peripheral circuit transistor has a gate electrode of a high breakdown voltage transistor and a gate electrode of a power supply voltage transistor.

In this case, it is more preferable that the gate electrode of the high breakdown voltage transistor is formed on an insulating film having a larger thickness than the insulating film below the gate electrode of the power supply voltage transistor.

It is more preferable that the gate electrode of the high breakdown voltage transistor, the gate electrode of the power supply voltage transistor, and the floating gate electrode of the memory transistor are each formed on an insulating film having a predetermined thickness.

Further, the inter-gate insulating film has a laminated structure composed of a silicon oxide film, a silicon nitride film and a silicon oxide film, the first conductive layer is made of conductive polysilicon, and the second conductive layer is made of a conductive polysilicon. Preferably, the conductive layer is made of conductive polysilicon, and the third conductive layer is made of metal, metal alloy or metal silicide.

(3) The present invention also relates to a method of manufacturing a stacked gate type nonvolatile semiconductor memory device including a step of forming a peripheral circuit transistor and a memory transistor on the same substrate. Forming a field oxide film, forming an insulating film in a region defined by the field oxide film on the substrate, and forming a first conductive film on the first insulating film. Process and
Forming a first conductive layer of a floating gate electrode by etching the first conductive film on at least the memory transistor formation region partitioned by the element isolation region; and forming the first conductive film and the first conductive film on the first conductive layer. Forming an inter-gate insulating film on the conductive layer, forming a second conductive film on the inter-gate insulating film, and forming a second conductive film on the peripheral circuit transistor forming region partitioned by the element isolation region. The second
Removing the conductive film and the inter-gate insulating film; and forming a peripheral circuit transistor forming region partitioned by the element isolation region on the first conductive film in the peripheral circuit transistor forming region and the memory cell transistor. Forming a third conductive film on the inter-gate insulating film in the formation region, and etching the third conductive film to form a third conductive layer of the peripheral circuit transistor and the control gate electrode And a method of manufacturing a nonvolatile semiconductor memory device.

In the method of manufacturing a nonvolatile semiconductor memory device according to the present invention, the step of forming a field oxide film on the substrate includes forming a field oxide film on the substrate so that the surface of the substrate has a high withstand voltage. It is preferable that the method further includes a step of partitioning into a region for forming a transistor, a region for forming a power supply voltage transistor, and a region for forming a memory transistor.

Further, the step of forming an insulating film in a region defined by the field oxide film on the substrate includes the steps of: forming an insulating film on the peripheral circuit transistor forming region and an insulating film on the memory transistor forming region; It is preferable to have a step of forming each with a predetermined film thickness.

In this case, the step of forming an insulating film on a region defined by the field oxide film on the substrate includes the step of forming the high breakdown voltage transistor,
Forming a first insulating film on a region for forming a power supply voltage transistor and a region for forming a memory transistor; and forming a first insulating film on a region for forming the power supply voltage transistor and a region for forming a memory transistor More preferably, and a step of forming a second insulating film on a region where the power supply voltage transistor is formed and a region where the memory transistor is formed.

In the step of forming the second insulating film, the step of forming the second insulating film on the region for forming the power supply voltage transistor and the region for forming the memory transistor is performed simultaneously with the step of forming the high withstand voltage transistor. above,
More preferably, the method further includes a step of forming a third insulating film having a thickness larger than that of the second insulating film.

Further, in the method of manufacturing a nonvolatile semiconductor memory device according to the present invention, the step of forming a first insulating film in a region defined by the field oxide film on the substrate includes the step of: It is preferable to include a step of forming a silicon oxide film thereon by a thermal oxidation method or an HTO method.

In the step of forming the first conductive film, a silicon compound and a phosphorus compound as an impurity may be used.
Forming a conductive polysilicon film by a VD method; and forming the inter-gate insulating film by the first method.
Sequentially stacking a first silicon oxide film on the conductive film and the first conductive layer, a silicon nitride film on the first silicon oxide film, and a second silicon oxide film on the silicon nitride film It is preferable that each has the following.

The step of forming the second conductive film includes a step of forming a conductive polysilicon film on the inter-gate insulating film by a CVD method using a silicon compound and a phosphorus compound as an impurity. Forming the conductive film of Step 3 on the first conductive film in the peripheral circuit transistor formation region and on the inter-gate insulating film in the memory transistor formation region by sputtering, CVD, or vacuum evaporation. And a step of forming a metal alloy or a metal silicide film.

(4) A method of manufacturing a nonvolatile semiconductor memory device according to the present invention, wherein the stacked gate type nonvolatile semiconductor memory device includes a step of forming a peripheral circuit transistor and a memory transistor on the same substrate. Forming a field oxide film on a semiconductor substrate of a first conductivity type, and forming a second conductivity type on a peripheral circuit transistor forming region of the semiconductor substrate defined by the field oxide film. Forming a first well, forming a second well of a second conductivity type in a memory transistor forming region of the semiconductor substrate defined by the field oxide film, and forming the field of the semiconductor substrate. A step of forming an insulating film over a region partitioned by the oxide film; and a step of forming a first conductive film over the insulating film. Forming a first conductive layer of a floating gate electrode by etching the first conductive film on the memory transistor forming region partitioned by the element isolation region; and forming the first conductive film and the first conductive film on the first conductive layer. On the conductive layer of
Forming an inter-gate insulating film; forming a second conductive film on the inter-gate insulating film; and forming the second conductive film on a peripheral circuit transistor forming region partitioned by the element isolation region. Removing a film and the inter-gate insulating film; and forming a third conductive film on the first conductive film on the peripheral circuit transistor forming region and on the inter-gate insulating film on the memory transistor forming region. Forming a third conductive film, and forming a third conductive layer of the peripheral circuit transistor and the control gate electrode by etching the third conductive film. Is preferred.

In the above-described method for manufacturing a nonvolatile semiconductor memory device, the step of forming the second well includes the step of forming a well for a high breakdown voltage transistor in a peripheral circuit transistor forming region of the semiconductor substrate defined by the field oxide film. And a step of forming a well for a power supply voltage transistor.

In the step of forming a field oxide film on the first conductivity type semiconductor substrate, a field oxide film is formed on the substrate, so that the surface of the substrate is formed in a region for forming a high breakdown voltage transistor, a power supply, More preferably, the method includes a step of partitioning into a region where a voltage transistor is formed and a region where a memory transistor is formed.

Further, the step of forming an insulating film on the first conductive type semiconductor substrate in a region defined by the field oxide film includes the steps of: forming an insulating film on the peripheral circuit transistor forming region; It is preferable to include a step of forming each of the insulating films with a predetermined film thickness.

In this case, the step of forming an insulating film on a region defined by the field oxide film on the first conductivity type semiconductor substrate includes forming a region for forming the high breakdown voltage transistor and a power supply voltage transistor. Forming a first insulating film over the region and the region where the memory transistor is formed; removing the first insulating film over the region where the power supply voltage transistor is formed and the region where the memory transistor is formed; More preferably, the method further includes a step of forming a second insulating film over a region where the power supply voltage transistor is formed and a region where the memory transistor is formed.

In the above, the step of forming the second insulating film includes forming the second insulating film on a region for forming the power supply voltage transistor and a region for forming the memory transistor, More preferably, the method further includes a step of forming a third insulating film having a thickness larger than the second insulating film on the formation region.

The stacked gate nonvolatile semiconductor memory device of the present invention is a stacked gate nonvolatile semiconductor memory device having a peripheral circuit transistor and a memory transistor formed on the same substrate via an insulating film. ,
The gate electrode of the peripheral transistor has a stacked structure of first and third conductive layers from the substrate side, the floating gate electrode of the memory transistor is formed of the first conductive layer, and
The control gate electrode of the memory transistor has a stacked structure of second and third conductive layers from the substrate side (the side of the inter-gate insulating film).

Further, a method of manufacturing a stacked gate type nonvolatile semiconductor memory device of the present invention includes forming a peripheral circuit transistor and a memory transistor on the same substrate via an insulating film. After forming the conductive film of
Forming a first conductive layer of a floating gate electrode of a memory transistor, forming an inter-gate insulating film, forming a second conductive layer, and forming only a second conductive film and an inter-gate insulating film on a peripheral circuit formation region; , A third conductive film is formed, and then a gate electrode of a peripheral circuit transistor and a control gate electrode of a memory transistor are formed.

By forming the stacked gate type nonvolatile semiconductor memory device in this manner, when the insulating film below the peripheral circuit transistor, which has conventionally been a problem, is formed by oxidation, the insulating film between the gates of the memory transistor is reduced. The influence of oxidation on the silicon nitride film is eliminated.
Therefore, a high-quality and thin silicon nitride film can be formed without increasing the number of steps at all as compared with the conventional method. Also, there is no adverse effect on peripheral circuit transistors.

Further, the nonvolatile semiconductor memory device obtained by the manufacturing method of the present invention has an inter-gate insulating film having a high-quality thin silicon nitride film. Therefore, the writing voltage is reduced and the nonvolatile semiconductor memory device has high reliability.

Further, according to the method for manufacturing a nonvolatile semiconductor memory device of the present invention, when an insulating film having a low defect occurrence rate is used, a single-layer thin inter-gate insulating film can be used. Therefore, the size of the memory cell can be further reduced.

As the nonvolatile semiconductor memory device of the present invention, for example, an EPROM (Erasable Program)
ramble Read Only Memor
y) or EEPROM (Electrically-Er)
available Programmable Read
Only Memory).

[0067]

Next, embodiments of the present invention will be described with reference to the drawings. First Embodiment FIG. 1 is a structural sectional view of a memory cell region and a peripheral circuit region of an EPROM, which is a nonvolatile semiconductor memory device of the present embodiment. FIG. 1A is a structural sectional view of the EPROM in the word line direction, and FIG. 1B is a structural sectional view of the memory cell region in the AA ′ direction.

This EPROM has a high withstand voltage transistor 123 and a power supply voltage transistor 124 as peripheral circuit transistors in a peripheral circuit area, and a floating gate electrode 112 and an inter-gate insulating layer as memory transistors in a memory cell area. Film 118 and control gate electrode 1
Stacked-gate type EPRO having a thickness of 26.
M.

The EPROM shown in FIG. 1 is largely divided into a peripheral circuit region and a memory cell region by a field oxide film 102 of an N-type silicon semiconductor substrate 101, and an N-type silicon semiconductor substrate 101 in a region where each transistor is formed. Have P-wells 104, 105 and 106. In addition, on the P well 105 in the peripheral circuit region, the power supply voltage transistor 12
7. The insulating film 10 is formed on the P well 106 in the peripheral circuit region.
9, a high voltage transistor 126 is provided, and a memory transistor 128 is provided on the P well 104 in the memory cell region via an insulating film 108.

The gate electrodes of the power supply voltage transistor 127 and the high voltage transistor 126 (both are also referred to as peripheral circuit transistors) in the peripheral circuit region are made of a conductive polysilicon layer (first conductive layer) and tungsten silicide. It is composed of a laminate of layers (third conductive layer). Also, the floating gate electrode 11 of the memory transistor
Reference numeral 2 denotes a conductive polysilicon layer (first conductive layer), and the control gate electrode 126 includes a conductive polysilicon layer (second conductive layer) 123 and a tungsten silicide layer (third conductive layer) 124. It consists of a laminate.

That is, in this EPROM, the conductive polysilicon layers (118, 12) of the peripheral circuit transistors are used.
0) and the floating gate electrode 112 of the memory transistor are a conductive layer (first conductive layer) made of the same material, the conductive polysilicon layer 120 of the peripheral circuit transistor and the conductive polysilicon layer of the control gate electrode of the memory transistor. Characteristically, 124 is a conductive layer (third conductive layer) of the same material.

The thickness of the insulating film (108, 109) formed under each transistor is set to a predetermined thickness according to the withstand voltage characteristics required for each transistor.

Further, the inter-gate insulating film 113 provided between the floating gate electrode and the control gate electrode
Although not shown in detail, the laminated film has three layers of a silicon oxide film / a silicon nitride film / a silicon oxide film. The thickness of the intermediate silicon nitride film is 2 nm.
The thickness of the entire inter-gate insulating film is also reduced.

In practice, an N-type impurity diffusion region (source / drain region), an interlayer insulating film, a connection plug, a wiring layer, and the like are formed in a P well. Omitted.

In the EPROM of this embodiment, the inter-gate insulating film has a high quality and a smaller thickness than the conventional one. Further, insulating films (tunnel oxide films) of the high breakdown voltage transistor, the power supply voltage transistor, and the memory transistor are each formed with a predetermined thickness.

Therefore, this EPROM is a highly reliable stacked gate type EPROM in which the write voltage is reduced.

Second Embodiment Next, a method of manufacturing the EPROM shown in FIG. 1 will be described in detail. First, as shown in FIG. 2A, a predetermined region of the N-type silicon semiconductor
ocal Oxidation of Silicon
Method), a thick field oxide film 102 is formed. A silicon oxide film 103 is formed on the semiconductor substrate 101 in a region defined by the field oxide film 102.
Is formed, for example, by a thermal oxidation method or the like.

In this embodiment, an N-type silicon semiconductor substrate is used as a substrate, but a P-type silicon semiconductor substrate, another glass substrate, a ceramic substrate, or the like can be used.

Then, as shown in FIG. 2B, a P-type impurity such as boron is formed in the high breakdown voltage transistor forming region B, the power supply voltage transistor forming region C, and the memory transistor forming region partitioned by the field oxide film. To
For example, P wells 104, 105, and 106 are formed by ion implantation.

Thereafter, as shown in FIG. 2C, only the region for forming the high breakdown voltage transistor is covered with the resist film 107, and the oxide film 103 on the region for forming the power supply voltage transistor and the region for forming the memory transistor is formed. After selectively removing the resist film 107 and removing the resist film 107, FIG.
As shown in (d), the silicon oxide film (gate oxide film) 108 is again formed by, for example, a thermal oxidation method, an HTO method, or the like.
It is formed with a film thickness of about 3 to 15 nm. At this time, the oxide film 103 on the high breakdown voltage transistor formation region is also oxidized, and a relatively thick oxide film 109 is formed on the high breakdown voltage transistor formation region.

Next, as shown in FIG. 3E, a first conductive polysilicon film 110 is formed. The first conductive polysilicon film 110 is made of, for example, SiH ₄ or SiH
Silane compound gas such as ₂ Cl ₂ and PH ₃ , POCl ₃
By a CVD method using a phosphorus compound such as
It can be deposited at about 50 nm.

In this embodiment, the conductive polysilicon is used as the material of the first conductive layer. However, other conductive materials, for example, aluminum, aluminum alloy, copper, copper alloy, tungsten, tungsten alloy, etc., may be used. It can also be used. The same applies to the case where the second conductive layer is formed.

Subsequently, as shown in FIG. 3F, resist patterning 111 for forming a floating gate electrode of the memory transistor is performed, and the first conductive polysilicon film is selectively etched to form a floating gate. An electrode 112 is formed. Thereafter, the resist film 111 is removed, and FIG.
The structure shown in FIG.

Next, a silicon oxide film and a silicon nitride film
And gate insulating film 11 composed of three layers of silicon oxide film
3 (ONO film) with the floating gate electrode 107 and the first
Over the entire surface so as to cover the polysilicon film 110.
The silicon oxide film is formed by, for example, a thermal oxidation method or an HTO method.
The silicon nitride film is made of, for example, SiH_Four-NH _Three
Each can be formed by a CVD method using a gas.
Wear.

In this embodiment, the ONO film is formed as an inter-gate insulating film. However, as the inter-gate insulating film, a single-layer insulating film having a low defect occurrence rate, for example, HT
It may be a single layer of a silicon oxide film formed by an O method or the like, or another laminated film such as a so-called ONON film in which a silicon nitride film is further laminated on an ONO film. In particular, in the case of forming a single layer such as a silicon oxide film, further thinning is possible.

Thereafter, a second conductive polysilicon film 114 is formed on the second insulating film 109. The second conductive polysilicon film 114 is made of, for example, SiH ₄ or SiH
Silane compound gas such as ₂ Cl ₂ and PH ₃ , POCl ₃
By a CVD method using a phosphorus compound such as
It can be deposited at about 20 nm. As described above, the structure shown in FIG.

Next, as shown in FIG. 4I, only the memory cell region is covered with the resist film 115, and as shown in FIG. The insulating film 113 is selectively removed by etching.

Next, after removing the resist film 115,
As shown in FIG. 5K, a third conductive film 116 made of tungsten silicide is formed on the first conductive film 110 and the second conductive film 114. The tungsten silicide film 116 includes, for example, tungsten, molybdenum,
A layer made of a metal silicide which is a compound of silicon and a refraction metal such as platinum, palladium, titanium, and tantalum is formed to a thickness of 80 to 120 by, for example, a CVD method.
nm. The formation of the metal silicide film on the conductive polysilicon film in this manner increases the conductivity of the entire gate electrode layer by forming a laminate (so-called polycide layer) composed of conductive polysilicon and metal silicide. That's why.

Further, as shown in FIG. 5 (l), resist patterning 117 for forming the gate electrodes of the high breakdown voltage transistor and the power supply voltage transistor in the peripheral circuit region is performed.
Is performed, and the first conductive film 1 is formed using the resist pattern as a mask.
10 and the third conductive film 116 are etched to form the gate electrodes (120, 121) of the high voltage transistor 126 and the gate electrodes (118, 118) of the power supply voltage transistor 127.
119) is formed.

After that, the resist film 117 is removed, and FIG.
As shown in (m), resist patterning for forming a control gate electrode of the memory transistor is performed, and the third conductive film 116 and the second conductive film 114 are etched using the resist pattern 122 as a mask. A control gate electrode 126 including the second conductive layer 123 and the third conductive layer 124 is formed. FIG. 6 (n) is a structural cross-sectional view taken along line AA ′ of the memory cell region in FIG. 6 (m).

Thereafter, although not described and shown in detail, an interlayer insulating film (not shown) is formed, and a connection hole for forming a connection plug for electrically connecting the source / drain region and the wiring layer (not shown) is formed. Then, a desired EPROM can be manufactured through a process of forming a wiring layer by burying a conductive material such as tungsten in the connection hole and forming a wiring layer.

As described above, the EPR of this embodiment is
According to the OM manufacturing method, when the insulating film below the peripheral circuit transistor, which has conventionally been a problem, is formed by oxidation, the influence of the oxidation is not added to the silicon nitride film as the inter-gate insulating film of the memory transistor. Therefore, a high-quality and thin silicon nitride film can be formed without increasing the number of steps at all as compared with the conventional method. Also, there is no adverse effect on peripheral circuit transistors.

Further, according to the present embodiment, when an insulating film having a low defect occurrence rate is used, a single-layer thin inter-gate insulating film can be used, so that the memory cell can be further reduced. Is possible.

Therefore, according to the present embodiment, an inter-gate insulating film having a high-quality and thin silicon nitride film is provided. Therefore, the write voltage is reduced, and a highly reliable nonvolatile semiconductor memory device can be manufactured with high yield.

The present embodiment is merely an embodiment of the present invention, and the present invention can be applied by freely designing and changing without departing from the gist of the present invention. For example, LDD (Lightly Do
EP of a transistor having a ped drain structure
The present invention can be similarly applied to other stacked gate type nonvolatile semiconductor memory devices such as a ROM and an EEPROM.

[0096]

As described above, the stacked gate type non-volatile semiconductor memory device of the present invention has a high quality and thin inter-gate insulating film. Therefore, the writing voltage is reduced and the nonvolatile semiconductor memory device has high reliability.

Further, according to the method of manufacturing a nonvolatile semiconductor memory device of the present invention, when the insulating film below the peripheral circuit transistor, which has been a problem in the past, is formed by oxidation, the silicon nitride of the inter-gate insulating film of the memory transistor is formed. The film is not affected by oxidation. Therefore, a high-quality and thin silicon nitride film can be formed without increasing the number of steps at all as compared with the conventional method. Also, there is no adverse effect on peripheral circuit transistors.

Further, according to the method of manufacturing a nonvolatile semiconductor memory device of the present invention, when an insulating film having a low defect occurrence rate is used, a single-layer thin inter-gate insulating film can be used. Therefore, the size of the memory cell can be further reduced.

[Brief description of the drawings]

FIG. 1 shows a nonvolatile semiconductor memory device (E) of the present invention.
FIG. 3 is a structural cross-sectional view of a peripheral circuit region and a memory cell region of a PROM.

FIG. 2 is a sectional view of a main process in a method for manufacturing a nonvolatile semiconductor memory device of the present invention.

FIG. 3 is a sectional view of a main step in the method for manufacturing a nonvolatile semiconductor memory device of the present invention.

FIG. 4 is a sectional view of a main step in the method for manufacturing a nonvolatile semiconductor memory device of the present invention.

FIG. 5 is a sectional view of a main step in the method for manufacturing a nonvolatile semiconductor memory device of the present invention.

FIG. 6 is a sectional view of a main step in the method for manufacturing a nonvolatile semiconductor memory device of the present invention.

FIG. 7 is a structural sectional view of a nonvolatile semiconductor memory device manufactured by a conventional method of manufacturing a nonvolatile semiconductor memory device.

FIG. 8 is a structural sectional view of a peripheral circuit region and a memory cell region of a conventional nonvolatile semiconductor memory device.

FIG. 9 is a sectional view of a main step in a conventional method of manufacturing a nonvolatile semiconductor memory device.

FIG. 10 is a cross-sectional view of a main step in a conventional method of manufacturing a nonvolatile semiconductor memory device.

FIG. 11 is a sectional view of a main step in a conventional method of manufacturing a nonvolatile semiconductor memory device.

FIG. 12 is a cross-sectional view of a main step in a conventional method of manufacturing a nonvolatile semiconductor memory device.

FIG. 13 is a sectional view of a main step in a conventional method of manufacturing a nonvolatile semiconductor memory device.

[Explanation of symbols]

101, 301... N-type silicon semiconductor substrate, 102, 2
02, 302... Field oxide film, 103, 108, 1
09, 203, 212, 303, 303 ', 313, 3
10, 310 ′, 313: gate oxide film, 104, 10
5,106,304,311,312 ... P well, 10
7, 111, 115, 117, 122, 306, 30
9, 320, 323 resist pattern, 110, 30
5: first conductive film, 112, 204, 307: floating gate electrode, 113, 205, 308: inter-gate insulating film, 1
14, 314: second conductive film, 116, 315: third conductive film, 118: gate electrode (power supply voltage transistor)
The first conductive layers of the gate electrodes (power supply voltage transistors); 120, 319 the first conductive layers of the gate electrodes (high breakdown voltage transistors);
1: third conductive layer of gate electrode (high breakdown voltage transistor), 126, 324: high breakdown voltage transistor, 127, 3
25: power supply voltage transistor, 128, 326: memory transistor, 126: control gate electrode, 316: second conductive layer of gate electrode (power supply voltage transistor), 31
8 ... second conductive layer of gate electrode (power supply voltage transistor), 123, 321 ... second conductive layer of control gate electrode
124, 322... Third conductive layer of control gate electrode, 20
DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 206 ... Control gate electrode, 208 ...
Connection holes, 210: first interlayer insulating film, 213: gate electrodes of peripheral circuit transistors, 215, 216, 218,
219: Source / drain region, 217: Second interlayer insulating film, 219: Metal wiring, B, E: High breakdown voltage transistor formation region, C, F: Power supply voltage transistor formation region

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) PR46 PR53 PR54 PR56 ZA07

Claims (37)

[Claims] 1. A stacked-gate nonvolatile semiconductor memory device having a peripheral circuit transistor and a memory transistor formed on the same substrate, wherein the peripheral circuit transistor is formed on a substrate via an insulating film. And at least one gate electrode having a stacked structure of a first conductive layer and a third conductive layer from a substrate side, wherein the memory transistor has a first conductive layer formed on a substrate via an insulating film. A floating gate electrode having a layer, formed on the floating gate electrode via an inter-gate insulating film;
A nonvolatile semiconductor memory device, comprising: a control gate electrode having a stacked structure of a second conductive layer and a third conductive layer from the substrate side. 2. The nonvolatile semiconductor memory device according to claim 1, wherein said peripheral circuit transistor has a gate electrode of a high voltage transistor and a gate electrode of a power supply voltage transistor. 3. A gate electrode of the high breakdown voltage transistor,
3. The nonvolatile semiconductor memory device according to claim 2, wherein said non-volatile semiconductor memory device is formed on an insulating film having a thickness larger than an insulating film below a gate electrode of said power supply voltage transistor. 4. The device according to claim 3, wherein the gate electrode of the high breakdown voltage transistor, the gate electrode of the power supply voltage transistor, and the floating gate electrode of the memory transistor are formed on insulating films each having a predetermined thickness. Non-volatile semiconductor storage device. 5. The nonvolatile semiconductor memory device according to claim 1, wherein said first conductive layer is made of conductive polysilicon. 6. The nonvolatile semiconductor memory device according to claim 1, wherein said third conductive layer is made of a metal, a metal alloy, or a metal silicide. 7. The nonvolatile semiconductor memory device according to claim 1, wherein said second conductive layer is made of conductive polysilicon. 8. The inter-gate insulating film is a silicon oxide film,
2. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device has a stacked structure including a silicon nitride film and a silicon oxide film. 9. A stacked gate non-volatile semiconductor memory device having a peripheral circuit transistor and a memory transistor on the same substrate, comprising: a first conductive type substrate; and a first conductive type substrate formed on the first conductive type substrate. A field oxide film, a first well of a second conductivity type formed in a peripheral circuit transistor forming region defined by the field oxide film of the first conductivity type substrate, and a first conductivity type. A second region formed in a memory transistor forming region defined by the field oxide film on the substrate;
And a gate electrode of a peripheral circuit transistor formed on the first well with an insulating film interposed therebetween and having a stacked structure of a first conductive layer and a third conductive layer from the substrate side A first well formed on the second well via an insulating film;
A floating gate electrode of a memory transistor having a conductive layer of: a memory transistor formed on the floating gate electrode via an inter-gate insulating film, and having a stacked structure of a second conductive layer and a third conductive layer from the substrate side And a control gate electrode. 10. The nonvolatile semiconductor memory device according to claim 9, wherein said peripheral circuit transistor has a gate electrode of a high voltage transistor and a gate electrode of a power supply voltage transistor. 11. A gate electrode of the high breakdown voltage transistor,
11. The nonvolatile semiconductor memory device according to claim 10, wherein a gate electrode of said power supply voltage transistor and a floating gate electrode of said memory transistor are respectively formed on an insulating film having a predetermined thickness. 12. The nonvolatile semiconductor memory device according to claim 11, wherein a gate electrode of said high breakdown voltage transistor is formed on an insulating film having a thickness larger than an insulating film below a gate electrode of said power supply voltage transistor. . 13. The nonvolatile semiconductor memory device according to claim 9, wherein said inter-gate insulating film has a laminated structure including a silicon oxide film, a silicon nitride film, and a silicon oxide film. 14. The nonvolatile semiconductor memory device according to claim 9, wherein said first conductive layer is made of conductive polysilicon. 15. The nonvolatile semiconductor memory device according to claim 9, wherein said second conductive layer is made of a metal, a metal alloy, or a metal silicide. 16. The nonvolatile semiconductor memory device according to claim 9, wherein said third conductive layer is made of conductive polysilicon. 17. A method for manufacturing a stacked gate type nonvolatile semiconductor memory device, comprising the steps of forming a peripheral circuit transistor and a memory transistor on the same substrate, wherein a field oxide film is formed on the substrate. A step of forming an insulating film in a region defined by the field oxide film on the substrate; a step of forming a first conductive film on the first insulating film; Forming a first conductive layer of a floating gate electrode by etching the first conductive film on the memory transistor formation region defined by the region; and on the first conductive film and the first conductive layer Forming an inter-gate insulating film; forming a second conductive film on the inter-gate insulating film; forming a peripheral circuit transistor partitioned by the element isolation region Removing the second conductive film and the inter-gate insulating film on a region; and forming a peripheral circuit transistor on the first conductive film on the peripheral circuit transistor forming region partitioned by the element isolation region. Forming a third conductive film on the inter-gate insulating film in the memory cell transistor formation region; and etching the third conductive film to form a third conductive film on the peripheral circuit transistor and the control gate electrode. Forming a conductive layer. 18. A process for forming a field oxide film on a substrate, comprising forming a field oxide film on the substrate to form a region for forming a high-voltage transistor and a region for forming a power supply voltage transistor on the substrate surface. The method for manufacturing a nonvolatile semiconductor memory device according to claim 17, further comprising a step of partitioning into a region where a memory transistor is formed. 19. The step of forming an insulating film in a region defined by the field oxide film on the substrate includes the steps of: forming an insulating film on the peripheral circuit transistor forming region and an insulating film on the memory transistor forming region; The method for manufacturing a nonvolatile semiconductor memory device according to claim 17, further comprising a step of forming each with a predetermined film thickness. 20. A step of forming an insulating film on a region defined by the field oxide film on the substrate, comprising forming a region for forming the high breakdown voltage transistor, a region for forming a power supply voltage transistor, and a memory transistor. Forming a first insulating film on a region to be formed, removing the first insulating film on a region for forming the power supply voltage transistor and a region for forming the memory transistor, and forming the power supply voltage transistor 19. The method for manufacturing a nonvolatile semiconductor memory device according to claim 18, further comprising a step of forming a second insulating film over the region where the memory transistor is formed and the region where the memory transistor is formed. 21. The step of forming the second insulating film includes forming a second insulating film on a region where the power supply voltage transistor is formed and a region where a memory transistor is formed, and simultaneously forming the high breakdown voltage transistor forming region. 21. The method for manufacturing a nonvolatile semiconductor memory device according to claim 20, further comprising a step of forming a third insulating film having a thickness larger than that of the second insulating film. 22. A step of forming a first insulating film on a region defined by the field oxide film on the substrate,
On the area of the substrate, a thermal oxidation method or HTO (High T
emperature Chemical Depos
The method for manufacturing a nonvolatile semiconductor memory device according to claim 17, further comprising a step of forming a silicon oxide film by an iterated oxidation method. 23. The step of forming the first conductive film, comprising: CVD using a silicon compound and a phosphorus compound as an impurity.
(Chemical Vapor Deposition
28. The method for manufacturing a nonvolatile semiconductor memory device according to claim 27, further comprising a step of forming a conductive polysilicon film by an n) method. 24. The step of forming the inter-gate insulating film,
A first silicon oxide film over the first conductive film and the first conductive layer; a silicon nitride film over the first silicon oxide film; and a second silicon oxide film over the silicon nitride film. The method for manufacturing a nonvolatile semiconductor memory device according to claim 17, further comprising a step of sequentially stacking. 25. The step of forming the second conductive film, wherein the CVD (Chemical Vapo) using a silicon compound and a phosphorus compound as an impurity is performed on the inter-gate insulating film.
The method for manufacturing a nonvolatile semiconductor memory device according to claim 17, further comprising a step of forming a conductive polysilicon film by an r Deposition method. 26. A step of forming the third conductive film, comprising: sputtering, CVD (Chemical Vapor Deposition) on the first conductive film in the peripheral circuit transistor formation region and on the inter-gate insulating film in the memory transistor formation region. Chemical
The method for manufacturing a nonvolatile semiconductor memory device according to claim 17, further comprising a step of forming a metal, a metal alloy, or a metal silicide film by a vapor deposition method or a vacuum evaporation method. 27. A method of manufacturing a stacked gate type nonvolatile semiconductor memory device, comprising the steps of forming a peripheral circuit transistor and a memory transistor on the same substrate, comprising the steps of: Forming an oxide film; forming a first well of a second conductivity type in a peripheral circuit transistor forming region defined by the field oxide film on the semiconductor substrate; and forming the field oxide film on the semiconductor substrate. Forming a second well of the second conductivity type in the memory transistor formation region defined by the above, and forming an insulating film on the region of the semiconductor substrate defined by the field oxide film. Forming a first conductive film on the insulating film; and at least a memory transistor partitioned by the element isolation region Forming a first conductive layer of the floating gate electrode by etching the first conductive film on the formation region; and forming an inter-gate insulating film on the first conductive film and the first conductive layer. Forming; forming a second conductive film on the inter-gate insulating film; and forming a second conductive film between the second conductive film and the gate on a peripheral circuit transistor forming region partitioned by the element isolation region. Removing an insulating film; forming a third conductive film on the first conductive film on the peripheral circuit transistor forming region and on an inter-gate insulating film on the memory transistor forming region; Forming the third conductive layer of the peripheral circuit transistor and the control gate electrode by etching the third conductive film. 28. The step of forming a first well of the second conductivity type includes forming a well for a high breakdown voltage transistor in a peripheral circuit transistor forming region defined by the field oxide film of the semiconductor substrate. 28. The method for manufacturing a nonvolatile semiconductor memory device according to claim 27, further comprising: forming a well for a power supply voltage transistor. 29. The step of forming a field oxide film on the first conductivity type semiconductor substrate includes forming a field oxide film on the substrate to form a field oxide film on a substrate surface, a region for forming a high breakdown voltage transistor, and a power supply. 28. The method for manufacturing a nonvolatile semiconductor memory device according to claim 27, further comprising a step of partitioning a region where a voltage transistor is formed and a region where a memory transistor is formed. 30. A step of forming an insulating film on the first conductive type semiconductor substrate in a region defined by the field oxide film, the method comprising the steps of: forming an insulating film on the peripheral circuit transistor forming region and forming a insulating film on the memory transistor forming region; And the insulating film of
28. The method for manufacturing a nonvolatile semiconductor memory device according to claim 27, further comprising a step of forming each with a predetermined film thickness. 31. A step of forming an insulating film on a region defined by the field oxide film on the first conductivity type semiconductor substrate, wherein the step of forming an insulating film comprises:
Forming a first insulating film on a region for forming a power supply voltage transistor and a region for forming a memory transistor; and forming a first insulating film on a region for forming the power supply voltage transistor and a region for forming a memory transistor 30. The method for manufacturing a nonvolatile semiconductor memory device according to claim 29, further comprising: removing a semiconductor device; and forming a second insulating film on a region where the power supply voltage transistor is formed and a region where the memory transistor is formed. 32. The step of forming the second insulating film comprises forming a second insulating film on a region for forming the power supply voltage transistor and a region for forming a memory transistor, and simultaneously forming the high withstand voltage transistor forming region. 32. The method for manufacturing a nonvolatile semiconductor memory device according to claim 31, further comprising a step of forming a third insulating film having a thickness larger than that of the second insulating film. 33. A step of forming an insulating film on a region of the semiconductor substrate defined by the field oxide film, the method comprises the steps of: using a thermal oxidation method or an HTO (High T
emperature Chemical Depos
28. The method for manufacturing a nonvolatile semiconductor memory device according to claim 27, further comprising a step of forming a silicon oxide film by an iterated oxidation method. 34. The step of forming the first conductive film is performed by CVD using a silicon compound and a phosphorus compound as an impurity.
(Chemical Vapor Deposition
28. The method for manufacturing a nonvolatile semiconductor memory device according to claim 27, further comprising a step of forming a conductive polysilicon film by an n) method. 35. The step of forming the inter-gate insulating film,
A first silicon oxide film on the first conductive film and the first conductive layer, a silicon nitride film on the first silicon oxide film, and a second silicon oxide film on the silicon nitride film 28. The method for manufacturing a nonvolatile semiconductor memory device according to claim 27, further comprising a step of sequentially laminating the semiconductor devices. 36. A step of forming the second conductive film, wherein the step of forming the second conductive film uses a CVD (Chemical Vapor) method using a silicon compound and a phosphorus compound as an impurity on the inter-gate insulating film.
28. The method for manufacturing a nonvolatile semiconductor memory device according to claim 27, further comprising a step of forming a conductive polysilicon film by a Deposition method. 37. A step of forming the third conductive film, the step of forming the third conductive film on the first conductive film in the peripheral circuit transistor forming region and on the inter-gate insulating film in the memory transistor forming region by sputtering, CVD ( Chemical
The method for manufacturing a nonvolatile semiconductor memory device according to claim 27, further comprising a step of forming a metal, a metal alloy, or a metal silicide film by a vapor deposition method or a vacuum evaporation method.