JPS62128566A - Manufacture of thin film transistor - Google Patents
Manufacture of thin film transistorInfo
- Publication number
- JPS62128566A JPS62128566A JP26884985A JP26884985A JPS62128566A JP S62128566 A JPS62128566 A JP S62128566A JP 26884985 A JP26884985 A JP 26884985A JP 26884985 A JP26884985 A JP 26884985A JP S62128566 A JPS62128566 A JP S62128566A
- Authority
- JP
- Japan
- Prior art keywords
- film
- resistance semiconductor
- amorphous silicon
- semiconductor film
- plasma
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 239000010408 film Substances 0.000 claims abstract description 75
- 239000004065 semiconductor Substances 0.000 claims abstract description 39
- 238000005530 etching Methods 0.000 claims abstract description 12
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 3
- 239000001301 oxygen Substances 0.000 claims abstract description 3
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 3
- 239000000758 substrate Substances 0.000 claims description 5
- 238000000034 method Methods 0.000 claims description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 18
- 238000001020 plasma etching Methods 0.000 abstract description 5
- 230000007547 defect Effects 0.000 abstract description 3
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 3
- 229910000681 Silicon-tin Inorganic materials 0.000 description 2
- LQJIDIOGYJAQMF-UHFFFAOYSA-N lambda2-silanylidenetin Chemical compound [Si].[Sn] LQJIDIOGYJAQMF-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、アクティブマトリクス液晶表示装置などに用
いられる薄膜トランジスタの製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a thin film transistor used in an active matrix liquid crystal display device or the like.
絶縁基板上に形成されたゲート電極とゲート絶縁膜と高
抵抗半導体膜と低抵抗半導体膜とソース電極とドレイン
電極から成る薄膜トランジスタにおいて、ソース電極と
ドレイン電極をマスクの一部として、前記低抵抗半導体
膜を酸素プラズマ（Ｏｔプラズマ）でエツチングするこ
とによって、オーミックコンタクトが良く、高抵抗半導
体膜を薄くできるので、遮光膜のいらないｇｉ膜トラン
ジスタが高歩留りで容易に得られる。In a thin film transistor consisting of a gate electrode, a gate insulating film, a high-resistance semiconductor film, a low-resistance semiconductor film, a source electrode, and a drain electrode formed on an insulating substrate, the low-resistance semiconductor is By etching the film with oxygen plasma (Ot plasma), a high-resistance semiconductor film with good ohmic contact can be made thin, so a GI film transistor that does not require a light-shielding film can be easily obtained with high yield.
（従来の技術〕
半導体薄膜とくに非晶質シリコンを用いた薄膜トランジ
スタは、光によって導電率が大きく変化するので、薄膜
トランジスタの製作においては、遮光を行う必要があっ
た。非晶質シリコンの光導電率を低下する一方法として
、非晶質シリコン膜厚を極めて薄くすることがあるが、
従来の製造方法では製作が困難であった。以下に第３図
を用いて従来技術の問題点を説明する。第３図は、一般
的に用いられる逆スタガ構造の薄膜トランジスタの断面
図である。薄膜トランジスタは、絶縁基板１上にゲート
電極２、ゲート絶縁膜（例えばシリコンチン化膜）３、
高抵抗半導体膜（例えば非晶質シリコン膜）４、低抵抗
半導体膜（例えばＮ゛゛晶質シリコン膜）５、ソース電
極６、ドレイン電極７からなり、高抵抗半導体１！４と
低抵抗半導体膜５は、連続的に形成することによって界
面のコンタクトを良好にしている。しかし従来の薄膜ト
ランジスタでは、ＣＦ４系のガスでエツチングするため
、低抵抗半導体膜５と高抵抗半導体膜４のエツチング速
度が非常に近いのと、エツチングスピードが早いため、
ソース電極６とドレイン電極７をマスクにして、低抵抗
半導体膜５を選択除去する際、下地の高抵抗半導体膜４
もエツチングされ制御が非常にむずかしい。また、ゲー
ト絶縁膜（例えば５ｉＮ）３も、高抵抗半導体膜４のピ
ンホール等によってエツチングされ、欠陥発生の原因と
なることがある。そこで、第２図の構造の薄膜トランジ
スタを製作する場合は、高抵抗半導体膜４を低抵抗半導
体膜５よりも充分厚く、例えば３０００Å以上形成して
いて、遮光膜も形成しなければならない。また、高抵抗
半導体膜４の膜厚が厚いと、その直列抵抗も大きくなり
トランジスタ特性上からも好ましくない。(Prior art) Since the conductivity of thin film transistors using semiconductor thin films, especially amorphous silicon, changes greatly depending on light, it is necessary to shield light when manufacturing thin film transistors.Photoconductivity of amorphous silicon One way to reduce this is to make the amorphous silicon film extremely thin.
It was difficult to manufacture using conventional manufacturing methods. The problems of the prior art will be explained below with reference to FIG. FIG. 3 is a cross-sectional view of a commonly used thin film transistor with an inverted staggered structure. The thin film transistor includes a gate electrode 2, a gate insulating film (for example, a silicon tin film) 3, on an insulating substrate 1.
Consists of a high-resistance semiconductor film (for example, an amorphous silicon film) 4, a low-resistance semiconductor film (for example, a N crystalline silicon film) 5, a source electrode 6, and a drain electrode 7; 5 improves the interface contact by forming them continuously. However, in conventional thin film transistors, since etching is performed using a CF4-based gas, the etching speed of the low resistance semiconductor film 5 and the high resistance semiconductor film 4 are very similar, and the etching speed is fast.
When selectively removing the low-resistance semiconductor film 5 using the source electrode 6 and drain electrode 7 as masks, the underlying high-resistance semiconductor film 4
It is also etched and very difficult to control. Further, the gate insulating film (for example, 5iN) 3 may also be etched by pinholes or the like in the high-resistance semiconductor film 4, causing defects. Therefore, when manufacturing a thin film transistor having the structure shown in FIG. 2, the high-resistance semiconductor film 4 must be sufficiently thicker than the low-resistance semiconductor film 5, for example, 3000 Å or more, and a light shielding film must also be formed. Furthermore, if the high-resistance semiconductor film 4 is thick, its series resistance also increases, which is undesirable from the viewpoint of transistor characteristics.
本発明は、従来のこのような欠点を解決するためになさ
れたもので、極めて薄い高抵抗半導体膜を用いたときで
も製作しやすい薄膜トランジスタの製造方法を提供する
ものである。The present invention was made to solve these conventional drawbacks, and provides a method for manufacturing a thin film transistor that is easy to manufacture even when using an extremely thin high-resistance semiconductor film.
上記問題点を解決するために、本発明は、低抵抗半導体
膜をソース電極とドレイン電極をマスクの一部として、
ｏ２プラズマエッチし、かつ低抵抗半導体膜の膜厚を極
めて薄＜シたものである。In order to solve the above problems, the present invention uses a low resistance semiconductor film as a part of a mask for a source electrode and a drain electrode.
O2 plasma etching is performed, and the thickness of the low resistance semiconductor film is extremely thin.
上記のように、高抵抗半導体膜を薄く （例えば５００
オングストローム以下）形成された薄膜トランジスタが
、高抵抗半導体膜と低抵抗半導体膜界面のコンタクトも
良好で、かつ遮光膜のいらない薄膜トランジスタが容易
にできる。As mentioned above, the high resistance semiconductor film is made thin (for example, 500
The formed thin film transistor (less than Angstrom) has good contact between the high-resistance semiconductor film and the low-resistance semiconductor film interface, and a thin film transistor that does not require a light-shielding film can be easily produced.
以下に本発明の実施例を図面に基づいて詳細に説明する
。第１図は、本発明の薄膜トランジスタの断面図を示す
。ガラス等の絶縁基板ｌ上に、ＡＩ。Embodiments of the present invention will be described in detail below based on the drawings. FIG. 1 shows a cross-sectional view of a thin film transistor of the present invention. AI on an insulating substrate such as glass.
Ｃｒ、Ｍｏ等のゲート電極２が設けられ、ゲート絶縁膜
（例えばシリコンチン化膜）３、高抵抗半導体膜（例え
ば非晶質シリコン膜）４、低抵抗半導体膜（例えばＮ゛
゛晶質シリコン膜）５、例えばＡＩ。A gate electrode 2 made of Cr, Mo, etc. is provided, and includes a gate insulating film (for example, a silicon tin film) 3, a high-resistance semiconductor film (for example, an amorphous silicon film) 4, and a low-resistance semiconductor film (for example, a N crystalline silicon film). )5, for example AI.
Ｃ「等のソース電極６、ドレイン電極７が形成されてい
る。Ｎ゛非非晶質シリコ脱膜５、ソース電極６、ドレイ
ン電極７をマスクの一部として、０゜プラズマエツチン
グする。例えば、非晶質シリコン膜４の膜厚を２００〜
５００オングストロームで、Ｎ０非晶質シリコン膜５の
膜厚を５０〜２００オングストロームの範囲で、Ｎ゛非
非晶質シリコ脱膜５ｏｚプラズマでエツチングして薄膜
トランジスタを製造した結果、安定したトランジスタ特
性が再現性よく得られた。また、仮に非晶質シリコン膜
４にピンホールがあっても、ゲート絶縁膜（シリコンチ
ン化膜） ３は、０２プラズマにエツチングされにくい
ため欠陥は発生しない。第２図は、本発明の一例を示す
もので、例えば非晶質シリコン膜４の膜厚が３００オン
グストロームで、Ｎ゛非非晶質シリコ脱膜５膜厚が１０
０オングストロームの時のゲート電圧■６−ドレイン電
流■。A source electrode 6 and a drain electrode 7 such as C' are formed. N' plasma etching is performed at 0° using the amorphous silicon removed film 5, source electrode 6, and drain electrode 7 as part of a mask. For example, The thickness of the amorphous silicon film 4 is 200~
Stable transistor characteristics were reproduced as a result of manufacturing a thin film transistor by etching the N0 amorphous silicon film 5 with a thickness of 50 to 200 angstroms using N0 amorphous silicon removal 5oz plasma. I got it very well. Further, even if there is a pinhole in the amorphous silicon film 4, no defect will occur because the gate insulating film (silicon tinned film) 3 is not easily etched by the 02 plasma. FIG. 2 shows an example of the present invention. For example, the thickness of the amorphous silicon film 4 is 300 angstroms, and the thickness of the removed amorphous silicon film 5 is 10 angstroms.
Gate voltage ■6-drain current■ at 0 angstrom.
特性の０□プラズマエツチングとの関係を示す。The relationship between the characteristics and 0□ plasma etching is shown.
第２図中曲線ａは、Ｎ゛゛晶質シリコン膜をエツチング
する前の特性を示し、０Ｎ１０ＦＦ比がなくソース電極
６とドレイン電橋７間が、単なる抵抗である事を示す、
第２図中曲ｂ’Ａ ｂは、Ｎ°非非晶質シリコ成膜５．
０．６ＴＯＲＲの圧力で、電力６０Ｗ、Ｏｆ流ｆｆｉ
２０ Ｓ ＣＣＭ、 ：Ｌ ７ チ７り時間１分３０秒
でｏ２プラズマエッチした後の特性を示す。第２図中曲
線Ｃは、曲線すと同一条件でエツチング時間を、３分３
０秒行った時の特性を示す。曲線す５曲線Ｃいずれの場
合も良好な○Ｎ／ＯＦＦ特性を示し、エツチング時間を
、２倍以上行ってもほとんど高抵抗半導体膜４にダメー
ジを与えず、再現性よい薄膜トランジスタが得られる。Curve a in FIG. 2 shows the characteristics before etching the N゛゛ crystalline silicon film, and shows that there is no 0N10FF ratio and the space between the source electrode 6 and the drain bridge 7 is just a resistance.
Curve b'A b in FIG. 2 indicates N° amorphous silicon film formation 5.
At a pressure of 0.6 TORR, power 60W, of flowffi
20 S CCM, :L 7 Characteristics after O2 plasma etching with an etching time of 1 minute and 30 seconds are shown. Curve C in Figure 2 shows that the etching time is 3 minutes and 3 minutes under the same conditions.
The characteristics when running for 0 seconds are shown. Curves 5 and 5 show good N/OFF characteristics, and even if the etching time is doubled or more, there is almost no damage to the high-resistance semiconductor film 4, and thin film transistors with good reproducibility can be obtained.
トランジスタ特性がよく、より安全な製造プロセスを得
るためには、高抵抗半導体膜は５００オングストローム
以下の膜厚で、かつ低抵抗半導体膜は２００オングスト
ローム以下の膜厚の方が本発明は、より有効である。In order to obtain good transistor characteristics and a safer manufacturing process, the present invention is more effective when the high resistance semiconductor film has a thickness of 500 angstroms or less, and the low resistance semiconductor film has a film thickness of 200 angstroms or less. It is.
本発明は以上説明したように、連続形成された高抵抗半
導体膜と低抵抗半導体膜において−、低抵抗半導体膜を
０２プラズマでエツチングすることにより、高抵抗半導
体膜が薄い膜厚（例えば５００オングストローム以下）
の時でも、ダメージが少なく、オーミックコンタクトの
よい、遮光膜のいらない薄膜トランジスタが、再現性よ
く高歩留まりで得られる。As explained above, in the present invention, in a high resistance semiconductor film and a low resistance semiconductor film that are continuously formed, the high resistance semiconductor film is etched with a thin film thickness (for example, 500 angstroms) by etching the low resistance semiconductor film with 02 plasma. below)
Even under these conditions, thin film transistors with little damage, good ohmic contact, and no light-shielding film can be obtained with good reproducibility and high yield.
第１図は、本発明による製造方法で作成した薄膜トラン
ジスタの断面図、第２図は、０□プラズマ工ツチ条件に
よるドレイン電ｍｌ。−ゲート電圧■。特性を示すグラ
フ、第３図は、従来の製造方法で作成した薄ＩＫ ）ラ
ンジスタの断面図を示す。
１・・絶縁基板
２・・ゲート電極
３・・ゲート絶縁膜
４・・高抵抗半導体膜
５・・低抵抗半導体膜
６・・ソース電極
７・ ・ドレイン電橋
以上
出願人 セイコー電子工業株式会社
？
１−光８月にＪ６製造力法ζイ乍八しｒ（薄膜トランジ
スタの上面図
第１図
酸素ブラスマエＶ号によ６ＪＤ−■特４土図第２図
従来の製造方法乞−作へ゛した
簿膜トランジスタの防面図
弔３図FIG. 1 is a cross-sectional view of a thin film transistor manufactured by the manufacturing method of the present invention, and FIG. 2 is a drain current ml under 0□ plasma processing conditions. −Gate voltage■. A graph showing the characteristics, FIG. 3, shows a cross-sectional view of a thin IK transistor manufactured by a conventional manufacturing method. 1. Insulating substrate 2. Gate electrode 3. Gate insulating film 4. High resistance semiconductor film 5. Low resistance semiconductor film 6. Source electrode 7. 1-J6 manufacturing method in August (Top view of thin film transistor) Diagram 3 of the membrane transistor shield
Claims (2)
、ゲート絶縁膜と、高抵抗半導体膜と、低抵抗半導体膜
と、ソース電極とドレイン電極からなる薄膜トランジス
タにおいて、前記ソース電極とドレイン電極をマスクの
一部として、前記低抵抗半導体膜を酸素プラズマでエッ
チングすることを特徴とする薄膜トランジスタの製造方
法。(1) In a thin film transistor consisting of at least a gate electrode, a gate insulating film, a high resistance semiconductor film, a low resistance semiconductor film, a source electrode and a drain electrode formed on an insulating substrate, the source electrode and the drain electrode are masked. A method for manufacturing a thin film transistor, comprising etching the low-resistance semiconductor film with oxygen plasma.
以下の膜厚で、かつ前記低抵抗半導体膜は、２００オン
グストローム以下の膜厚である特許請求の範囲第１項記
載の薄膜トランジスタの製造方法。(2) The method of manufacturing a thin film transistor according to claim 1, wherein the high resistance semiconductor film has a thickness of 500 angstroms or less, and the low resistance semiconductor film has a thickness of 200 angstroms or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26884985A JPS62128566A (en) | 1985-11-29 | 1985-11-29 | Manufacture of thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26884985A JPS62128566A (en) | 1985-11-29 | 1985-11-29 | Manufacture of thin film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62128566A true JPS62128566A (en) | 1987-06-10 |
Family
ID=17464119
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26884985A Pending JPS62128566A (en) | 1985-11-29 | 1985-11-29 | Manufacture of thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62128566A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6459863A (en) * | 1987-08-31 | 1989-03-07 | Matsushita Electric Ind Co Ltd | Semiconductor device |
| JPH02281633A (en) * | 1989-04-21 | 1990-11-19 | Casio Comput Co Ltd | Manufacture of thin film transistor |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57194533A (en) * | 1981-05-26 | 1982-11-30 | Nec Corp | Removing method for exposed silicon surface slowly controlling thickness of removed layer cleanly |
| JPS6042868A (en) * | 1983-08-18 | 1985-03-07 | Matsushita Electronics Corp | Manufacture of amorphous silicon thin film fet |
| JPS60170260A (en) * | 1984-02-14 | 1985-09-03 | Fujitsu Ltd | Manufacture of thin-film transistor |
| JPS60186063A (en) * | 1984-02-06 | 1985-09-21 | Sony Corp | Thin film transistor |
-
1985
- 1985-11-29 JP JP26884985A patent/JPS62128566A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57194533A (en) * | 1981-05-26 | 1982-11-30 | Nec Corp | Removing method for exposed silicon surface slowly controlling thickness of removed layer cleanly |
| JPS6042868A (en) * | 1983-08-18 | 1985-03-07 | Matsushita Electronics Corp | Manufacture of amorphous silicon thin film fet |
| JPS60186063A (en) * | 1984-02-06 | 1985-09-21 | Sony Corp | Thin film transistor |
| JPS60170260A (en) * | 1984-02-14 | 1985-09-03 | Fujitsu Ltd | Manufacture of thin-film transistor |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6459863A (en) * | 1987-08-31 | 1989-03-07 | Matsushita Electric Ind Co Ltd | Semiconductor device |
| JPH02281633A (en) * | 1989-04-21 | 1990-11-19 | Casio Comput Co Ltd | Manufacture of thin film transistor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100225098B1 (en) | Method of fabrication of thin transistor | |
| JPH0380226A (en) | Active matrix substrate for liquid crystal display element and production thereof | |
| JPH05235034A (en) | Manufacture of thin-film transistor | |
| JPS6251264A (en) | Manufcture of thin film transistor | |
| JPS6113670A (en) | Method of producing thin film field effect transistor and transistor obtained by same method | |
| JPS58190061A (en) | Amorphous silicon semiconductor device and manufacture thereof | |
| JPS62128566A (en) | Manufacture of thin film transistor | |
| JPH05165059A (en) | Manufacture of thin film transistor | |
| JPH0918006A (en) | Thin film transistor and manufacture thereof | |
| JPS61191072A (en) | Thin film transistor and manufacture thereof | |
| JP2692914B2 (en) | Method for manufacturing thin film transistor | |
| JP2621619B2 (en) | Method for manufacturing thin film transistor | |
| JPH03185840A (en) | Thin film transistor | |
| KR19990011352A (en) | A thin film transistor liquid crystal display device having a double gate insulating film and a method of manufacturing the same | |
| JP3210196B2 (en) | Thin film transistor and manufacturing method thereof | |
| JPS62172761A (en) | Amorphous silicon thin film transistor and manufacture thereof | |
| JPH02224254A (en) | Thin film transistor, manufacture thereof, matrix circuit substrate, and picture display using it | |
| JP2671898B2 (en) | Method for manufacturing thin film transistor | |
| JPS63172469A (en) | Thin film transistor | |
| JPH0732255B2 (en) | Method of manufacturing thin film transistor | |
| JPS63172470A (en) | Thin film transistor | |
| JPS61183970A (en) | Thin film transistor | |
| JPH05119351A (en) | Liquid crystal display device and production thereof | |
| KR950003942B1 (en) | Method of manufacturing thin film transistor for lcd | |
| KR970010689B1 (en) | Thin film transistor semiconductor device |