JPS60170260A - Manufacture of thin-film transistor - Google Patents
Manufacture of thin-film transistorInfo
- Publication number
- JPS60170260A JPS60170260A JP59025381A JP2538184A JPS60170260A JP S60170260 A JPS60170260 A JP S60170260A JP 59025381 A JP59025381 A JP 59025381A JP 2538184 A JP2538184 A JP 2538184A JP S60170260 A JPS60170260 A JP S60170260A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- source
- film
- amorphous silicon
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 238000000034 method Methods 0.000 claims abstract description 23
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 230000001681 protective effect Effects 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims abstract description 4
- 239000004065 semiconductor Substances 0.000 claims description 3
- 210000004907 gland Anatomy 0.000 claims description 2
- 238000010030 laminating Methods 0.000 claims description 2
- 238000000926 separation method Methods 0.000 claims 2
- 239000010408 film Substances 0.000 abstract description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 6
- 239000011521 glass Substances 0.000 abstract description 6
- 238000007373 indentation Methods 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 abstract 1
- 238000007493 shaping process Methods 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- VNNRSPGTAMTISX-UHFFFAOYSA-N chromium nickel Chemical compound [Cr].[Ni] VNNRSPGTAMTISX-UHFFFAOYSA-N 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 229910001120 nichrome Inorganic materials 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 238000007740 vapor deposition Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 239000011159 matrix material Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 1
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 229910018487 Ni—Cr Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000009834 vaporization Methods 0.000 description 1
- 230000008016 vaporization Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
Description
【発明の詳細な説明】 （ａ）発明の技術分野 本発明は薄膜トランジスタの製造方法に関する。[Detailed description of the invention] (a) Technical field of the invention The present invention relates to a method for manufacturing a thin film transistor.
（ｂ）技術の背景
本発明は、近時、極薄型、広面積の平面ディスプレイ装
置として着目される液晶ディスプレイデバイスに係、特
に該デバイス駆動の例えば７トリノクス構成のＩＴＯ腺
表示電極駆動をなす水素化アモルファス半導体素子から
なる能動スイッチ素子の形成手段に就いて提示したもの
である。(b) Background of the Technology The present invention relates to a liquid crystal display device that has recently attracted attention as an ultra-thin, wide-area flat display device. This paper presents a means for forming an active switching element made of an amorphous semiconductor element.
（Ｃ）従来技術と問題点
従来、液晶デバイスに於ｉＪる１１゛０電極（Ｊカ明な
表示電極）を制御駆動する薄膜トランジスタは。(C) Prior Art and Problems Conventionally, thin film transistors control and drive 11'0 electrodes (J clear display electrodes) in liquid crystal devices.
ディスプレイデバイス形成のガラス基板上に水素化アモ
ルファスシリコン（以−ト ａＳｉ と略記する）半導
体素子が使用されている。Hydrogenated amorphous silicon (hereinafter abbreviated as aSi) semiconductor elements are used on glass substrates to form display devices.
第１図は、ガラス基板にａ−５ｉ の薄膜トランシスタ
カＳ形成される従来方法を説明する要部プロセスを示す
断面図である。FIG. 1 is a cross-sectional view showing the main process for explaining a conventional method for forming an a-5i thin film transistor stacker S on a glass substrate.
■はガラス基板ａ上にゲート電極すがパターン蒸着され
た状態である。■ば前記パターン蒸着後。3 shows a state in which a gate electrode pattern is deposited on a glass substrate a. (2) After the pattern deposition.
窒化シリコンのゲート絶縁層Ｃと、厚さ１０００人の真
性ａ−５ｉ層ｄ、及びチャンネル部保護をなす厚さ２０
００人の酸化シリコン層ｅ （絶縁層）を２同一プラス
マ気相成圏装置（ＣＶＤ装置）により連続的に成膜した
状感、又■は、前記■に続いてその表面にスピンコード
してポジ形レジストｆ （マイクロポジット）を塗着し
た後、基板背面からの露光と。A gate insulating layer C of silicon nitride, an intrinsic a-5i layer d having a thickness of 1000 nm, and a thickness 20 mm forming a channel protection layer.
000 silicon oxide layer e (insulating layer) was continuously deposited using the same plasma vapor deposition device (CVD device). After applying a positive resist f (microposit), exposure is performed from the back of the substrate.
該昂光後のレシス］−現像及び弗酸・弗化アンモン・水
の混合液による酸化シリコン層ｅを工、チング処理した
状態である。Resis after the irradiation] - This is a state in which the silicon oxide layer e was developed and etched using a mixed solution of hydrofluoric acid, ammonium fluoride, and water.
更に、■は前記処理に続いて、ａ−５ｉ層とオーミック
コンタクトを取得する前記ＣＶＤ装置による厚さ約１０
０人のｎ＋ａ−５ｉ層ｇの成膜と、続いて厚さ約７００
人のニノう一ルクローＪ、、 （ＮｉＣｒ）層りが成膜
になるソーストレイン電極を蒸着装置により被着した状
態である。然る後、前記塗着のレジスト層ｆ側面の不連
続性を利用して該レジストの剥肖１１処理（リフトオフ
法）をして、同図■に示ずソースとドレイン電極が分離
されたトランジスタが形成される。Further, (2) is a thickness of about 10 mm formed by the CVD apparatus to obtain ohmic contact with the a-5i layer following the above treatment.
Deposition of 0 n+a-5i layer g, followed by a thickness of about 700
This is a state in which a source train electrode, in which a NiCr (NiCr) layer is formed, is deposited using a vapor deposition apparatus. Thereafter, the resist is subjected to a peeling process (lift-off method) by utilizing the discontinuity of the side surface of the applied resist layer f, and a transistor with the source and drain electrodes separated, as shown in (■) in the same figure, is fabricated. is formed.
か様な背面露光を用いた自己整合形ａ−５ｔ薄腺１−ラ
ンジスタの製造方法は、ポジ形レジストｆを用いるスタ
ガ型ソース・ドレイン電極をリフトオフ法により形成す
るため、 ｎ＋層を用いる際筒温成膜が不可能である。The method for manufacturing a self-aligned A-5T thin conductor transistor using variable back exposure is to form staggered source/drain electrodes using a positive resist f by a lift-off method. Hot film formation is not possible.
且つｎ＋層の段差被膜性が良いためリフトオフ法の歩留
りが不充分であるとバう欠点がある。又、コブラナー型
においては、前記欠点以前に薄膜トランジスタ製造上、
■要な界面であるゲート絶縁層とａ−３ｉ層との界面が
真空外にさらされると云う欠点がある。In addition, since the step filmability of the n+ layer is good, there is a drawback that the yield of the lift-off method is insufficient. In addition, in the Koblerner type, before the above-mentioned drawbacks, there are problems in manufacturing thin film transistors.
(2) There is a drawback that the interface between the gate insulating layer and the a-3i layer, which is an important interface, is exposed to the outside of vacuum.
（ｄ）発明の目的
本発明の目的は、ゲート絶縁層とａ−５ｉ層との界面生
成、 ａ−５ｉ層とソーストレイン電極との界面生成を
真空を破らないで生成すること、併せてゲート電極とソ
ースドレイン電極を自己整合法により位置合わせするこ
とにより安定な特性を持つ薄膜１−ランリスタを高精細
かつ大面積基板にに配置形成する製造方法を提示するこ
とである。(d) Purpose of the Invention The purpose of the present invention is to generate the interface between the gate insulating layer and the a-5i layer, and the interface between the a-5i layer and the source train electrode without breaking the vacuum. The object of the present invention is to present a manufacturing method for forming a thin film 1-run lister with stable characteristics on a high-definition, large-area substrate by aligning electrodes and source/drain electrodes by a self-alignment method.
（ｅ）発明の構成
前記目的は、ゲート電極形成の基板に、ゲート絶縁層、
動作半導体層としてのアモルファスシリコン（ａ−５ｉ
） Ｎ、該ａ−５ｉｌ−の表面側にソース・ルイン電
極膜を順次積層する構成の薄膜トランジスタに於いて、
前記のケート絶縁層、ａ−５ｉ層、 ｎ＋アモルファス
シリコン層、及びＴＴＯ電極層を同一の真空中で連続積
層する手段と、ネガレジストを用い目つ前記ゲート電極
をマスクとして基板背面から露光し現像したレジストパ
ターンにより ＩＴ（ｌ電極層及びｎ＋アモルファスシ
リコン層からなるソース並びにトレイン電極間のエツチ
ング分Ｆ４１１を行う手段と、により形成する薄膜トラ
ンジスタとして達成される。(e) Structure of the invention
Amorphous silicon (a-5i
) N, in a thin film transistor having a structure in which a source/ruin electrode film is sequentially laminated on the surface side of the a-5il-,
A means for successively laminating the gate insulating layer, the a-5i layer, the n+ amorphous silicon layer, and the TTO electrode layer in the same vacuum, and exposing and developing the substrate using a negative resist from the back side using the gate electrode as a mask. A thin film transistor formed by IT (means for performing etching F411 between source and train electrodes consisting of an l electrode layer and an n+ amorphous silicon layer) is achieved using the resist pattern.
（ｆ）発明の実施（ｔｌｌ
本発明は、薄膜１−ランリスタのソース・トレ・イン電
極を、）喚厚さ１００人程度の半透明性ｎ＋アモルファ
スシリコン層と■１゛０導電膜との二層膜構成とする。(f) Implementation of the Invention (tll) The present invention provides a thin-film 1-run lister with source-train-in electrodes consisting of a translucent n+ amorphous silicon layer with a thickness of about 100 mm and a 10 conductive film. It has a layered structure.
これによりゲート絶縁層とａ−５ｉ層の界面。This creates an interface between the gate insulating layer and the a-5i layer.
更に、 ａ−３ｉ層とソース・ｌ” ｌ／イン電極の界
面が。Furthermore, the interface between the a-3i layer and the source/l''l/in electrode.
共に同一真空中で生成され、然る後背面露光が出来る。Both are produced in the same vacuum, allowing subsequent back exposure.
またネガ型レジストの使用によりソース・トレイン電極
がエツチングでパターンニング出来、該バターニング形
成の歩留り低−トを抑えることが出来る。Further, by using a negative type resist, the source/train electrode can be patterned by etching, and a low yield of patterning can be suppressed.
以下９本発明の製造方法を、第２図薄膜トランジスタ断
面を示すプロセス図を参照し２ながら詳細に説明する。Hereinafter, the manufacturing method of the present invention will be explained in detail with reference to FIG. 2, a process diagram showing a cross section of a thin film transistor.
第２図プロセス図中７■はガラス基板ａの表面にニッケ
ルクローム（ＮｉＣｒ＞よりなるデー１−電極すが欣厚
さ略７００人の厚さにパターン蒸着された状態である。In the process diagram of FIG. 2, 7.sub.1 indicates a state in which a pattern of electrodes made of nickel chrome (NiCr) is deposited on the surface of a glass substrate a to a thickness of approximately 700 mm.
■は前記パターン蒸宥後、窒化シリコン（ＳｉＮ ：
Ｈ）のり“−１・絶縁層Ｃと、１００（１人１１さの真
性ａ−５ｉｆｆｉｄとを順次被着して、更にその上面に
厚さ１００人程度のｎ＋アモルファスシリコン層１と厚
さ１０００人のＴＴＯ導電欣五との二層膜構成のソース
・ドレイン電極を順次被着した状態である。前記ｈｉＩ
！ｊ次被着するデー１−絶縁層Ｃ９真１！＋ａＳｉｌｔ
ｉｆｄ、及びｎ＋アモルファスシリコン層１は。(2) After the pattern vaporization, silicon nitride (SiN:
H) Insulating layer C with glue "-1" and intrinsic a-5 iffid with a thickness of 100 (11 mm) are sequentially deposited, and on top of that, an n+ amorphous silicon layer 1 with a thickness of about 100 mm and an n+ amorphous silicon layer 1 with a thickness of 1000 mm This is a state in which source and drain electrodes with a two-layer film structure are sequentially deposited with human TTO conductive material.
! jth deposited day 1-insulating layer C9 true 1! +aSilt
ifd, and n+ amorphous silicon layer 1.
（Ｉ＋■れも同一のプラスマＤＶＤ （Ｃｈｅｍｉｃａ
ｌ Ｖａｐｏｒ Ｄｅｐｏｓｉｔｉｏｎ ）装置により
連続的に成膜し得る。又厚さ１０００人のＩＴＯ専電Ｂ
’Ａ ｉは、電子ビーム蒸着法やイオンブレーティング
法及びスパッタ法により成膜Ｌ２得る。(I+■ also the same plasma DVD (Chemica
The film can be continuously formed using a Vapor Deposition (Vapor Deposition) device. Also, 1000 thick ITO electric wire B
'A i is formed into a film L2 by an electron beam evaporation method, an ion blating method, or a sputtering method.
プロセス図中■は、前記■に続いてその表面にスピンオ
フ法でネガ形しジストｊを塗着した後。In the process diagram, ■ is after the surface is negative-shaped by a spin-off method and the resist j is applied following the above-mentioned step (■).
基板ａ背面からの背面露光（上方向矢印参照）をなす状
態と、併せて前記背面露光後、現像処理により図示１（
の凹みが形成された状態を示す。In addition to the state of back exposure from the back side of the substrate a (see the upward arrow), the state shown in FIG. 1 (
This shows the state in which a dent has been formed.
■は、前記凹み（チャンネル）ｋの底面にあるＩＴＯ膜
導電腺ｉと０１アモルファスシリコンＮ１の温度で該隔
離のチャンネル部面に対して酸化シリニｌン１１費（Ｓ
ｉＯ２，股厚約２０００人）の絶縁保護膜ｒｎを成膜し
た状態である。(2) shows the ITO film conductive gland i on the bottom surface of the recess (channel) k and the silicon oxide layer 11 (S) applied to the isolated channel surface at the temperature of the amorphous silicon N1.
This is the state in which an insulating protective film rn of iO2, thickness of about 2,000 mm) has been formed.
史に、■はりフトオフ法によりチャンネル部ｌ（以外の
保護１ｆ！Ｉｔ！ｍ−ｔｌ−除去した状態図である。This is a state diagram in which the protection 1f!It!m-tl- is removed by the beam lift-off method.
前記本発明の実施例手段によりゲート絶縁層とａ−３ｉ
層、該ａ −Ｓ ｉ層とソース・ドレイン電極との形成
が真空を破ることなく、従ってクリーンな表面状態を維
持して接蕃すること力咄来る為、マトリックス電極を構
成するセル駆動の安定なスイッチングトランジスタが実
現可能となる。According to the embodiment of the present invention, the gate insulating layer and the a-3i
Since the formation of the a-Si layer and the source/drain electrodes can be carried out without breaking the vacuum and maintaining a clean surface condition, the cell drive that constitutes the matrix electrode is stable. This makes it possible to realize a switching transistor with a wide range of functions.
（ｇ）発明の効果
以−ヒ、詳細に説明した本発明の薄膜トランジスタの製
造方法によれば、ゲート絶縁層とａ、ｓｉ層の界面、及
びａ−３ｉ・層とソース・トレイン電極の界面が同一・
の真空中で形成され、かつセルフアライメント法が導入
されるので、液晶表示のセル駆動をなす信頼性の商い為
精細な目つ大型の踏欣マトリノクススイノチンクアレイ
が製造可能となる。(g) Effects of the Invention According to the method for manufacturing a thin film transistor of the present invention explained in detail, the interface between the gate insulating layer and the a-3i layer and the si layer, and the interface between the a-3i layer and the source/train electrode Same/
Since it is formed in a vacuum and a self-alignment method is introduced, it is possible to manufacture a large scale matrix matrix array with fine details for reliability in driving cells of a liquid crystal display.
第１図は従来の薄膜トランジスタ形成方法を説明するプ
ロセス要部の断面図、第２図は本発明の薄膜トランジス
タ形成プロセス要部手段を示す断面図である。
図中、ａはガラス基板、ｂはデー１−電極、Ｃは窒化シ
リコン層（ＳｉＮ ： Ｈ） 、ｄは真性アモルファス
シリコン（ａ−５＋ ）層、ｅば酸化シリコン層（Ｓｉ
０２）、ｆはレジスｌ”ｌｌＬ ｇとＩはｎ” ａ−５
ｉ層、ｈばニッケルクローム（ＮｉＣｒ）組成のソース
・トレイン電極、ｉはＩＴＯ膜糾成のソース・ドレイン
電極、にはチャンネル部、及びｍばｌ（の保護膜 １
区
筈 ２ 圀
■
■
■
■
■
■
／／ Ｖｌｕ ｔ＋ ７７ ＼＼／ｌいＩ／ブ
えFIG. 1 is a cross-sectional view of a main part of a process for explaining a conventional method for forming a thin film transistor, and FIG. 2 is a cross-sectional view of a main part of a process for forming a thin film transistor according to the present invention. In the figure, a is a glass substrate, b is a D1-electrode, C is a silicon nitride layer (SiN:H), d is an intrinsic amorphous silicon (a-5+) layer, and e is a silicon oxide layer (SiN).
02), f is Regis l”llL g and I are n” a-5
i layer, h is source/train electrode of nickel chromium (NiCr) composition, i is source/drain electrode of ITO film, channel part, and protective film of mbal (1)
Ward must 2 圀 ■ ■ ■ ■ ■ ■ // Vlu t+ 77 \\/lI/Bue
Claims (1)
）Ｉ’ｍ、該ａ−５ｉ層の表面側にソース・トレイン電
極腺を順次積層する構成の薄膜トランジスタに於いて、
前記のゲート絶縁層、ａ−５ｉ層 ｎ ＋アモルファス
シリコン１ｉ、及びＩＴＯ電極層を同一の真空中で連続
積層する手段と、不ガレジストを用い目一つ前記ゲート
電極をマスクとして基板背面から露光し現像したレタス
トパターンにより ＩＴＯ電極層及びｎ＋アモルファス
シリコン層からなるソース）１１トびにトレ・イン電極
間のエツチング分離を行う手段と、により形成すること
を特徴とする薄１１史トランジスタの製造方法。 く２）前記ＩＴＯ電極層及びｎ＋アモルファスシリコン
層からなるソース並びにＩレイン電極間のエツチング分
離部分の表向にリフトオフ法によりチャンネルの保護欣
を形成することを特徴とする特許請求の範囲第１項記載
の薄膜トランジスタの製造方法。(1) Qi-l-insulating layer on the substrate for forming the gate electrode. Amorphous silicon (aSi) as a semiconductor layer
) I'm, in a thin film transistor having a structure in which source and train electrode glands are sequentially laminated on the surface side of the a-5i layer,
Using means for successively laminating the gate insulating layer, the a-5i layer n + amorphous silicon 1i, and the ITO electrode layer in the same vacuum, and a non-galvanic resist, the first step was to expose the substrate to light from the back side using the gate electrode as a mask. 1. A method for manufacturing a thin 11-thickness transistor, characterized in that it is formed using a developed retaste pattern, and means for performing etching separation between a source 11 and a train electrode consisting of an ITO electrode layer and an n+ amorphous silicon layer. (2) A protective shield for the channel is formed by a lift-off method on the surface of the etched separation portion between the source and I-rain electrodes made of the ITO electrode layer and the n+ amorphous silicon layer. A method of manufacturing the thin film transistor described above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59025381A JPS60170260A (en) | 1984-02-14 | 1984-02-14 | Manufacture of thin-film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59025381A JPS60170260A (en) | 1984-02-14 | 1984-02-14 | Manufacture of thin-film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60170260A true JPS60170260A (en) | 1985-09-03 |
| JPH0464181B2 JPH0464181B2 (en) | 1992-10-14 |
Family
ID=12164277
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59025381A Granted JPS60170260A (en) | 1984-02-14 | 1984-02-14 | Manufacture of thin-film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60170260A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61139069A (en) * | 1984-12-10 | 1986-06-26 | Fuji Xerox Co Ltd | Thin-film transistor and manufacture thereof |
| JPS62128566A (en) * | 1985-11-29 | 1987-06-10 | Seiko Instr & Electronics Ltd | Manufacture of thin film transistor |
| JPS62140467A (en) * | 1985-12-13 | 1987-06-24 | Sharp Corp | Manufacture of thin-film transistor |
-
1984
- 1984-02-14 JP JP59025381A patent/JPS60170260A/en active Granted
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61139069A (en) * | 1984-12-10 | 1986-06-26 | Fuji Xerox Co Ltd | Thin-film transistor and manufacture thereof |
| JPS62128566A (en) * | 1985-11-29 | 1987-06-10 | Seiko Instr & Electronics Ltd | Manufacture of thin film transistor |
| JPS62140467A (en) * | 1985-12-13 | 1987-06-24 | Sharp Corp | Manufacture of thin-film transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0464181B2 (en) | 1992-10-14 |
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| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |