JPH0680685B2 - Thin film transistor and manufacturing method thereof - Google Patents
Thin film transistor and manufacturing method thereofInfo
- Publication number
- JPH0680685B2 JPH0680685B2 JP61311828A JP31182886A JPH0680685B2 JP H0680685 B2 JPH0680685 B2 JP H0680685B2 JP 61311828 A JP61311828 A JP 61311828A JP 31182886 A JP31182886 A JP 31182886A JP H0680685 B2 JPH0680685 B2 JP H0680685B2
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- source
- insulating film
- gate electrode
- amorphous semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000010409 thin film Substances 0.000 title claims description 36
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000010408 film Substances 0.000 claims description 53
- 229910052751 metal Inorganic materials 0.000 claims description 25
- 239000002184 metal Substances 0.000 claims description 25
- 239000004065 semiconductor Substances 0.000 claims description 16
- 229920002120 photoresistant polymer Polymers 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 15
- 229910021332 silicide Inorganic materials 0.000 claims description 13
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 13
- 239000012535 impurity Substances 0.000 claims description 8
- 238000000059 patterning Methods 0.000 claims description 6
- 229910021417 amorphous silicon Inorganic materials 0.000 description 17
- 238000000034 method Methods 0.000 description 7
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 5
- 229910052804 chromium Inorganic materials 0.000 description 5
- 239000011651 chromium Substances 0.000 description 5
- 239000011521 glass Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910004205 SiNX Inorganic materials 0.000 description 1
- 229910003070 TaOx Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- QRRWWGNBSQSBAM-UHFFFAOYSA-N alumane;chromium Chemical compound [AlH3].[Cr] QRRWWGNBSQSBAM-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- VNNRSPGTAMTISX-UHFFFAOYSA-N chromium nickel Chemical compound [Cr].[Ni] VNNRSPGTAMTISX-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78663—Amorphous silicon transistors
- H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は自己整合型薄膜トランジスタおよびその製造方
法に関する。The present invention relates to a self-aligned thin film transistor and a method for manufacturing the same.
近年液晶フラットディスプレイ、あるいは長尺イメージ
センサの駆動デバイスとして使われる薄膜トランジスタ
の研究開発が盛んに行われている。In recent years, research and development of thin film transistors used as driving devices for liquid crystal flat displays or long image sensors have been actively conducted.
フラットディスプレイの画品質向上やイメージセンサの
高速化のために、ゲート金属、ソース・ドレイン間容量
の低減された自己整合型薄膜トランジスタが強く望まれ
ている（例えば、電子通信学会電子デバイス研究会技術
報告、ED−84−70（1984））。In order to improve the image quality of flat displays and the speed of image sensors, self-aligned thin film transistors with reduced gate metal and source-drain capacitance are strongly desired (eg, IEICE Technical Report on Electronic Devices). , ED-84-70 (1984)).
また、この自己整合型薄膜トランジスタは、トランジス
タ形成時の目合わせ精度を軽減できるため、上記大面積
デバイスを形成するときに有用な素子であり、特に非晶
質シリコンを用いた自己整合型薄膜トランジスタは非晶
質シリコンが低温処理で大面積に形成できることや、抵
抗が高く、オフ電流が小さい等の利点を有するため、特
に強くその開発を急がれている。Further, this self-aligned thin film transistor is an element useful when forming the above-mentioned large-area device because it can reduce the alignment accuracy at the time of forming the transistor. In particular, the self-aligned thin film transistor using amorphous silicon is not Since crystalline silicon can be formed in a large area by low-temperature treatment, and has advantages such as high resistance and small off-current, its development is particularly urgently needed.
第３図（ｄ）に従来例の非晶質シリコンを用いた自己整
合型薄膜トランジスタの断面図を示す（電子通信学会電
子デバイス研究会技術報告、ED−83−70（1983））。こ
の構造の薄膜トランジスタの製造工程を第３図（ａ）〜
（ｄ）に示す。FIG. 3 (d) shows a cross-sectional view of a conventional self-aligned thin film transistor using amorphous silicon (Technical Report of Electronic Device Research Society of Electronic Communication Society of Japan, ED-83-70 (1983)). The manufacturing process of the thin film transistor having this structure is shown in FIG.
It shows in (d).
まず、第３図（ａ）に示すように、ガラス基板10にゲー
ト金属を形成し、パターニングし、ゲート電極11に成形
する。この上にゲート絶縁膜12、非晶質シリコン膜13を
順次形成し、所望の大きさにパターニングする。この上
にフォトレジスト15を塗布し、ガラス基板10側から紫外
光16を照射することによりフォトレジスト15を感光させ
る。このとき、ゲート金属がマスクとなってゲート金属
上のフォトレジスト15は感光しない。これを現像する
と、第３図（ｂ）に示すようにゲート金属の直上のみに
フォトレジスト６が残る。次に第３図（ｃ）に示すよう
に、この上にn+非晶質シリコン膜22を形成し、ソース・
ドレイン電極用金属19を蒸着する。次に、フォトレジス
ト15を除去し、不要なn+非晶質シリコン膜およびソース
・ドレイン用電極金属をリフトオフして取除けば第３図
（ｄ）のように自己整合型非晶質シリコン薄膜トランジ
スタが完成する。First, as shown in FIG. 3A, a gate metal is formed on the glass substrate 10, patterned, and formed into a gate electrode 11. A gate insulating film 12 and an amorphous silicon film 13 are sequentially formed on this and patterned to a desired size. A photoresist 15 is applied on this, and ultraviolet light 16 is irradiated from the glass substrate 10 side to expose the photoresist 15 to light. At this time, the gate metal serves as a mask and the photoresist 15 on the gate metal is not exposed. When this is developed, the photoresist 6 remains only on the gate metal, as shown in FIG. 3 (b). Next, as shown in FIG. 3 (c), an n + amorphous silicon film 22 is formed on this,
The metal 19 for the drain electrode is deposited. Next, if the photoresist 15 is removed and unnecessary n + amorphous silicon film and source / drain electrode metal are lifted off and removed, as shown in FIG. 3D, a self-aligned amorphous silicon thin film transistor is formed. Is completed.
しかしながら、第３図（ａ）〜（ｄ）に示した薄膜トラ
ンジスタは特性的には満足できるものの、n+非晶質シリ
コン膜およびソース・ドレイン用電極金属のリフトオフ
工程が難しく、これが歩留り低下を来たし、生産的に問
題がある。However, although the thin film transistors shown in FIGS. 3 (a) to 3 (d) are characteristically satisfactory, the lift-off process of the n + amorphous silicon film and the source / drain electrode metal is difficult, which causes a decrease in yield. , Productive problem.
本発明の目的は上述した非晶質シリコン薄膜トランジス
タの製造におけるリフトオフ工程を含まず、安定に製造
が行える自己整合型薄膜トランジスタおよびその製造方
法を提供することにある。An object of the present invention is to provide a self-aligned thin film transistor that does not include the lift-off process in manufacturing the above-described amorphous silicon thin film transistor and can be stably manufactured, and a manufacturing method thereof.
上記目的を達成するために、本発明は、絶縁性基板上に
形成されたゲート電極と、前記ゲート電極を覆うように
形成された第１の透明絶縁膜と、前記第１の透明絶縁膜
上に形成された島状の非晶質半導体膜と、前記非晶質半
導体薄膜内に形成されたソース・ドレイン領域と電気的
に接触するにように形成されたソース・ドレイン金属電
極からなる逆スタガ型薄膜トランジスタにおいて、前記
非晶質半導体膜上に形成された前記ゲート電極と同じ形
状の第２の絶縁膜下を除いた非晶質半導体薄膜の全部ま
たは前記第２の絶縁膜下を除いた前記絶縁性基板の非晶
質半導体表面部分に不純物を含むソース・ドレイン領域
を形成し、前記ソース・ドレイン領域の表面に前記第２
の絶縁膜と前記ソース・ドレイン金属電極の間に前記第
２の絶縁膜と自己整合的に形成されたシリサイドを設け
たものである。In order to achieve the above object, the present invention provides a gate electrode formed on an insulating substrate, a first transparent insulating film formed so as to cover the gate electrode, and a first transparent insulating film on the first transparent insulating film. An inverted stagger consisting of an island-shaped amorphous semiconductor film formed on the substrate and source / drain metal electrodes formed so as to make electrical contact with the source / drain regions formed in the amorphous semiconductor thin film. -Type thin film transistor, the amorphous semiconductor thin film except the portion below the second insulating film having the same shape as the gate electrode formed on the amorphous semiconductor film, or the portion excluding the portion below the second insulating film Source / drain regions containing impurities are formed on the surface of the amorphous semiconductor of the insulating substrate, and the second source / drain regions are formed on the surface of the source / drain regions.
And a silicide formed in a self-aligned manner with the second insulating film is provided between the insulating film and the source / drain metal electrode.
また、上記目的を達成するために、本発明は、絶縁性基
板上にゲート電極を形成する工程と、前記ゲート電極を
覆うように第１の透明絶縁膜、非晶質半導体薄膜、第２
の透明絶縁膜を形成する工程と、前記非晶質半導体薄膜
を島状にパターニングする工程と、前記ゲート電極をマ
スクとして前記絶縁性基板側から露光して前記第２の絶
縁膜をパターニングする工程と、パターニングされた前
記第２の絶縁膜またはフォトレジストをマスクとして前
記非晶質半導体薄膜の一部に不純物を導入する工程と、
ソース・ドレイン金属電極を形成した後、前記ゲート電
極上部の第２の透明絶縁膜と重ならないように離して、
且つ、表面に露出したソース・ドレイン領域表面に形成
されたシリサイドを残して前記ソース・ドレイン金属電
極をパターニングし、前記ソース・ドレイン金属電極を
形成する工程を設けたものである。In order to achieve the above object, the present invention provides a step of forming a gate electrode on an insulating substrate, a first transparent insulating film, an amorphous semiconductor thin film, and a second transparent insulating film so as to cover the gate electrode.
Forming a transparent insulating film, patterning the amorphous semiconductor thin film in an island shape, and exposing the insulating substrate side using the gate electrode as a mask to pattern the second insulating film. And a step of introducing impurities into a part of the amorphous semiconductor thin film using the patterned second insulating film or photoresist as a mask,
After forming the source / drain metal electrodes, they are separated so as not to overlap the second transparent insulating film on the gate electrode,
In addition, the step of forming the source / drain metal electrode by patterning the source / drain metal electrode while leaving the silicide formed on the surface of the source / drain region exposed on the surface is provided.
第１図（ａ），（ｂ）において、ソース・ドレイン領域
17はゲート電極11とほぼ同形状に形成された第２の絶縁
膜14によりゲート電極11と自己整合的に形成されてお
り、このためソース・ドレイン領域とゲート金属の重な
り容量はほとんどなく、重なり容量のばらつきによる液
晶ディスプレイの高画品質やイメージセンサにおけるト
ランジスタスイッチ動作による雑音の低減が図られる。In FIGS. 1A and 1B, the source / drain regions
17 is formed in a self-aligned manner with the gate electrode 11 by the second insulating film 14 formed in substantially the same shape as the gate electrode 11. Therefore, there is almost no overlap capacitance between the source / drain region and the gate metal, and there is no overlap. Higher image quality of the liquid crystal display due to variations in capacitance and noise due to transistor switch operation in the image sensor can be reduced.
トランジスタオン時にはチャネルとソース・ドレイン電
極20はシリサイド層21により接続される。このシリサイ
ド層21は面積抵抗が５〜100Kオーム／□と小さいため、
比較的抵抗の高い非晶質シリコンソース・ドレイン領域
17（108〜109オーム／□）のみの場合に比べてオン抵抗
の低下はなく、デバイス動作が可能になる。When the transistor is on, the channel and the source / drain electrode 20 are connected by the silicide layer 21. Since this silicide layer 21 has a small sheet resistance of 5 to 100 K ohms / square,
Amorphous silicon source / drain region with relatively high resistance
Compared with the case of only 17 (10 8 to 10 9 ohm / □), there is no decrease in on-resistance, and device operation is possible.
また、第２図（ａ）〜（ｄ）において、ゲート電極11を
マスクとして背面露光により作られた第２の絶縁膜14を
マスクとして不純物の導入が図られ、この上に形成され
るシリサイド層21を利用して自己整合型トランジスタが
形成されるため、従来のフォトレジストのリフトオフ工
程によるものと比べて安定にデバイス形成が可能にな
る。In addition, in FIGS. 2A to 2D, impurities are introduced by using the second insulating film 14 formed by backside exposure with the gate electrode 11 as a mask, and a silicide layer formed thereon Since 21 is used to form a self-aligned transistor, a device can be formed more stably than in the conventional photoresist lift-off process.
さらに、ソース・ドレイン電極のパターニングにはゲー
ト電極とソース・ドレイン電極のパターンが重ならなく
てもよいため、目合わせ精度は厳しくなく、大面積デバ
イスには適したトランジスタである。Further, the patterning of the source / drain electrodes does not need to overlap the patterns of the gate electrode and the source / drain electrodes, so that the alignment accuracy is not severe and the transistor is suitable for a large area device.
次に本発明の実施例について図面を参照にして説明す
る。第１図（ａ），（ｂ）は本発明に係る薄膜トランジ
スタを示す平面図と断面図、第２図（ａ）〜（ｄ）は本
発明に係る薄膜トランジスタの製造方法を工程順に示し
た素子の断面図である。第１図（ａ），（ｂ）および第
２図（ａ）〜（ｄ）を用いて本発明の実施例を説明す
る。Next, embodiments of the present invention will be described with reference to the drawings. 1 (a) and 1 (b) are a plan view and a cross-sectional view showing a thin film transistor according to the present invention, and FIGS. 2 (a) to 2 (d) are an element showing a method of manufacturing the thin film transistor according to the present invention in order of steps. FIG. An embodiment of the present invention will be described with reference to FIGS. 1 (a) and (b) and FIGS. 2 (a) to (d).
まず、絶縁性基板としてのガラス基板10上にゲート金属
としてクロミウムを100nm蒸着し、パターニングしてゲ
ート電極11に成形する。次に、ゲート絶縁膜12としてSi
Nxを300nm、非晶質シリコン膜13を50nm、第２の絶縁膜1
4としてSiOx14を100nmプラズマCVD法により形成した
後、非晶質シリコン膜13と第２の絶縁膜14を島状にパタ
ーニングする。さらに、フォトレジスト15を被覆した
後、ガラス基板10側から紫外光16を照射してゲート電極
をマスクとしてフォトレジスト15を感光させる（第２図
（ａ））。このとき紫外光の照射時間は５〜10分でゲー
ト金属とほぼ同じ形状にフォトレジスト15を感光するこ
とができた。First, 100 nm of chromium as a gate metal is vapor-deposited on a glass substrate 10 as an insulating substrate, and patterned to form a gate electrode 11. Next, Si is used as the gate insulating film 12.
Nx 300 nm, amorphous silicon film 13 50 nm, second insulating film 1
After forming SiOx 14 as 100 nm by the 100 nm plasma CVD method, the amorphous silicon film 13 and the second insulating film 14 are patterned into an island shape. Further, after coating the photoresist 15, ultraviolet light 16 is irradiated from the glass substrate 10 side to expose the photoresist 15 using the gate electrode as a mask (FIG. 2 (a)). At this time, the irradiation time of the ultraviolet light was 5 to 10 minutes, and the photoresist 15 could be exposed in the same shape as the gate metal.
フォトレジスト15をパターニングした後、フォトレジス
ト15をマスクにして第２の絶縁膜14をパターニングし、
該第２の絶縁膜14あるいはフォトレジスト15をマスクに
して不純物原子18として燐を非晶質シリコン膜13中に導
入した。不純物の導入としてはイオン注入により燐を５
×1015cm2,40kVで非晶質シリコン膜13中に打込んだ（第
２図（ｂ））。続いてソース・ドレイン電極用金属19と
してクロミウムを150nm蒸着する。（第２図（ｃ））。
このとき、ソース・ドレイン領域17の非晶質シリコン膜
13とクロミウムの間にはシリサイド層21が形成される
が、確実にシリサイド層を形成するためには150℃20分
間アニールするとよい。このときのシリサイド層21の抵
抗は約10kオーム／□と低抵抗であった。その後、ソー
ス・ドレイン電極20をパターニングすることにより不要
なソース・ドレイン電極用金属19を除去することにより
薄膜トランジスタが完成される（第２図（ｄ））。この
場合、クロミウムをエッチングするときにはシリサイド
層21はエッチングされないようにする必要がある。この
とき、ソース・ドレイン電極20間の長さはゲート電極11
の長さより大きくてよい（例えばゲート電極長10nm（チ
ャネル長）に対しソース・ドレイン間長25nmであっ
た。）。After patterning the photoresist 15, the second insulating film 14 is patterned using the photoresist 15 as a mask,
Phosphorus was introduced into the amorphous silicon film 13 as impurity atoms 18 using the second insulating film 14 or the photoresist 15 as a mask. For introducing impurities, phosphorus is added by ion implantation.
Implanted into the amorphous silicon film 13 at × 10 15 cm 2 and 40 kV (Fig. 2 (b)). Then, as the source / drain electrode metal 19, chromium is deposited to a thickness of 150 nm. (FIG. 2 (c)).
At this time, the amorphous silicon film in the source / drain region 17
Although the silicide layer 21 is formed between 13 and chromium, it is preferable to anneal at 150 ° C. for 20 minutes to surely form the silicide layer. At this time, the resistance of the silicide layer 21 was as low as about 10 kΩ / □. Then, the source / drain electrodes 20 are patterned to remove the unnecessary source / drain electrode metal 19 to complete the thin film transistor (FIG. 2 (d)). In this case, it is necessary to prevent the silicide layer 21 from being etched when etching chromium. At this time, the length between the source / drain electrode 20 is equal to the gate electrode 11
The length may be larger than the length (for example, the gate electrode length is 10 nm (channel length) and the source-drain length is 25 nm).
本薄膜トランジスタの製造においては、第１の絶縁膜12
としてSiOx,第２の絶縁膜14としてSiOxを使用したが、S
iOx,SiNx,TaOx等透明絶縁膜ならば使用可能である。ま
た形成法においてもスパッタ法、光CVD法等使用可能で
ある。In manufacturing the thin film transistor, the first insulating film 12
Although SiOx is used as the second insulating film 14 and SiOx is used as the second insulating film 14,
Any transparent insulating film such as iOx, SiNx, TaOx can be used. In addition, as a forming method, a sputtering method, an optical CVD method, or the like can be used.
また、ソース・ドレイン電極用金属19としてはクロミウ
ムの他、ニッケル，モリブデン，バラヂウム等でもよ
く、クロミウム−アルミニウム，クロミウム−ニッケ
ル，ニッケル−金等の積層構造、または合金でも可能で
ある。In addition to chromium, the source / drain electrode metal 19 may be nickel, molybdenum, palladium, or the like, and may have a laminated structure of chromium-aluminum, chromium-nickel, nickel-gold, or an alloy.
以上説明したように本発明の製造方法においてはその工
程の中にリフトオフ工程が含まれていないため、従来と
比べて歩留りよく自己整合型薄膜トランジスタを形成す
ることができる。As described above, in the manufacturing method of the present invention, the lift-off process is not included in the process, so that the self-aligned thin film transistor can be formed with a higher yield than in the conventional case.
また、第１図（ａ），（ｂ）の構造から分かるようにゲ
ート電極と自己整合的に形成されたソース・ドレイン領
域とシリサイド層のためにチャネル部とソース・ドレイ
ン電極が低抵抗にてつながり、実際に形成された薄膜ト
ランジスタではチャネル幅40μm,チャネル長10μｍの素
子において、ソース・ドレイン間に10V,ゲート電圧に15
V印加したオン電流は２〜４×10-6A,移動度0.2〜0.4cm2
/v・secと非晶質シリコントランジスタとして十分な特
性を有しており、またオフ電流も２〜８×10-12Ａと十
分小さく、液晶ディスプレイやイメージセンサに使える
ことが明らかになった。As can be seen from the structures of FIGS. 1 (a) and 1 (b), the channel portion and the source / drain electrodes have low resistance because of the source / drain regions and the silicide layer formed in self-alignment with the gate electrode. In an actually formed thin film transistor, a device with a channel width of 40 μm and a channel length of 10 μm has a source-drain voltage of 10 V and a gate voltage of 15 μm.
V-applied on-current is 2 to 4 × 10 -6 A, mobility 0.2 to 0.4 cm 2
It has a sufficient characteristic of / v · sec as an amorphous silicon transistor, and has a sufficiently small off-current of 2 to 8 × 10 −12 A, which makes it clear that it can be used for liquid crystal displays and image sensors.
さらに、本発明によれば自己整合型トランジスタが得ら
れるため、寄生容量の低減ができ、デバイスの高性能化
を実現できる効果を有するものである。Furthermore, according to the present invention, a self-aligned transistor can be obtained, so that the parasitic capacitance can be reduced and the performance of the device can be improved.
第１図（ａ）は本発明の自己整合型薄膜トランジスタを
示す平面図、（ｂ）は同断面図、第２図（ａ）〜（ｄ）
は本発明の自己整合型薄膜トランジスタの製造プロセス
を示す断面図、第３図（ａ）〜（ｄ）は従来例の自己整
合型薄膜トランジスタの製造プロセスを示す断面図であ
る。 10…ガラス基板、11…ゲート電極 12…第１の絶縁膜、13…非晶質シリコン膜 14…第２の絶縁膜、15…フォトレジスト 16…紫外光、17…ソース・ドレイン領域 18…不純物原子、19…ソース・ドレイン電極用金属 20…ソース・ドレイン電極、21…シリサイド層 22…n+非晶質シリコン層1A is a plan view showing a self-aligned thin film transistor of the present invention, FIG. 1B is a sectional view of the same, and FIGS. 2A to 2D.
Is a sectional view showing a manufacturing process of the self-aligned thin film transistor of the present invention, and FIGS. 3A to 3D are sectional views showing a manufacturing process of a conventional self-aligned thin film transistor. 10 ... Glass substrate, 11 ... Gate electrode 12 ... First insulating film, 13 ... Amorphous silicon film 14 ... Second insulating film, 15 ... Photoresist 16 ... UV light, 17 ... Source / drain region 18 ... Impurity Atom, 19 ... Source / drain electrode metal 20 ... Source / drain electrode, 21 ... Silicide layer 22 ... n + Amorphous silicon layer
Claims (2)
前記ゲート電極を覆うように形成された第１の透明絶縁
膜と、前記第１の透明絶縁膜上に形成された島状の非晶
質半導体膜と、前記非晶質半導体薄膜内に形成されたソ
ース・ドレイン領域と電気的に接触するように形成され
たソース・ドレイン金属電極からなる逆スタガ型薄膜ト
ランジスタにおいて、前記非晶質半導体膜上に形成され
た前記ゲート電極と同じ形状の第２の絶縁膜下を除いた
非晶質半導体薄膜の全部または前記第２の絶縁膜下を除
いた前記絶縁性基板の非晶質半導体表面部分に不純物を
含むソース・ドレイン領域を形成し、前記ソース・ドレ
イン領域の表面に前記第２の絶縁膜と前記ソース・ドレ
イン金属電極の間に前記第２の絶縁膜と自己整合的に形
成されたシリサイドを設置したことを特徴とする薄膜ト
ランジスタ。1. A gate electrode formed on an insulating substrate,
A first transparent insulating film formed to cover the gate electrode, an island-shaped amorphous semiconductor film formed on the first transparent insulating film, and formed in the amorphous semiconductor thin film. In an inverted staggered thin film transistor including source / drain metal electrodes formed so as to make electrical contact with the source / drain regions, a second staggered thin film transistor having the same shape as the gate electrode formed on the amorphous semiconductor film is formed. Source / drain regions containing impurities are formed on the entire surface of the amorphous semiconductor thin film except under the insulating film or on the surface of the amorphous semiconductor of the insulating substrate except under the second insulating film. A thin film transistor, wherein a silicide formed in a self-aligned manner with the second insulating film is provided between the second insulating film and the source / drain metal electrodes on the surface of the drain region.
と、前記ゲート電極を覆うように第１の透明絶縁膜、非
晶質半導体薄膜、第２の透明絶縁膜を形成する工程と、
前記非晶質半導体薄膜を島状にパターニングする工程
と、前記ゲート電極をマスクとして前記絶縁性基板側か
ら露光して前記第２の絶縁膜をパターニングする工程
と、パターニングされた前記第２の絶縁膜またはフォト
レジストをマスクとして前記非晶質半導体薄膜の一部に
不純物を導入する工程と、ソース・ドレイン金属電極を
形成した後、前記ゲート電極上部の第２の透明絶縁膜と
重ならないように離して、且つ、表面に露出したソース
・ドレイン領域表面に形成されたシリサイドを残して前
記ソース・ドレイン金属電極をパターニングし、前記ソ
ース・ドレイン金属電極を形成する工程を含むことを特
徴とする薄膜トランジスタの製造方法。2. A step of forming a gate electrode on an insulating substrate, and a step of forming a first transparent insulating film, an amorphous semiconductor thin film, and a second transparent insulating film so as to cover the gate electrode.
Patterning the amorphous semiconductor thin film into an island shape; exposing the second insulating film by exposing from the insulating substrate side using the gate electrode as a mask; and the patterned second insulating film A step of introducing impurities into a part of the amorphous semiconductor thin film by using a film or a photoresist as a mask, and forming a source / drain metal electrode so as not to overlap the second transparent insulating film on the gate electrode. A thin film transistor comprising a step of forming the source / drain metal electrode by patterning the source / drain metal electrode, leaving the silicide formed on the surface of the source / drain region exposed at the surface. Manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61311828A JPH0680685B2 (en) | 1986-12-29 | 1986-12-29 | Thin film transistor and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61311828A JPH0680685B2 (en) | 1986-12-29 | 1986-12-29 | Thin film transistor and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63168052A JPS63168052A (en) | 1988-07-12 |
| JPH0680685B2 true JPH0680685B2 (en) | 1994-10-12 |
Family
ID=18021888
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61311828A Expired - Lifetime JPH0680685B2 (en) | 1986-12-29 | 1986-12-29 | Thin film transistor and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0680685B2 (en) |
Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2952887B2 (en) * | 1989-05-20 | 1999-09-27 | 富士通株式会社 | Semiconductor device and manufacturing method thereof |
| US5010027A (en) * | 1990-03-21 | 1991-04-23 | General Electric Company | Method for fabricating a self-aligned thin-film transistor utilizing planarization and back-side photoresist exposure |
| EP0459763B1 (en) | 1990-05-29 | 1997-05-02 | Semiconductor Energy Laboratory Co., Ltd. | Thin-film transistors |
| JP2633061B2 (en) * | 1990-06-06 | 1997-07-23 | 松下電器産業株式会社 | Method for manufacturing semiconductor device |
| TW237562B (en) | 1990-11-09 | 1995-01-01 | Semiconductor Energy Res Co Ltd | |
| EP0493113B1 (en) * | 1990-12-28 | 1997-03-19 | Sharp Kabushiki Kaisha | A method for producing a thin film transistor and an active matrix substrate for liquid crystal display devices |
| JP3255942B2 (en) * | 1991-06-19 | 2002-02-12 | 株式会社半導体エネルギー研究所 | Method for manufacturing inverted staggered thin film transistor |
| US6979840B1 (en) | 1991-09-25 | 2005-12-27 | Semiconductor Energy Laboratory Co., Ltd. | Thin film transistors having anodized metal film between the gate wiring and drain wiring |
| JP3173854B2 (en) | 1992-03-25 | 2001-06-04 | 株式会社半導体エネルギー研究所 | Method for manufacturing thin-film insulated gate semiconductor device and semiconductor device manufactured |
| JP3002064B2 (en) * | 1992-11-12 | 2000-01-24 | 松下電器産業株式会社 | Thin film transistor |
| JPH07506703A (en) * | 1993-03-01 | 1995-07-20 | ゼネラル・エレクトリック・カンパニイ | Self-aligned thin film transistor constructed using lifting method |
| US6331717B1 (en) | 1993-08-12 | 2001-12-18 | Semiconductor Energy Laboratory Co. Ltd. | Insulated gate semiconductor device and process for fabricating the same |
| JP3173926B2 (en) | 1993-08-12 | 2001-06-04 | 株式会社半導体エネルギー研究所 | Method of manufacturing thin-film insulated gate semiconductor device and semiconductor device thereof |
| JP3134910B2 (en) * | 1993-09-07 | 2001-02-13 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device and method for manufacturing integrated circuit for liquid crystal display |
| US5796116A (en) | 1994-07-27 | 1998-08-18 | Sharp Kabushiki Kaisha | Thin-film semiconductor device including a semiconductor film with high field-effect mobility |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5799775A (en) * | 1980-12-12 | 1982-06-21 | Toshiba Corp | Manufacture of semiconductor device |
| JPS58115851A (en) * | 1981-12-28 | 1983-07-09 | Seiko Epson Corp | Active matrix substrate |
| JPS58168278A (en) * | 1982-03-30 | 1983-10-04 | Toshiba Corp | Manufacture of thin film transistor |
| JPS5927574A (en) * | 1982-08-04 | 1984-02-14 | Fujitsu Ltd | Manufacture of self-alignment thin film transistor |
| JPS6045066A (en) * | 1983-08-22 | 1985-03-11 | Fujitsu Ltd | Manufacture of thin film transistor |
| JPS6070764A (en) * | 1983-09-26 | 1985-04-22 | Sony Corp | Manufacture of field-effect type transistor |
| JPS60211982A (en) * | 1984-04-06 | 1985-10-24 | Hitachi Ltd | Thin film transistor |
| JPH0612780B2 (en) * | 1985-03-29 | 1994-02-16 | 松下電器産業株式会社 | Method of manufacturing thin film transistor array |
| JPS62205664A (en) * | 1986-03-06 | 1987-09-10 | Matsushita Electric Ind Co Ltd | Manufacture of thin film transistor |
| JPH0622245B2 (en) * | 1986-05-02 | 1994-03-23 | 富士ゼロックス株式会社 | Method of manufacturing thin film transistor |
-
1986
- 1986-12-29 JP JP61311828A patent/JPH0680685B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63168052A (en) | 1988-07-12 |
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