JPH0513365A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To simplifying a semiconductor manufacturing process by applying ohmic metal coating to ohmic regions and an insulating film on a semiconductor substrate, converting the metal coating to an allay, applying low-resistance metal coating, and removing undesired areas of the two metal coatings by a single patterning. CONSTITUTION:An insulating film 2 is applied to cover ohmic regions 1s and 1d and a gate electrode G on a semiconductor substrate 1. With a resist pattern 3 used as a mask, holes are opened in the insulating film 2 to expose part of the ohmic regions. After the resist pattern is removed, the regions 1s and 1d and the insulating film are covered with metal to form an ohmic layer 4. This metal layer 4 is converted to an alloy by heating. A wiring metal layer 5 is applied on the ohmic layer 4. The ohmic layer and the wiring layer are simultaneously processed using a resist pattern as a mask. According to this method, only one patterning operation is required, thereby simplifying the manufacturing process.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device using an insulating film on an ohmic region in which impurities are implanted at a high concentration.

[0002]

2. Description of the Related Art When a semiconductor device is manufactured using an n-type compound semiconductor such as GaAs, A is used as an ohmic metal.
uGe / Ni is commonly used. The AuGe-based ohmic metal can easily form a good ohmic contact with the compound semiconductor, but has a problem that it cannot be used alone as a wiring metal because of its high specific resistance. Therefore, it is necessary to form a metal having a lower resistance than the ohmic metal on the upper surface to reduce the resistance as a whole.

By the way, the ohmic metal is ensured to be ohmic with the semiconductor by alloying. However, if this alloying is carried out after the low resistance metal is attached, the reaction between the low resistance metal and the ohmic metal is caused by the ohmic metal and the semiconductor. A good ohmic contact cannot be obtained before the reaction with.

Therefore, in the conventional manufacturing method, first, an ohmic metal is deposited on a semiconductor, then processed and shaped into an electrode shape by a lift-off method, and this is alloyed alone. Next, a two-step technique of forming a low resistance metal so as to cover the entire processed ohmic metal and processing the low resistance metal separately was adopted.

[0005]

However, the conventional manufacturing method has a drawback that the workability is poor and the process is complicated because the constituent elements forming the same ohmic electrode are manufactured by different processing steps. It was

Therefore, the present invention aims to improve workability and simplify the process.

[0007]

In order to achieve the above object, the present invention provides a step of exposing an ohmic region from an insulating film by forming an opening in the insulating film formed on the ohmic region, and A step of forming a continuous first metal layer on the upper surface of the ohmic region and the insulating film by depositing an ohmic metal material on the opening and the insulating film, and by alloying the first metal layer Forming an ohmic contact between the first metal layer and the semiconductor substrate, and forming a second metal layer on the upper surface of the first metal layer by depositing a low resistance metal material on the first metal layer. And a mask pattern is formed on the second metal layer,
And removing unnecessary portions of the first metal layer and the second metal layer using the mask pattern.

[0008]

In the method of manufacturing a semiconductor device according to the present invention, the first
In the step of forming the second metal layer on the upper surface of the metal layer, the resistance of the ohmic metal is reduced and the metal wiring connected to the ohmic metal is formed. Further, the first metal layer and the second metal layer are processed in the same process using the same mask pattern.

[0009]

An embodiment of the present invention will be described below with reference to the accompanying drawings. In the description, the same elements will be denoted by the same reference symbols, without redundant description. 1A to 1D are process diagrams showing a method for manufacturing a MESFET which is an embodiment of the present invention.

Impurities are implanted at a high concentration in the ohmic region of the semiconductor substrate 1, and the ohmic region 1s,
1d is formed. This ohmic region 1s, 1d
A gate electrode G is formed in advance between the gaps, and the entire gate electrode G is covered with the insulating film 2 (FIG. 7A).

First, a resist material is applied on the upper surface of the insulating film 2 by spin coating, and a resist pattern 3 having openings on the ohmic regions 1s, 1d is formed by using a photolithography technique. This resist pattern 3
With the mask as a mask, an opening is formed in the insulating film 2 to expose a part of the ohmic regions 1s, 1d of the semiconductor substrate 1 from the insulating film 2 (FIG. 2B). In this case, both wet etching using a solution and dry etching using a reactive gas can be used.

Next, the resist pattern 3 is removed, an ohmic metal forming an ohmic electrode is deposited on the ohmic regions 1s, 1d and the insulating film 2, and an ohmic metal layer (first metal layer) 4 continuous on the surface is formed. Form. The ohmic metal layer 4 is formed by evaporating AuGe to a thickness of 1000 Å and Ni to a thickness of 300 Å.
It can have a layered structure. This ohmic metal layer 4 is 450 ° C. as it is without any special processing.
Is heated in the atmosphere for 60 seconds to alloy the ohmic metal layer 4. By this alloying, an ohmic junction is formed between the ohmic metal layer 4 on the ohmic regions 1s and 1d and the semiconductor substrate 1.

Next, a wiring metal layer (second metal layer) 5 is formed on the upper surface of the ohmic metal layer 4. The wiring metal layer 5 may have a three-layer structure in which Ti is 200 angstroms, Pt is 400 angstroms, and Au is 2000 angstroms. Here, Ti has a function of increasing the adhesive force with the ohmic metal layer 4, Au reduces the overall resistance, and Pt has a function of preventing mutual diffusion between AuGe and Au forming the ohmic metal layer 4. Instead of Au of the wiring metal layer 5, a low resistance metal such as Al or W may be used.

Next, the gate electrode G is formed on the upper surface of the wiring metal layer 5.
A resist pattern (mask pattern) 6 having an opening containing is formed (FIG. 3D), and the ohmic metal layer 4 and the wiring metal layer 5 are simultaneously processed using the resist pattern 6 as a mask (FIG. )). In particular,
When an Au-based metal is used as the wiring metal layer 5 and an AuGe / Ni-based metal is used as the ohmic metal 4, the unnecessary portion is removed by the ion milling method. Also, the wiring metal layer 5
As an Al-based metal, and ohmic metal 4 as AuGe /
RI using chlorine-based gas when Ni-based metal is used
The unnecessary portion of the Al-based metal is removed by wet etching using E or phosphoric acid-based solution, and then the unnecessary portion of the AuGe / Ni-based metal is removed by the ion milling method. Further, when a W-based metal is used as the wiring metal layer 5 and an AuGe / Ni-based metal is used as the ohmic metal 4, an unnecessary portion of the W-based metal is removed by RIE using a fluorine-based gas, and then an ion milling method is used. AuGe
/ Remove unnecessary portions of Ni-based metal. Through the above steps, the ohmic electrode including the resistance lowering layer and the wiring layer connected to the ohmic electrode are formed on the ohmic regions 1s and 1d.

As described above, according to this embodiment, since the resistance lowering layer of the ohmic electrode and the wiring layer can be formed in the same step, the patterning process is completed in one time, and the step is simplified. In addition, there is more room for selecting the wiring metal, and the process stability is improved.

The present invention is not limited to the above embodiment. For example, the first metal layer and the second metal layer are not limited to the structure, the material, the shape, and the film thickness described in this embodiment, and those that meet the manufacturing conditions are applied.

[0017]

As described above, according to the present invention, the resistance lowering layer of the ohmic electrode and the wiring metal can be formed by performing the patterning once, so that the workability in manufacturing the semiconductor device is improved. The process can be simplified.

[Brief description of drawings]

FIG. 1 is a process chart showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[Explanation of symbols]

 1 ... Semiconductor substrate 2 ... Insulating film 3 ... Resist pattern 4 ... Ohmic metal layer (first metal layer) 5 ... Wiring metal layer (second metal layer) 6 ... Resist pattern (mask pattern)

Claims (1)

Claim: What is claimed is: 1. A method of manufacturing a semiconductor device using an insulating film on an ohmic region in which impurities are implanted at a high concentration, wherein an opening is formed in the insulating film formed on the ohmic region. A step of exposing the ohmic region from the insulating film, and a first metal continuous to the upper surface of the ohmic region and the insulating film by depositing an ohmic metal material on the opening and the insulating film. Forming a layer, forming an ohmic junction between the first metal layer on the ohmic region and the semiconductor substrate by alloying the first metal layer, and on the first metal layer Forming a second metal layer on the upper surface of the first metal layer by depositing a low resistance metal material on the mask layer, and forming a mask pattern on the second metal layer. And a step of removing unnecessary portions of the first metal layer and the second metal layer by using a turn.