JPS6088444A - Formation of three-dimensional wiring - Google Patents

Abstract

PURPOSE:To greatly simplify the process required to form the titled wiring being air-insulated by a method wherein a photo resist itself which can be easily treated in the process of photolithography is used as a spacer member. CONSTITUTION:A gate electrode 22, source electrodes 23, and a drain electrode 24 are formed on a GaAs substrate 20, a positive resist 27 being provided so as to cover a gate supply wiring 224, and a quality-changing layer 28 containing a large amount of fluorine atoms being then formed by CF4 plasma treatment. A thick film wiring 29 is formed by Au plating, a supply metallic film 30 being formed by evaporation, and a cross-over electrode 32 being then formed by Au plating. The quality-changing layer is removed by O2 plasma treatment, and the photo resist is removed with a resist releaser, resulting in the completion of an air cross-over structure wherein the wiring 224 and the electrode 32 are air-insulated.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for forming a three-dimensional wiring in a semiconductor device, and more particularly to a method for forming an air-insulated three-dimensional wiring.

Semiconductor elements, especially junction gate field effect transistors using GaAs, a compound semiconductor (hereinafter referred to as GaAs transistors)
(referred to as FD'I') has been put into practical use as a microwave transistor that breaks through the characteristic limits of 8i bipolar transistors. GaAsMB8 in microwave like this
The output power of the FET can be increased by increasing the total gate width.

Therefore, normally, a 0aAs 5FET for power use is shown in Figure 1 (
As shown in the plan view of a), a structure is adopted in which comb-shaped drain electrodes 11 and source electrodes 12 are alternately arranged, and a gate electrode 13 is arranged between them.

In order to achieve such a configuration, the wiring 121 to the source electrode 12 and the power supply wiring 131 to the gate electrode 13 must necessarily be three-dimensionally wired (crossover) at a position such as point 14. Normally, these crossovers have a structure in which the sio and p wiring electrodes are insulated by a film 15, as shown in FIG. 1(b), which is a cross section taken along the line AA' in FIG. .

However, at ultra-high frequencies above the X band, the parasitic capacitance generated in these three-dimensional wiring sections cannot be ignored compared to the gate-source depletion layer capacitance Cas of the FET itself, and together with the conductor loss, the gain decreases. is a cause of deterioration of band characteristics. Although the main capacitance can be reduced to some extent by reducing the width of the three-dimensionally intersecting electrodes, an increase in wiring resistance is not preferable because it causes electromigration of the wiring electrodes.

One way to significantly reduce the capacitance without increasing parasitic resistance is to insulate the grade-separated intersection with air without using a power transmission body (
Air crossover structure) is the most effective.

Several devices with air crossover structures have been reported so far, but all of their formation methods mainly utilize etching selectivity. In other words, the metal that becomes the spacer material (steel is commonly used)
In this method, a shear cross-over structure is obtained by forming a spacer material between both wiring electrodes by electrolytic plating or the like, and then selectively removing only the spacer material by etching.

When attempting to create an air crossover of GaAsMH8FET using such a conventional method.

This causes problems as described below. Namely, 1) It is difficult to obtain an etching solution that can selectively remove only the spacer material without at all attacking gate electrodes made of GaAs or A, which are sensitive to acid or alkaline solutions.

2) It is difficult to process spacer material formed to a thickness of several μm with good uniformity within the wafer.

An object of the present invention is to provide a novel method for forming air-insulated three-dimensional wiring.

According to the present invention, a first photoresist layer consisting of a thick film is formed on a band-shaped electrode that becomes a first wiring on a substrate, and a CF
, a step of forming an altered layer containing a large amount of fluorine atoms on the surface by exposing it to dirt, and electrolytic plating using the first photoresist layer as a mask. In the step of forming a thick film wiring, after depositing a metal film for power supply on the entire surface, a second photoresist layer with openings at the intersection with the first wiring is formed, and electrolytic plating is performed again. a step of forming a second wiring that intersects the first wiring three-dimensionally by applying ions; after removing the second photoresist layer, using the second wiring as a mask, the metal film for power supply is ionized; The exposed first photoresist layer is removed by etching or chemical etching, and the exposed first photoresist layer is removed by etching or chemical etching. A method for forming an air-insulated three-dimensional wiring is obtained, which includes the steps of removing the altered layer by plasma treatment and then removing it with an organic solvent.

According to the present invention, since the photoresist itself, which can be easily processed by a normal photolithography process, is used as a spacer material, the steps required for forming three-dimensional wiring are greatly simplified compared to conventional methods.

Hereinafter, GaAsME8FI (T
This will be explained in detail using an example of air crossover.

2 and 3 are diagrams for explaining one embodiment of the present invention, and FIGS. 2(a) to 3(f) are plan views of main parts of the manufacturing process, and FIGS. 3(a) to (f) ) are respectively A-A'B- in Figure 2.
B', C-C', D-D', E-H',
A cross-sectional view of a main part taken along line FF' is shown. First, an active layer 21 is epitaxially grown on a semi-insulating GaAs substrate 20, and an A layer for forming a Schottky barrier is formed on this layer.
A gate electrode 22 made of I, and an ohmic source electrode 23 and a drain electrode 24 made of AuGeNi are formed by a lift-off method using ordinary optical exposure (see FIG. 2(a)).
)). Next, 4Mam and fx Si of KAl gate electrode 22
O,! 25 to about 93,000 yen by CVD method.
- Cover the entire surface, and make windows in the source and drain electrode number protruding parts 231, 241 and the gate electrode area protruding part 221. Next, in order to prevent a reaction between the gate pad portion 222 made of AI and the bonding wire made of Au drawn out from the gate pad portion 222, a reaction prevention electrode 223 made of, for example, Ti/Pt was selectively formed on the gate pad portion 222. After that, 1 is used as a power supply metal film 26 for electrolytic plating.
For example, about 50 OA of each of T i /Au is deposited (FIG. 3(b)). After coating the entire surface with a positive photoresist 27 such as AZ1375 (trade name) to a thickness of 4 to 6 μm, patterning is performed to selectively cover the power supply wiring 224 to the gate electrode 22 (see Fig. 2). (shaded area in (C)). Next, after baking at 120°C for about 60 minutes, the CF4 gas pressure Q, 3 Torr,
CF and plasma treatment under 200W RF power condition.
After about a year, an altered layer 28 containing about 200X of fluorine atoms is formed on the surface. This altered layer 28 is made of an organic solvent such as n-butyl acetate, which is a solvent for AZ resist, or an organic solvent such as AZ resist.
Although it is insoluble in the m<*-based resist solution, it can be easily removed by O, plasma treatment. This CF and plasma treatment has the effect of preventing the resist pattern 27 from being deformed in the subsequent photoprocessing step. Then the second
By applying Au plating to the f+ line portion shown in FIG. 3(d), a thick film wiring 29 having a thickness comparable to that of the photoresist layer 27 is formed. For the purpose of preventing deformation after completion of the cross-over electrode that will be formed later, it is desirable that the thickness of the thick film wiring 29 be equal to or slightly thicker than the photoresist layer 27. Next, a power supply metal film 30 similar to that described above is formed again by vapor deposition over the entire surface, and then a photoresist 31 such as AZ 1350J is applied so that the shaded area in FIG. 2(e) is selectively covered. Perform patterning.

cl on the photoresist 27 of the first loaf! ', This is thought to be due to poor coverage due to the complicated shape of the stepped portion in the conventional method that does not involve plasma treatment. The resist is dissolved and the power supply metal film 30 is deformed or lint-off.

Later formation of the crossover electrode was difficult.

Next, photoresist N31 is applied to the mask and re-plated with Au to form a crossover electrode 32 having a thickness of, for example, 2 to 3 μm (FIG. 3(e)). Next, the photoresist 31 is removed using a solvent such as acetone.

As a crossover tHim32e mask, unnecessary power supply metal film 32 other than the portion of crossover electrode 32 is removed using Ar ion beam etching or I,:KI:H,0-based and H2so-based etching solutions. Next, after removing the altered layer 28 on the exposed side of the photoresist layer 27 by performing O plasma treatment for about 2 minutes under the conditions of KO, lJ gas pressure 0.5 Tor r and RF force 200 W, resist 14I 1 m The photoresist 27 is completely removed using an etching agent (J'-100), and finally, the unnecessary power supply metal film 26 is selectively removed using the same etching solution as described above. If the gate oxygen supply wiring 224 and crossover polarization 32 as shown in FIG.
Since the formation of the spacer material, which requires a miscellaneous process, can be carried out through the photo process, the OT capability has been greatly improved in terms of material size, yield, and hardness.

[Brief explanation of drawings]

Figure 1 (a) and υ) are respectively GaAs for general power use.
-MESFRT’s debt structure? Shown in plane and cross-sectional view of main parts. 11.12.13 is the drain, source, gate electrode, 15t, 1.5i02n moxibustion, 121 is the source d
self line, 131, gate wiring 1411, source wiring 4J12
1 and a three-dimensional wiring section of gate wiring 131. Figures 2 (a) to (f) and 3 (a) to (f) are diagrams for explaining the one-day embodiment of the present invention, and Figure 2 (a)
~Cf) is a plan view of the manufacturing process, Figures 3(a) to (f)
) is a sectional view of the main part of Figure 2. In Figure 17, 20... Semi-insulating (]aAa
Board, 21... Operation 1%, 22, 23, 24...
・・・・・・Gate, source, drain'rJL
Extreme, 25...sho. II<'-! ,, 26, 30...Metal J model for power supply, 27.31...Positive photoresist,
28...Altered layer, 29...Thick film wiring,
32...Crossover'#tI'A, 221
゜231.241...StO, film 25 respectively
Windows for gate, source, and drain electrodes, 2
22...Gate pad, 223...Reaction prevention, use@group; stool, 224...Gate@tube wiring. 7 Figure (θ2 31 tb) Foil Z Figure ζI) te) (C) (f) 3 (a) 1 [I Rino (1) Figure td+ (e) (f)

Claims (2)

[Claims] (1) Forming a first photoresist layer containing a large amount of fluorine atoms on the surface of the first wiring on the substrate, and using the first photoresist layer as a mask to form a second photoresist layer with a similar thickness. a step of forming a second photoresist layer having openings at intersections with the first wiring; and a step of forming a second wiring that three-dimensionally intersects with the first wiring; A method for forming an air-insulated three-dimensional wiring, comprising the step of removing the exposed first photoresist layer after removing the second photoresist layer. (2) The method for forming three-dimensional wiring according to claim (1), wherein the first and second photoresist layers are positive resists.