JPS6088445A - Formation of three-dimensional wiring - Google Patents

Abstract

PURPOSE:To greatly simplify the process required to form the titled wiring being air-insulated by a method wherein a photo resist itself which can be easily treated by the process of photolithography is used as a spacer member. CONSTITUTION:A gate electrode 22, source electrodes 23, and a drain electrode 24 are formed on a GaAs substrate 20, and the negative type photo resist 27 is so provided as to cover a gate supply wiring 224. A thick film wiring 28 is formed by Au plating, a supply metallic film 29 being formed by evaporation, and a cross-over electrodes 31 being then formed by Au plating. The unnecessary part of the metallic film 29 is removed, and the photo resist layer 27 is removed with a release agent. resulting in the completion of an air cross-over structure wherein the wiring 224 and a cross-over electrode 32 are air-insulated.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of forming a three-dimensional wiring in a semiconductor device, and more particularly to a method of forming a three-dimensional wiring that is air-insulated.

Semiconductor elements, especially junction gate field effect transistors (hereinafter referred to as GaAsMF) using GaAs, which is a compound semiconductor
38FFiT) has been put into practical use as a microwave transistor that overcomes the characteristic limits of the 3i bipolar transistor. GaA8M in microwave like this
The output power of the E8FET can be increased by increasing the total gate width.

Therefore, the GaAs 8FET for power use is usually shown in Figure 1 (
As shown in the plan view of a), a structure is adopted in which comb-shaped drain electrodes 11 and source electrodes 12 are alternately arranged, and gate electrodes 1 and 3 are arranged between them.

In order to achieve such a configuration, the wiring 121 to the source electrode 12 and the power supply wiring 131 to the gate electrode 13 must necessarily be three-dimensionally wired (crossover) at a position such as point 14. Usually, these crossovers are arranged at 5.
A structure is adopted in which the io2 film 15 insulates both wiring electrodes.

However, at ultra-high frequencies above the X band, the parasitic capacitance generated in these three-dimensional interconnections cannot be heated and moistened compared to the gate-source depletion layer capacitance CGSK of the ffT itself, and together with the conductor loss, the gain Alternatively, it may be a cause of deterioration of band characteristics.If the width of the intersecting electrodes is made smaller, some parasitic capacitance can be reduced, but if the wiring resistance increases, this will cause electromicration of the wiring electrodes, so it is preferable that tL<
do not have.

The most effective way to significantly reduce the main passenger load by 1 kt without increasing parasitic resistance is to insulate the grade crossing with air without using a conductive material (air crossover structure).

Debye devices with air crossover structures have been reported so far, but all of their formation methods primarily utilize etching selectivity. I wish,
After forming a spacer material (copper is commonly used) between both metal electrodes by electrolytic plating, etc., a shear crossover structure can be obtained by selectively etching away only the spacer wings. It's a method.

If an attempt is made to make a GaAs MESFET into an air crossover using such a conventional method, the following problems arise. Namely, 1) the gate ia made of GaAs or 1, which is sensitive to alkali solutions;
It is difficult to obtain an etching solution that can selectively remove only the spacer material without attacking other materials.

2) It is a national problem to process spacer materials formed to a thickness of several μm with good uniformity within a wafer.

2F, the purpose of the invention is to solve these conventional r#! This invention provides a new method for forming gas-insulated three-dimensional interconnections that eliminates the problem.

According to the present invention, a first metal film for power supply is formed on a strip-shaped first wiring on a substrate, and the first wiring portion is coated with a thick film negative type photoresist layer serving as a spacer. After that, a step of forming a thick film wiring with a thickness of N similar to that of the photoresist layer by applying electrolytic plating, and after depositing a second metal film for power supply on the entire surface, the intersection with the wiring of g1 is formed. forming a positive type photoresist layer with openings, and forming a second wiring that three-dimensionally intersects the first wiring by performing electrolytic plating again, after removing the positive type photoresist layer; , a step of removing the second metal film for power supply except for the second wiring portion by performing ion or chemical etching using the second wiring as a mask; after removing the negative photoresist layer; There is obtained a method for forming an air-insulated three-dimensional wiring, further comprising the step of selectively removing the first metal film for power supply using the thick film wiring as a mask.

According to the present invention, since the photoresist itself, which can be easily processed in a normal photolithography process, is used as a spacer material, the steps required for forming three-dimensional wiring are greatly simplified compared to conventional methods.

Hereinafter, as an embodiment of the present invention, GaAsMESFB'l
This will be explained in detail using the example of air crossover.

2 and 3 are diagrams for explaining one embodiment of the present invention, and FIGS. 2(a) to 3(f) are plan views of main parts of the manufacturing process, and FIGS. 3(a) to (f) ) are respectively A-A'B- in Figure 2.
B', C-C', D-D/, E-Ei, F
- shows a sectional view of the main part of F'. First of all, semi-insulating Qa
Active layer 21 epitaxially grown on As substrate 20
A gate electrode 22 made of AJ for forming a Schottky barrier, and a source electrode 23 and a drain electrode 24 made of AuQeNi are formed on the silicon wafer by a conventional optical exposure method (see FIG. 2). (a)). Next!
The protective film of the gate electrode 22 is SiO, film 25cvI.
) Law 1c Yo,? 3 o Oo
241 and the gate electrode number projection portion 221 are provided with windows. Next, in order to prevent a reaction between the gate pad portion 222 made of A/A and the bonding wire made of Au drawn out from there, a reaction prevention electrode 223 such as T i /P t is selectively attached to the gate pad portion. 222, for example, Ti and Au are deposited in this order at about 500× each as a power supply metal film 26 for electrolytic plating (FIG. 3(b)). Next K Woo r--ha Full surface Negative photoresist 27 such as KOMR83 (product name)
After coating it to a thickness of about 5 μm, patterning is performed to selectively cover the power supply wiring 224 to the gate electrode 22 (shaded area in FIG. 2(C)). Next 130
After baking at ℃ for about 60 minutes, the power supply metal film 2
By using 6 as a conductive path, Au plating is applied to the hatched portion in FIG. Next, a power supply metal film 29 similar to that described above is formed again by vapor deposition on the entire surface, and then
Apply a positive type photoresist 30 such as AZ1350J, and connect the power supply wiring #! Patterning is performed so that the intersection with 224 is opened, that is, the area indicated by diagonal lines in FIG. 2(e) is selectively covered with the photoresist layer 30.

First layer photoresist 27 and second #2 photoresist 30
In the case of positive or negative type photoresist,
Alternatively, if the 11th ## mark is a positive type and the 21st mark is a negative type, as shown in Fig. 3(d), the photoresist layer 2 is
Since the boundary between 7 and the thick film wiring 28 has a complicated shape, the power feeding metal film 28 is likely to break off at this boundary.
In the process of feeding the rice, coating the second photoresist layer 30, and treating the urine, the first photoresist layer 27 is dissolved,
The power feeding metal film 29 is deformed or lifted off, making it difficult to form a crossover electrode later.

Next, by applying Au plating again using the photoresist N30 as a mask, a crossover electrode 31 having a thickness of, for example, 2 to 3 μm is formed (FIG. 3(e)).

Next, after removing the photoresist layer 30 with a virtuous solvent such as acetone, using the crossover electrode 31 as a mask, Ar ion beam etching or Remove unnecessary power supply metal film 29 other than over electrode 31,
Furthermore, the exposed photoresist Jm27 is completely removed using a resist remover (J-100). Finally, by using the thick film wiring M28 as a mask and using the same etching solution as described above to remove the unpleasant power supply metal film 26 other than the thick film wiring 28, the gate power supply as shown in FIG. 3(f) is removed. An air crossover structure in which the wiring 224 and the crossover electrode 32 are air-insulated is completed.

As described above, by using the forming method according to the present invention, it is possible to easily concentrate the spacer material using a normal photo process, which requires a complicated process as in the past, thereby improving productivity, yield, and reliability. It has become possible to significantly improve the degree of

[Brief explanation of the drawing]

Figures 1 (a) and (b) are general Ga for
11, 12, and 13 are a drain and a source, respectively. A gate electrode, 15 an SIO film, and 121 a source wiring. 131 is a gate wiring, and 14 is a three-dimensional wiring section of the source wiring 121 and the gate wiring 131. Figures 2(a) to (f) and Figures 3(a) to (f) are diagrams for explaining non-embodiments of the present invention.
) is a /4 main part plan view of the manufacturing process, and FIGS. 3(a) to <0 are sectional views of the valley part in FIG. 2. In each figure, 2o... semi-insulating GaAs substrate, 21°°... active layer, 22, 23. 24... group...
Gate, source, drain electrodes, 25...
...SiU. Membrane, 26.29... Metal membrane for power supply, 27...
...Negative photoresist, 28...Thick film wiring, 30...Positive photoresist, 31.-
...-Crossover electrode, 221, 231, 241
・・・・・・SiQ respectively. Windows for gate, source and drain electrodes opened in the film 25, 222...Gate pad, 223...
. . . Metal film for reaction prevention, 224 . . . Indicates wiring for gate power supply. Name / 1st Ctl) (b) Atsushi 2 Figure (dn (e) tc) <f)

Claims (1)

[Claims] forming a negative photoresist layer covering at least a portion of the first wiring section on the substrate; forming a thick film wiring having a thickness similar to that of the photoresist layer; forming a positive photoresist layer with an opening at the intersection with the first wiring, and forming a second wiring that three-dimensionally intersects with the first wiring; and after removing the positive photoresist layer, Type photoresist 7? remove t,
A method for forming an air-insulated three-dimensional wiring, comprising the step of selectively removing the metal film of @1 using the thick film wiring as a mask.