JP3409057B2 - Field effect transistor - Google Patents

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a field effect transistor.

[0002]

BACKGROUND OF THE INVENTION The gate of a conventional field effect transistor has a structure elongated in the finger direction. Particularly, in order to reduce the gate resistance, the upper part of the gate is enlarged to form an umbrella shape. The method of doing is adopted. Furthermore, it is known that the insulating film and the like beside the gate must be removed in order to reduce the parasitic capacitance. However,
Since the upper part of the gate is larger than the lower part, when the oxide film and the resist used for forming the gate are removed, stress is exerted also in the direction perpendicular to the gate finger direction, and the gate metal is also peeled off.

<Prior art example> Then, Japanese Patent Laid-Open No. 26344/1990
As shown in FIG. 17 as in Japanese Patent Laid-Open No. 3, an insulating region (region other than 202) is partially provided in the gate finger direction, and the gate length 203 is taken along the line ee in that portion.
In some cases, a structure having a larger gate length than the portion (a) was used. However, in recent years, high-frequency high-performance devices are increasingly aimed at a gate length of 0.1 μm or less, and it is becoming difficult to support the stress applied to the gate by partially increasing the gate length.

[0004]

Therefore, the present invention has been made in view of the drawbacks of the above-described conventional example, and its purpose is to remove an oxide film or to lift off as compared with the prior art. An object of the present invention is to provide a field-effect transistor that is strong against the stress applied to the gate and is unlikely to peel off the gate electrode.

[0005]

According to the present invention, the above object can be achieved by constructing a field effect transistor as follows: 1: At least, a substrate on which an active region and an insulating region are formed, A field effect transistor comprising a source electrode, a drain electrode, and a gate electrode formed on a substrate, wherein the plane pattern of the gate electrode has a grid-like structure in which the gate fingers are connected and the gate electrodes intersect. An insulating region is provided immediately below the connecting gate electrode, and the gate finger extends between the active region and the insulating region. 2: At least, a substrate having an active region and an insulating region formed thereon, and a source electrode, a drain electrode and a gate electrode formed on the substrate, wherein the plane pattern of the gate electrode is connected to the gate finger to form a gate. It has a grid-like structure where the electrodes intersect, and the gate finger
The connecting gate electrode that laterally connects the
In a field effect transistor having a cross-sectional structure thicker than that of Gar , an insulating region is provided immediately below the connecting gate electrode , and the gate finger extends over the active region and the insulating region. 3: The drain electrode has an air bridge structure across the connecting gate electrode. 4: The source electrode has a direct via hole structure from the back surface or an air bridge structure straddling the connecting gate electrode. 5: a substrate in which strip-shaped active regions and strip-shaped insulating regions are alternately formed; A gate electrode composed of a connecting gate electrode having a rectangular cross section that laterally connects the gate fingers formed in each insulating region, a source portion and a drain portion alternately formed on each active region, and each source portion A source electrode that is connected and has a direct via hole structure from the backside, or an air bridge structure that straddles the connecting gate electrode, and a drain that is connected to each drain part and has an air bridge structure that straddles the connecting gate electrode. Electrodes,
Consist of.

[0006]

Example 1 The shape of the gate electrode of a field effect transistor (hereinafter referred to as "FET") formed according to the present invention has a plane structure shown in FIG. The cross-section (finger section cross-section) at a ′ is shown in FIG.
A cross-sectional view (cross-section of the connecting gate electrode portion) taken along line (a) and line bb ′ in FIG. 1 is shown in FIG. 2 (b).

An area surrounded by a dotted line 102 in FIG. 1 is an active area, and other areas are insulating areas.
Indicates a gate electrode. Thus, the planar pattern of the gate electrode 103 is the “gate finger” on the active area.
Part and the "connecting gate electrode part" in the insulating region,
Each has a structure that intersects in a grid pattern. Further, the source electrode 112 and the drain electrode 113 are constituted by an air bridge structure which straddles over the gate connecting electrode as shown in FIG.

The structure of the FET of the first embodiment will be described in more detail according to its manufacturing method. Patterning 106 covering the active layer 102 of FIG. 1 is performed on the epi-substrates (or impurity-implanted substrates) 101 and 102 with a photoresist, and a desired insulating region portion including a connecting gate portion is opened.
The active layer 102 exposed on the surface is removed by etching for insulation (or insulation ion implantation is performed) (FIG. 3: bb ′ cross section).

Thereafter, the patterning resist 106 is formed.
To remove. In this case, in the longitudinal direction of the fine gate, for example, an active region of 20 μm and 2 μ sandwiched between this active region
The structure is such that it is composed of m inactive regions.

Next, as shown in FIG. 4 (cross section aa 'in FIG. 1), a resist pattern 107 for opening desired regions of the source 104 and drain 105 electrodes of the FET is formed,
An ohmic metal is vapor-deposited here and lifted off to form each ohmic electrode.

Next, a low-sensitivity resist 108 is applied on this, exposure 110 and development are performed by combining EB exposure and ultraviolet exposure on the photoresist 108, and the photoresist 10 is then formed.
8 is formed in a pattern in which the gate portion is opened as shown in FIG. 5 (a-a 'cross section in FIG. 1), and a high-sensitivity resist 109 is applied to the upper layer, and this portion is exposed by i-line or the like 111, By developing (FIG. 6: aa ′ cross section of FIG. 1) and depositing a gate metal on this, the shape of FIG. 7 (aa ′ cross section of FIG. 1) is obtained. 1 and FIG. 2 (a), b- as aa 'cross section in FIG.
FIG. 2B is obtained as a b ′ cross section.

After this, the source electrode and the drain electrode are connected and the source 11 of FIG.
2. An air bridge electrode is formed on the drain 113.

As described above, the FET of the first embodiment
Has a structure in which the gate fingers are fixed to each other by a thick connection at several places, so that it is more resistant to the stress applied to the gate when the oxide film is removed or lifted off than in the conventional case, and the gate peeling is less likely to occur.

Further, since the gate fingers are installed on the substrate in a grid pattern with the gate connecting electrodes even in the lateral direction where the strength is weak, the strength of the gate is reinforced and the gate electrode is less likely to peel off.

<Embodiment 2> In the above-mentioned Embodiment 1, the vapor deposition gate has been described. The formation of the gate electrode is as follows.
It can also be applied by using a sputtering method. Specifically, the insulating regions are formed on the epitaxial substrates 101 and 102 (or the impurity-implanted substrate) in the insulating region portion including the portion directly below the connecting gate as in the first embodiment. Thereafter, in the second embodiment, a- in FIG.
The process of Example 2 will be described using the shape of the a ′ cross section.

A gate oxide film 121 and a resist 122 are applied on the substrate (FIG. 9). From above, the photoresist is patterned using EB exposure 123 or the like as shown in FIG. 10 to remove the oxide film in the opening (FIG. 10).
After the entire surface of the gate metal is sputtered (FIG. 11), a pattern having a desired size is formed from a resist as a gate umbrella, and an unnecessary portion of the metal is removed from above to obtain a gate shape (FIG. 12). ).

Next, patterning is performed with a resist at a position where an ohmic electrode is to be formed, and ohmic metal is vapor-deposited and lifted off at that portion to form an ohmic electrode (FIG. 13). After that, the oxide film around the gate is removed to reduce the parasitic capacitance (FIG. 14). After that, the source electrode and the drain electrode and the air bridge electrode are formed as in the first embodiment.

<Embodiment 3> In Embodiments 1 and 2, the source electrode has an air bridge structure.
It is also possible to form via holes . Specifically, similarly to Embodiments 1 and 2, after forming an insulating region, a gate electrode and an ohmic electrode are formed by vapor deposition or sputtering, and then an air bridge of a drain electrode is formed (FIG. 1).
5). After that, a via hole pattern is opened on the back surface of the ohmic portion connecting the source electrode, and the substrate in the opening portion is etched. Thereafter, gold plating 128 is performed on the entire surface to form a via hole electrode from the back surface (FIG. 16 :) .
(Ccc cross section of FIG. 15).

[0019]

As described above, the field-effect transistor according to the present invention has a structure in which the gate fingers are fixed to each other by a thick connection at several places,
Compared to the conventional method, the gate is more resistant to stress applied to the gate when the oxide film is removed or lifted off, and the gate is less likely to peel off. Also,
Since the gate fingers are installed on the substrate in a grid pattern with the gate connecting electrodes even in the lateral direction where the strength is weak, the strength of the gate is reinforced and peeling of the gate electrode does not easily occur.

[Brief description of drawings]

FIG. 1 is a planar structure of a gate electrode of Example 1 according to the present invention.

FIG. 2 is aa ′ (finger portion) and b- in FIG.
Sectional drawing in b '(connecting gate electrode part).

FIG. 3 is a cross-sectional view (connecting gate electrode portion) of the bb ′ section in FIG. 1 during manufacture.

FIG. 4 is a process drawing of the first embodiment according to the present invention.

FIG. 5 is a process drawing of the first embodiment according to the present invention.

FIG. 6 is a process drawing of Example 1 according to the present invention.

FIG. 7 is a process drawing of the first embodiment according to the present invention.

FIG. 8 is a plan structure diagram of a gate electrode of Example 1 according to the present invention.

FIG. 9 is a process drawing of a second embodiment according to the present invention.

FIG. 10 is a process drawing of a second embodiment according to the present invention.

FIG. 11 is a process drawing of a second embodiment according to the present invention.

FIG. 12 is a process drawing of a second embodiment according to the present invention.

FIG. 13 is a process drawing of a second embodiment according to the present invention.

FIG. 14 is a process diagram of a second embodiment according to the present invention.

FIG. 15 is a plan structural view of a gate electrode of Example 3 according to the present invention.

16 is a cross-sectional view taken along line c-c ′ of FIG.

FIG. 17 is a plan view showing the structure of a conventional gate electrode.

FIG. 18 is a cross-sectional view taken along line ee ′ and dd ′ of FIG.

[Explanation of symbols]

101, 201 Substrate 102, 202 Substrate active layer 103, 203 Gate electrode 104, 113, 204 Drain electrode (ohmic electrode) 105, 112, 205 Source electrode (ohmic electrode) 106, 107, 108, 109, 122, 125 Resist 110,111,123 Exposure 121 Oxide film 124 Gate metal 126,127 Ohmic metal 128 Gold plating

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/337-21/338 H01L 27/095 H01L 27/098 H01L 29/775-29/778 H01L 29 / 80-29/812 H01L 21/28-21/288 H01L 21/44-21/445 H01L 29/40-29/43 H01L 29/47 H01L 29/872

Claims (5)

(57) [Claims] 1. A substrate comprising at least an active region and an insulating region, and a source electrode, a drain electrode and a gate electrode formed on the substrate, wherein the plane pattern of the gate electrode is a gate finger. In a field effect transistor having a checkerboard-like structure in which the connecting gate electrode and the connecting gate electrode cross each other, an insulating region is provided directly below the connecting gate electrode, and the gate finger extends across the active region and the insulating region. A field-effect transistor characterized in that 2. A substrate comprising at least an active region and an insulating region, and a source electrode, a drain electrode and a gate electrode formed on the substrate, wherein the plane pattern of the gate electrode is a gate finger. a tie has become in a grid-like structure which intersects the gate electrode, the gate
The connecting gate electrode that horizontally connects the gate fingers is
In a field-effect transistor having a cross-section structure thicker than that of the gate finger, an insulating region is provided directly below the connecting gate electrode , and the gate finger straddles an active region and an insulating region. Effect transistor. 3. The field effect transistor according to claim 1, wherein the drain electrode has an air bridge structure across the connecting gate electrode. 4. The field effect transistor according to claim 1, wherein the source electrode has a direct via hole structure from the back surface or an air bridge structure straddling a connecting gate electrode. 5. A substrate in which strip-shaped active regions and strip-shaped insulating regions are alternately formed, and a gate finger having an umbrella-shaped cross section formed in each of the active regions and straddling the active regions and the insulating regions. And a gate electrode composed of a connecting gate electrode having a rectangular cross section that laterally connects the gate fingers formed in each of the insulating regions, a source portion and a drain portion alternately formed on each of the active regions, and A source electrode is connected and the direct via hole structure from the back side, or a source electrode that has an air bridge structure that straddles the connecting gate electrode, and an air bridge structure that connects each of the drain parts and straddles the connecting gate electrode. And a drain electrode that is formed on the field effect transistor.