JPH07273346A - Manufacture of thin film transistor - Google Patents

Abstract

PURPOSE:To enable formation of a stable silicide electrode in a few processes. CONSTITUTION:A substrate 11, a gate electrode GE, a gate insulation layer 31 and a silicon layer 33 are laminated. A channel blocking layer 35 is formed on a channel formation predetermined region of the silicon layer 33. Then. n-type impurities are implanted to the silicon layer 33 using the channel blocking layer 35 as a mask. After the silicon layer 33 whereto impurities are implanted is subjected to surface treatment, a chromium layer 41 is formed. Thereafter, the silicon layer 33 and the chromium layer 41 are patterned to an element shape. The chromium layer 41 near a channel region is patterned and a source electrode SE and a drain electrode DE are connected to a channel region through a silicide electrode formed on a surface of the semiconductor layer 33. After the chromium layer 41 is patterned, an overcoat layer is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor used as an active element of an active matrix liquid crystal display device.

[0002]

2. Description of the Related Art A schematic structure of a display pixel substrate of an active matrix liquid crystal display device is shown in FIG. As shown,
The display pixel substrate is the gate wiring pad 1 on the transparent substrate 11.
3 and the gate wiring 1 connected to the gate wiring pad 13
5, drain wiring pad 17, drain wiring 19 connected to drain wiring pad 17, and gate wiring 15
And a pixel electrode 23 connected to the source of the corresponding thin film transistor 21.
And are arranged in a matrix.

The display pixel substrate shown in FIG. 6 is conventionally shown in FIG.
It is manufactured by the steps shown in FIGS. First, as shown in FIG. 7A, the gate wiring 15 and the gate electrode GE of the thin film transistor 21 are formed on the transparent substrate 11. Next, the gate insulating layer 3 is formed on the entire surface of the transparent substrate 11.
1, the semiconductor layer (i-Si layer) 33, the channel blocking layer 35, and the photoresist layer 37 are sequentially formed.

The photoresist layer 37 is exposed from the back side of the transparent substrate 11. At this time, the gate wiring 15 and the gate electrode GE serve as a mask. On the other hand, the gate electrode GE portion is masked from the front surface side of the transparent substrate 11 for exposure. By the exposure from the back surface and the front surface, only the portion of the photoresist layer 37 corresponding to the gate electrode GE is in the unexposed state.

After developing the photoresist layer 37,
As shown in (B), a resist pattern formed in self alignment with the gate electrode GE is formed. The channel blocking layer 35 is patterned using this resist pattern as a mask to form the channel blocking layer 35 formed in self-alignment with the gate electrode GE, as shown in FIG. 7B.

As shown in FIG. 7C, impurities are implanted into the semiconductor layer 33 by using the patterned channel blocking layer 35 as a mask, and n-type high concentration (n ⁺ )
Form the layers. Next, as shown in FIG. 8A, the semiconductor layer 33 is patterned to form a device area.
An ITO (indium-tin oxide) film is formed on the entire surface of the substrate by sputtering or the like. This ITO film is patterned to form a pixel electrode 23 connected to the source of the thin film transistor 21, as shown in FIG.

The gate insulating layer 31 at a predetermined position on the gate wiring 15 is etched to form a contact hole 39 for arranging a gate wiring pad as shown in FIG. 8 (C). A chromium (Cr) layer 41 and an aluminum titanium (AlTi) layer 43 for forming source / drain electrodes and lead wirings are sequentially formed on the entire surface of the substrate, and these are formed as shown in FIG.
Patterning is performed as shown in FIG. 3 to form the gate wiring pad 13.

As shown in FIG. 9B, the chromium layer 41 and the aluminum titanium layer 43 in the channel portion of the semiconductor layer 33 and in the vicinity thereof are etched to separate the drain electrode DE and the source electrode SE. Chromium silicide, which is an alloy of chromium and silicon, is formed on the surface of the semiconductor layer 33, and this functions as a chromium silicide electrode that connects the channel region (intrinsic semiconductor region) to the drain electrode DE and the source electrode SE. .

An overcoat layer (passivation film) 45 made of a silicon nitride film or the like is formed on the entire surface of the substrate. The overcoat layer 45 is patterned, and the gate wiring pad 13, the drain wiring pad 17, and the pixel electrode 23 are patterned.
Is exposed, and the manufacturing of the display pixel substrate shown in FIG. 6 is completed.

According to the above manufacturing method, since the source / drain electrodes are not arranged in the vicinity of the channel region, the parasitic capacitance of the thin film transistor (gate-drain capacitance Cgd
And the gate-source capacitance Cgs) becomes small. Also,
Due to the function of the chromium silicide electrode, the source resistance and the drain resistance are maintained at small values.

[0011]

However, according to the above-mentioned manufacturing method, the photolithography process, the ion implantation process, and the ITO process are performed.
During the basic steps such as film formation and patterning, the surface of the semiconductor layer 33 is roughened or oxidized to form a natural oxide film (SiO2). Therefore, there is a problem that the formation of chromium silicide is hindered, and as a result, the source resistance and the drain resistance of the thin film transistor 21 increase.

When the chrome layer 41 is formed after processing the device area, the chrome layer 41 adheres also to the side surface (side wall) of the channel region of the semiconductor layer 33 to form silicide. Therefore, even when the thin film transistor 21 is turned off, a current flows between the source and the drain through the silicide, which causes a problem that the off current of the thin film transistor 21 increases.

Further, if the chromium layer 41 is formed only for forming the silicide electrode, there is a problem that the number of steps is increased accordingly.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a method of manufacturing a thin film transistor capable of forming a stable silicide electrode with a small number of steps. Moreover, this invention aims at providing the manufacturing method of the thin-film transistor which can manufacture the thin-film transistor which has the outstanding characteristic.

[0015]

In order to achieve the above object, a method of manufacturing a thin film transistor according to the present invention comprises:
A step of laminating a substrate, a gate electrode, a gate insulating layer, and a silicon layer, a step of forming a channel blocking layer on a channel formation region of the silicon layer, and an impurity in the silicon layer using the channel blocking layer as a mask. Implanting step, a surface treatment step of applying a surface treatment to the silicon layer, a step of forming a first metal layer on the silicon layer while leaving the channel blocking layer remaining, the silicon layer and the first layer Patterning the metal layer into an element shape, patterning the first metal layer with the metal silicide generated on the surface of the silicon layer remaining, and a source electrode connected to the channel region via the silicide; An electrode forming step of forming a drain electrode, and a step of forming an overcoat layer on the silicon layer Characterized in that it comprises a.

[0016]

In order to reduce the gate-source capacitance / gate-drain capacitance of the thin film transistor, the source electrode and the drain electrode in the vicinity of the channel are removed, and the silicide formed on the surface of the silicon layer is used as a silicide electrode instead. According to the experiments by the inventor of the present application, the factors that inhibit the formation of the silicide and the factors that destroy the formed silicide are classified as shown in FIG. According to the method of manufacturing a thin film transistor, the silicon layer is surface-treated before forming the first metal layer to form the first metal layer, and the overcoat layer is formed immediately after patterning the first metal layer. Therefore, the silicide electrode having sufficiently low resistance can be stably formed.

When the pixel electrode connected to the thin film transistor is formed, it is desirable that the electrode forming step is performed after the pixel electrode is formed.

By arranging the first metal layer as a wiring lead-out layer in the pad portion and stacking this wiring lead-out layer and another metal layer connected to the gate electrode or the drain electrode, a multi-layered lead-out line is formed. As a result, the reliability against oxidation and the like can be improved. In particular, if the positions of the contact hole and the gate pad formed in the gate insulating layer for drawing out the gate wiring are made to differ in plan view, the oxidation of the gate wiring can be effectively prevented. For example, the first metal layer is formed of chromium, the second and third metal layers are formed of aluminum alloy such as aluminum titanium formed in substantially the same process, and the gate electrode and the gate wiring are formed of a single layer. Constructed from structural aluminum alloy.

[0019]

[Examples] Various experiments were conducted to investigate factors that hinder the formation of the chromium silicide electrode or destroy the formed chromium silicide. The results of this investigation are shown in FIG. In FIG. 5, “inhibition factor” means a factor that inhibits the formation of the chromium silicide electrode, and includes an ion doping process, a photolithography process, a photoresist developing solution, and ITO.
The film forming process, the etching solution of ITO, etc. are obstacles. On the other hand, the "destruction factor" means a factor that destroys the formed chromium silicide electrode, and the formation of the ITO film is the destruction factor.

In order to form a good, ie, sufficiently low resistance silicide electrode, a chromium layer for silicide formation is formed on a silicon layer before or after the inhibition factor is removed, and the destruction factor The chrome silicide electrode may be exposed after the above step.

Therefore, the present application proposes a method of manufacturing a thin film transistor, which will be specifically described below as an embodiment. Hereinafter, a method of manufacturing a thin film transistor according to an embodiment of the present invention will be described with reference to FIGS. 1 to 4 by taking a case of manufacturing a display pixel substrate of an active matrix liquid crystal display element shown in FIG. 6 as an example.

First, a conductive layer made of aluminum, an aluminum alloy, chromium or the like is formed on a transparent substrate 11 made of glass, a flexible film or the like by vapor deposition, sputtering or the like, and patterned to form a gate having a single layer structure. The wiring 15 and the gate electrode GE are formed.

Then, the transparent substrate 11 is formed to a thickness of 100-5.
00nm silicon nitride (SiN), silicon oxide (Si
O) or the like, a gate insulating layer 31, a thickness of 30 to 70 nm of amorphous silicon, a semiconductor layer 33 of polysilicon or the like, a thickness of 30 to 100 nm of silicon nitride, a channel blocking layer 35 of silicon oxide or the like, a photoresist layer. 37, plasma CVD method, sputtering,
The layers are sequentially formed using a technique such as coating.

The photoresist layer 37 is exposed from the back surface side of the transparent substrate 11. At this time, the gate wiring 15 and the gate electrode GE serve as a mask. Further, the photoresist layer 37 is exposed from the front surface side of the transparent substrate 11 using an exposure mask (not shown) masking the channel formation region. By exposure from the back surface side and the front surface side, the photoresist layer 37 in the area other than the channel formation area is exposed.

After developing the photoresist layer 37, FIG.
As shown in (B), the photoresist layer 37 is left on the channel formation region. The channel blocking layer 3 is formed by using the remaining photoresist layer 37 as a mask.
5 is wet-etched (or may be dry-etched) using hydrofluoric acid or the like to form a channel blocking layer 35 formed in self-alignment with the gate electrode GE.

As shown in FIG. 1C, an impurity such as phosphorus is ion-doped (ion-implanted) into the semiconductor layer 33 using the channel blocking layer 35 as a mask to form an n-type high concentration (n +) region. After that, in order to remove the rough surface and natural oxide film by ion doping, NH
The surface of the semiconductor layer 33 is treated with 4F or the like (the surface is slightly etched).

Next, as shown in FIG. 2A, a chromium layer 41 for forming a silicide electrode and forming a lead line is formed on the entire surface of the substrate by sputtering.

As shown in FIG. 2B, the chromium layer 41 and the semiconductor layer 33 are patterned by etching to process the device area. At this time, the chromium layer 41 is left in the silicide electrode portion. Further, the chrome layer 41 and the semiconductor layer 33 are left as wiring lead layers also in the gate wiring pad formation region and the drain wiring pad formation region.

IT is formed on the entire surface of the substrate by using sputtering or the like.
A transparent conductive film made of O (indium-tin oxide) or the like is formed and patterned to form a pixel electrode 23 connected to the chromium layer 41 and the source region, as shown in FIG. . As shown in FIG. 3A, a contact hole 39 for connecting the gate wiring 15 and the gate wiring pad 13 is formed in the gate insulating layer 31 by wet etching or dry etching.

Aluminum titanium (AlT
i) is deposited by sputtering or the like to form an aluminum titanium layer 43. At this time, the above-mentioned contact hole 39 is also filled with AlTi. Next, FIG. 3 (B)
As shown in FIG. 3, the aluminum titanium layer 43 is patterned to be connected to the drain electrode DE of the thin film transistor 21, the wiring 19 extending on the drain wiring drawing layer, the source electrode SE, and the gate wiring 15, and the contact hole 3
9 is filled, and a gate wiring lead line 51 extending on the gate electrode lead layer is formed.

Next, as shown in FIG. 3C, the chromium layer 41 near the channel portion is etched to expose the n ⁺ type semiconductor layer 33. On the exposed surface of the semiconductor layer 33,
Chromium silicide, which is an alloy of chromium and silicon, is formed, and this chromium silicide functions as a silicide electrode that connects the channel portion to the source electrode SE and the drain electrode DE.

As shown in FIG. 4, an overcoat layer (passivation film) 45 made of silicon nitride, silicon oxide or the like is formed on the entire surface. Next, overcoat layer 4
5 is etched to expose predetermined positions of the gate wiring lead line 51 and the drain wiring 19 to form the gate wiring pad 13 and the drain wiring pad 17, and the formation of the display pixel substrate shown in FIG. 6 is completed.

According to the above manufacturing method, since the chromium layer 41 is formed immediately after the ion doping step and then the device area is patterned, silicide is formed on the side surface of the channel region of the semiconductor layer 33. Can be prevented. Since the surface treatment of the semiconductor layer 33 is performed before the formation of the chrome layer 41, the rough surface and the natural oxide film which hinder the formation of silicide are removed, and high quality silicide can be reliably formed. Since the etching of the chromium layer 41 in the silicide electrode portion is performed immediately before the formation of the overcoat layer 45, the silicide electrode is formed in the overcoat layer 45.
Protected by the chromium layer 41 from the process before formation, a high quality silicide electrode can be secured.

Since the chromium layer 41 and the semiconductor layer 33 in the pad formation region remain as the wiring lead-out layer during the device area processing, the lead-out lines (pads) for the gate wiring and the drain wiring are n ⁺ and chromium and aluminum titanium (AlTi). 3), the reliability is improved. Further, by displacing the contact hole 39 and the opening for exposing the gate wiring pad 13 in the horizontal direction, it is possible to prevent the influence of the oxidation of the gate wiring pad 13 on the gate wiring 15 having a single-layer structure and susceptible to oxidation. It is desirable to separate the contact hole 39 and the opening for exposing the gate wiring pad 13 as much as possible. Further, since the pad surface has a multi-layer structure of chromium and aluminum, which is difficult to oxidize, it is possible to prevent oxidation around the wiring pad.

Further, by using the chromium layer for forming the multi-layered lead lines and the chromium layer for forming the silicide electrode, it is possible to prevent an increase in the number of manufacturing steps.

The present invention is not limited to the above embodiment. For example, in the above-described embodiment, the chromium layer 41 is formed and chromium silicide is formed as the silicide electrode, but the type of silicide is not limited to chromium silicide. For example, a tungsten (W) layer or the like may be formed instead of the chromium layer 41, and a tungsten silicide electrode or the like may be formed. In addition, various metal silicide electrodes can be used. Similarly, aluminum other than aluminum titanium, aluminum alloys, other metals, etc. can be used for wiring.

In the above embodiments, the present invention has been described by taking the display pixel substrate of the liquid crystal display element as an example, but the present invention can be similarly applied to thin film transistors for other purposes. The pixel electrode 23 and the like may be arranged as necessary. Although a thin film transistor having a self-aligned inverted stagger structure has been exemplified,
It is also applicable to thin film transistors having other configurations.

[0038]

As described above, according to the present invention, a high-quality silicide electrode can be reliably formed. In addition, the reliability of the thin film transistor can be improved.

[Brief description of drawings]

FIG. 1 is a diagram showing a manufacturing process of a thin film transistor according to an embodiment of the present invention.

FIG. 2 is a diagram showing a manufacturing process of a thin film transistor according to an embodiment of the present invention.

FIG. 3 is a diagram showing a manufacturing process of the thin film transistor according to the embodiment of the present invention.

FIG. 4 is a diagram showing a manufacturing process of the thin film transistor according to the embodiment of the present invention.

FIG. 5 is a diagram showing factors that hinder the formation of silicide and factors that destroy the silicide.

FIG. 6 is a plan view showing an example of the configuration of a display pixel substrate.

FIG. 7 is a diagram showing a manufacturing process of a conventional thin film transistor.

FIG. 8 is a diagram showing a manufacturing process of a conventional thin film transistor.

FIG. 9 is a diagram showing a manufacturing process of a conventional thin film transistor.

[Explanation of symbols]

11 ... Transparent substrate, 13 ... Gate wiring pad, 15 ...
Drain wiring pad, 19 ... Drain wiring, 21 ... Thin film transistor, 23 ... Pixel electrode, 31 ... Gate insulating layer (SiN), 33 ... Semiconductor layer (Si) ), 35 ... Channel blocking layer, 37 ... Photoresist layer, 39 ... Contact hole, 41 ... Chrome (Cr) layer, 43 ... Aluminum titanium (AlT
i) layer, 45 ... overcoat layer (passivation film), 51 ... gate wiring lead line

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H01L 21/28 301 S 29/40 A

Claims (8)

[Claims] 1. A laminating step of laminating a substrate, a gate electrode, a gate insulating layer, and a silicon layer; a step of forming a channel blocking layer on a channel formation region of the silicon layer; and a step of using the channel blocking layer as a mask. Implanting impurities into the silicon layer, performing a surface treatment on the silicon layer, forming a first metal layer on the silicon layer while leaving the channel blocking layer remaining, and the silicon layer And a step of patterning the first metal layer into an element shape, and patterning the first metal layer with the metal silicide formed on the surface of the silicon layer remaining, and connecting to the channel region through the silicide. Forming step of forming a formed source electrode and drain electrode, and an overcoat layer on the silicon layer A method of manufacturing a thin film transistor, comprising: 2. The thin film transistor according to claim 1, further comprising a step of forming a pixel electrode connected to the first metal layer, wherein the step of forming the electrode is performed after forming the pixel electrode. Production method. 3. The stacking step includes a step of forming a gate wiring connected to a gate electrode on the substrate, wherein the electrode forming step patterns the silicon layer and the first metal layer to form a gate. The method includes a step of forming a wiring lead layer and a drain wiring lead layer, and a step of forming a contact hole reaching the gate wiring in the gate insulating film, being connected to the first metal layer and extending on the drain wiring lead layer. Forming a second metal layer that is present and a third metal layer that is connected to the gate line through the contact hole and that extends over the gate line lead-out layer; And a third metal layer, and forming an opening in the overcoat layer to expose the second and third metal layers as a pad. The method of manufacturing a thin film transistor according to claim 1 or 2, characterized in that: 4. The method of manufacturing a thin film transistor according to claim 3, wherein the contact hole and the opening exposing the third metal layer are formed at different positions in plan view. 5. A method of manufacturing a thin film transistor, wherein a source electrode and a drain electrode in the vicinity of a channel region are removed to reduce capacitance and a silicide electrode is used, wherein a metal film for forming a silicide electrode is formed by a silicon layer. A method for manufacturing a thin film transistor, comprising: after implanting impurities into the substrate, treating the surface thereof, and then, etching the metal film immediately before forming the overcoat layer. 6. The method of manufacturing a thin film transistor according to claim 5, wherein after forming the metal film, the metal film and the silicon layer are patterned into an element shape. 7. The metal film for forming the silicide electrode is arranged also in a pad portion, and the pad portion has a laminated structure of the metal film and another metal film connected to the silicon layer. The method for manufacturing a thin film transistor according to claim 5 or 6. 8. A position of an opening formed in the overcoat layer for exposing the gate wiring pad by exposing the gate wiring through a contact hole formed in a gate insulating film and connecting to the gate wiring pad. 8. The method of manufacturing a thin film transistor according to claim 7, wherein: