JPS63318145A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63318145A JPS63318145A JP62154109A JP15410987A JPS63318145A JP S63318145 A JPS63318145 A JP S63318145A JP 62154109 A JP62154109 A JP 62154109A JP 15410987 A JP15410987 A JP 15410987A JP S63318145 A JPS63318145 A JP S63318145A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- metal layer
- thick
- conductive metal
- resist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 238000000034 method Methods 0.000 claims abstract description 19
- 238000009713 electroplating Methods 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 239000002184 metal Substances 0.000 claims description 57
- 229910052751 metal Inorganic materials 0.000 claims description 57
- 238000007747 plating Methods 0.000 claims description 38
- 239000010410 layer Substances 0.000 claims 16
- 239000011247 coating layer Substances 0.000 claims 4
- 239000003795 chemical substances by application Substances 0.000 abstract description 2
- 239000000463 material Substances 0.000 abstract description 2
- 230000008020 evaporation Effects 0.000 abstract 3
- 238000001704 evaporation Methods 0.000 abstract 3
- 238000007740 vapor deposition Methods 0.000 description 7
- 238000005530 etching Methods 0.000 description 6
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体装置の製造方法に係り、特に厚メッ
キ電極の形成方法の改良に関するものである。以下、半
導体基板として砒化ガリウム（ＧａＡｓ）を用いたンヨ
ットキ障壁ゲー１−構造Ｇ ａＡ ｓＮ界効果トランノ
スタ（以下ＧａＡｓＭＥ Ｓ Ｆ Ｅ Ｔ’という）を
例にとって説明を行う、。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to an improvement in a method for forming thickly plated electrodes. Hereinafter, explanation will be given by taking as an example a Nyotoki barrier Ga1-structure GaA sN field effect transistor (hereinafter referred to as GaAsMESFET') using gallium arsenide (GaAs) as a semiconductor substrate.
７リツプチツプ構造のＧ ａＡｓＭ Ｅ Ｓ Ｆ’ Ｅ
Ｔは、Ｘ？１）以上の高周波領域においても高利得を
保持するのに有効であることは周知である。これはボン
ディングワイヤを介さず、Ｆ“ＥＴチップがパッケージ
に倒置形で直接熱圧着されることにより寄生インダクタ
ンス（Ｌ８）および熱抵抗（ｒｔｔＪの低減効果による
ところが大である。7-lip chip structure GaAsM E S F' E
T is for X? 1) It is well known that it is effective in maintaining high gain even in the above high frequency range. This is largely due to the effect of reducing parasitic inductance (L8) and thermal resistance (rttJ) by directly thermocompressing the FET chip upside down onto the package without using bonding wires.
ところで、この種のＦ Ｅ ’Ｉ’構造では、ＦＥ’ｒ
チップ上のソース、ゲートおよびドレインの各電極の所
望の部分に、Ｆ Ｅ Ｔパッケージとの熱圧着のための
中間接着導体として厚メッキ電極層を選択的に形成する
ことが不可欠となる。By the way, in this kind of FE 'I' structure, FE'r
It is essential to selectively form thick plated electrode layers on desired portions of the source, gate and drain electrodes on the chip as intermediate adhesive conductors for thermocompression bonding with the FET package.
この種の厚メッキ電極層の形成方法の一例として第２図
（ａ）〜（ｆ）の主要工程における断面図に示すような
方法がある。An example of a method for forming this type of thick plated electrode layer is the method shown in cross-sectional views of main steps in FIGS. 2(a) to 2(f).
ナオ、以下に述へる方法は、ソース電極上のみに着目し
た場合であるが、ゲ−１・電極およびドレイン電極上に
ついても同様であるため省略しである。Nao, the method described below focuses only on the source electrode, but the same applies to the gate electrode and the drain electrode, so the explanation is omitted.
すなわち、この方法では、まず第２図（ａ）に示すよう
に、半絶縁性ＧａＡｓ基板２１上に生成されたｎ型Ｇａ
Ａｓ半導体層２２の表面にソース電極２３、ゲート電極
２４およびドレイン電極２５が所定の間隔で設けられた
試料ウェハを用意する。That is, in this method, first, as shown in FIG. 2(a), n-type Ga
A sample wafer is prepared in which a source electrode 23, a gate electrode 24, and a drain electrode 25 are provided at predetermined intervals on the surface of an As semiconductor layer 22.
続いて第２図（ｂ）に示すように、ソース電極２３上の
一部を露出させ、他を被覆する第１のレジスト層２６を
形成する。その後、第２図（Ｃ）に示すように、第１の
レジスト層２６およびソース電極２３上の開孔部にわた
り、Ｔ ｉ −Ａ ｕの２層構造からなる電解メッキ用
の第１の導通金属層２７を周知の蒸着法により形成する
。Subsequently, as shown in FIG. 2(b), a first resist layer 26 is formed to expose a part of the source electrode 23 and cover the rest. Thereafter, as shown in FIG. 2(C), a first conductive metal for electrolytic plating consisting of a two-layer structure of Ti-Au is applied over the first resist layer 26 and the opening on the source electrode 23. Layer 27 is formed by a well-known vapor deposition method.
その後、第２図（ｄ）に示すように、ソース電極２３上
の開孔部に相当する位置に一部の開孔部を残し、他を第
２のレジスト層２８で被覆する。しかる後、第２図（ｅ
）に示すように、第２のレレスｌ一層２８をマスクとし
て第１の導通金属層２７により電解メッキを行い、選択
的に金の厚メッキ層２９を形成する。Thereafter, as shown in FIG. 2(d), some openings are left at positions corresponding to the openings on the source electrode 23, and the rest are covered with a second resist layer 28. After that, Figure 2 (e
), electrolytic plating is performed using the first conductive metal layer 27 using the second layer 28 as a mask to selectively form a thick gold plating layer 29.
その後、第２のレジス）・層２８．第１の導通金属層２
７．および第１のレジスト層２６を順次除去し、第２図
（ｆ）に示すような構造を得ろ。Thereafter, a second resist) layer 28. First conductive metal layer 2
7. Then, remove the first resist layer 26 in order to obtain a structure as shown in FIG. 2(f).
しかしながら、この方法においては、’Ｌ’ ｉ −Ａ
ｕの２層構造を有する第１の導通金属層２７をつＬッ
）・エツチングにより除去する場合、厚メッキ層２９も
同時に蝕刻され、厚メッキ層２９の表面に凹凸が生じる
ことによりボンディング強度の低下、ひいては素子の信
頼性を低下させる大きな要因となっていた。However, in this method, 'L' i −A
When the first conductive metal layer 27 having a two-layer structure is removed by etching, the thick plating layer 29 is also etched at the same time, and the surface of the thick plating layer 29 becomes uneven, which reduces the bonding strength. This has been a major factor in reducing the reliability of the device.
この発明は、このような従来の決定を除去するためにな
さ噴またもので、ソース、ゲートおよびドレインの各電
極上の一部に電解メッキ法により厚メッキ層を形成する
方法において、メッキ形成後の処理法に工夫を加える乙
とによって、メッキ用導通金属層の除去時に厚メッキ層
表面が損傷を受けるのを防止することができる半導体装
置の製造方法を提供することを目的とする。The present invention was made in order to eliminate such conventional decisions, and in a method for forming a thick plating layer on a portion of each source, gate, and drain electrode by electrolytic plating, It is an object of the present invention to provide a method for manufacturing a semiconductor device that can prevent the surface of a thick plating layer from being damaged during the removal of a conductive metal layer for plating by adding a device to the processing method.
この発明に係る半導体装置の製造方法は、電解メッキ法
により厚メッキ層を形成し、その後、電解メッキ用の一
層以上からなる導通金属層の最下層の金属層と同種の金
属層を蒸着法により厚メッキ層表面ならびに非メッキ領
域全体に形成した後、不要部分を除去するようにしたも
のである。A method for manufacturing a semiconductor device according to the present invention includes forming a thick plating layer by electrolytic plating, and then applying a metal layer of the same type as the lowest metal layer of a conductive metal layer consisting of one or more layers for electrolytic plating by vapor deposition. After forming the thick plating layer on the surface and the entire non-plated area, unnecessary portions are removed.
この発明においては、厚メッキ層形成直後にメッキ導通
金属層と同種の金属層（多層の場合、最・ Ｆ層の金属
層）を蒸着法により被着させることにより、メッキ時の
導通金属層をウェットエツチングにより除去する場合に
厚メッキ層表面の損傷を防止でき、メッキ表面の凹凸の
発生を低減できろ。In this invention, immediately after forming a thick plating layer, a metal layer of the same type as the plated conductive metal layer (in the case of multilayer, the first F layer metal layer) is deposited by vapor deposition, thereby making the conductive metal layer during plating. When removing by wet etching, damage to the surface of the thick plating layer can be prevented and the occurrence of unevenness on the plating surface can be reduced.
第１図（ａ）〜（ｊ）はこの発明の一実施例の電界効果
トランジスタの製造方法の概略構成を示す断面図である
。FIGS. 1(a) to 1(j) are cross-sectional views showing a schematic structure of a method for manufacturing a field effect transistor according to an embodiment of the present invention.
この方法では、まず第１図（ａ）に示すように、半絶縁
性ＧａＡｓ基板１上に生成されたｎ型ＧａＡｓ半導体層
２の表面に、ソース電極３．ゲ−１・電極４およびドレ
イン電極５が所定の間隔で設けられた試料ウェハを用意
する。続いて第１図（ｂ）に示すように、ソース電極３
上の一部を露出させ、他を被覆する第１のレジス）・層
６を形成する３、その後、第１図（ｃ）に示すように、
第１のレジスト層６およびソース電極３上の開孔部に対
し、電解メッキ用の導通金属層７を所定の厚さに周知の
蒸着法により形成する。上記の導通金属層７は多層構造
、例えば下層をＴｉｆｆＪ、上層をＡｕＪｉ！とした２
層構造の金属層である。その後、第１図（ｄ）に示すよ
うに、ソース電極３上の開孔部に相当する位置に一部の
開孔部を残し、他を第２のレレスト層８で被覆する。し
かる後、第１図（ｅ）に示すように、第２のレジスト層
８をマスクとして導通金属層７により電解メッキを行い
選択的に厚メッキ層９を形成する。その後、第１図（ｆ
）に示すように、この発明の意図する金属層１０を蒸着
法により厚メッキ層９表曲から第２のレジ・スト層８上
にわたり被着する。この場合、金属層１ｏは、導通金属
層７の最下層金属層、ここではＴｉ層と同種の金属層、
っま１）Ｔｉの金属層か、または導通金属層７と同じ蝕
刻液で除去できる金属層、または厚メッキ層９表面を蝕
刻しないエツチング液で容易に除去可能な金属層とし、
最下層のＴｉ層と同じ厚さの数百入の厚さとする。続い
て、第２のレジスト層８の剥＃液中に浸すことにより、
金属層１０の不連続箇所から浸入した剥離液により第２
のレジスト層８が除去され、第２の°レジスト層８上の
金属層１０も同時に除去され、第１図（ｇ）に示すよう
な構造が得られる。この場合、第２のレジスト層８上の
金属層１０の除去には水スプレー等を併用するとより効
果的である。この後、第１図（ｈ）に示すように、導通
金属層７の上層金属（Ａ ｕ層）を所定のエツチング液
で除去する。この場合、厚メッキ層９表面は金属層（Ｔ
ｉ層）１０で覆われているためエツチングされない１．
従来法では、この工程で厚メッキｌ１９ｆ ９表面が損
傷を受けてい１．＝（、シかる後、この実施例でば導通
金属層７の下層金属層であるｌ′１層を所定のエツチン
グ液で除去ずろと同時に、厚メッキ層９上の金属Ｊ！
１０も除去し、第１図（ｉ）に示すような構造を得ろ。In this method, first, as shown in FIG. 1(a), a source electrode 3. A sample wafer in which a gate electrode 4 and a drain electrode 5 are provided at a predetermined interval is prepared. Next, as shown in FIG. 1(b), the source electrode 3
Form a layer 6 (first resist layer 6 exposing the top part and covering the other part), then as shown in FIG. 1(c),
A conductive metal layer 7 for electrolytic plating is formed to a predetermined thickness in the opening on the first resist layer 6 and the source electrode 3 by a well-known vapor deposition method. The conductive metal layer 7 has a multilayer structure, for example, the lower layer is TiffJ and the upper layer is AuJ! 2
It is a metal layer with a layered structure. Thereafter, as shown in FIG. 1(d), some openings are left at positions corresponding to the openings on the source electrode 3, and the rest are covered with the second resist layer 8. Thereafter, as shown in FIG. 1(e), electrolytic plating is performed using the conductive metal layer 7 using the second resist layer 8 as a mask to selectively form a thick plating layer 9. After that, Fig. 1 (f
), the metal layer 10 contemplated by the present invention is deposited from the thick plating layer 9 to the second resist layer 8 by vapor deposition. In this case, the metal layer 1o is the lowest metal layer of the conductive metal layer 7, here a metal layer of the same type as the Ti layer,
1) A metal layer of Ti, a metal layer that can be removed with the same etching solution as the conductive metal layer 7, or a metal layer that can be easily removed with an etching solution that does not etch the surface of the thick plating layer 9;
The thickness is several hundred, which is the same thickness as the bottom Ti layer. Subsequently, by immersing the second resist layer 8 in a stripping solution,
The stripping liquid that entered from the discontinuous parts of the metal layer 10 caused the second
The second resist layer 8 is removed, and the metal layer 10 on the second resist layer 8 is also removed at the same time, resulting in a structure as shown in FIG. 1(g). In this case, it is more effective to remove the metal layer 10 on the second resist layer 8 by using a water spray or the like in combination. Thereafter, as shown in FIG. 1(h), the upper metal layer (Au layer) of the conductive metal layer 7 is removed using a predetermined etching solution. In this case, the surface of the thick plating layer 9 is a metal layer (T
i layer) 1. which is not etched because it is covered with 10.
In the conventional method, the thick plating l19f9 surface was damaged in this process.1. =(, in this embodiment, the l'1 layer, which is the lower metal layer of the conductive metal layer 7, is removed using a predetermined etching solution, and at the same time, the metal J! on the thick plating layer 9 is removed).
10 is also removed to obtain a structure as shown in FIG. 1(i).
最後に、第１のレジスト層６を除去することにより、ソ
ー゛ス電極３上に選択的に厚メッキ＋ｉ ９が形成され
ｌコ第１図（ｊ）に示すような構造を得る。Finally, by removing the first resist layer 6, a thick plating layer 9 is selectively formed on the source electrode 3, resulting in a structure as shown in FIG. 1(j).
このように、上記実施例ではメッキ形成直後に厚メッキ
層９上に電解メッキ用の導通金属層７の最下層の金属層
と同種の金属層または厚メッキ層９を蝕刻しないエツチ
ング液で容易に除去可能な金属からなる金属層１０を蒸
着法により被着するようにしたことから、導通金属層７
の除去時に厚メッキ層９表面が損傷することを防止でき
、厚メッキ層９表面の凹凸が緩和できることから、組立
時のボンディング強度の向上が計られ、歩留りの向上や
高信頼度化に有効となる。In the above embodiment, immediately after plating is formed, a metal layer of the same type as the lowest metal layer of the conductive metal layer 7 for electrolytic plating or an etching solution that does not etch the thick plating layer 9 can be easily etched onto the thick plating layer 9. Since the metal layer 10 made of a removable metal is deposited by vapor deposition, the conductive metal layer 7
Since it is possible to prevent the surface of the thick plating layer 9 from being damaged during the removal of the thick plating layer 9, and the unevenness on the surface of the thick plating layer 9 can be alleviated, the bonding strength during assembly can be improved, which is effective in improving yield and increasing reliability. Become.
なお、上記実施例ではＧ ａ Ａ ｓ Ｍ ’Ｅ Ｓ
ｆ・′Ｉε°１′のソース電極３に厚メッキ層９を形成
する場合について述べたが、この発明はこれに限らず、
ゲート電極４およびドレイン電極５に対しても適用でき
るものである。また、フリップ方式のＦ Ｅ ’Ｉ’に
限らず、他の方式のＦＥＴにも適用できる。さらに、Ｇ
＾ＡｓＦＥ’ｒに限らず、半導体材料からなる半導体装
置に対してもこの発明は広く適用できる。In addition, in the above example, G a A s M 'E S
Although the case where the thick plating layer 9 is formed on the source electrode 3 of f·'Iε°1' has been described, the present invention is not limited to this.
It can also be applied to the gate electrode 4 and the drain electrode 5. Further, the present invention is not limited to the flip type FET, but can also be applied to other types of FETs. Furthermore, G
This invention is widely applicable not only to AsFE'r but also to semiconductor devices made of semiconductor materials.
し発明の効果〕
この発明は以上説明したとおり、厚メッキ層を有する半
導体装置の製造方法において、メッキ形成直後に厚メッ
キ層上に電解メッキ用の一層以上からなる導通金属層の
最下層の金属層と同種の金属層を蒸着により被着した後
、導通金属１５の除去と同時に厚メッキ層上の金属層を
除去するようにし１．＝ので、導通金属層の除去時に厚
、メッキ層の表１１１が損傷することを防止でき、厚メ
ッキ層表向の凹凸が緩和できることから、組立時のボン
ディング強度の向上が計られ、歩留り向上や高信頼度化
にイア効となる。[Effects of the Invention] As explained above, the present invention provides a method for manufacturing a semiconductor device having a thick plating layer, in which the metal of the lowest layer of a conductive metal layer consisting of one or more layers for electrolytic plating is placed on the thick plating layer immediately after plating is formed. After a metal layer of the same type as the layer is deposited by vapor deposition, the metal layer on the thick plating layer is removed at the same time as the conductive metal 15 is removed.1. =, it is possible to prevent damage to the thick plated layer surface 111 when the conductive metal layer is removed, and the unevenness on the surface of the thick plated layer can be alleviated, which improves the bonding strength during assembly and improves yield. This is effective in increasing reliability.
第１図（ａ）〜（ｊ）はこの発明による厚メッキ層を有
するＧａＡｓＭＥＳＦＥ’ｌ’の主要工程における状態
を示す断面図、第２図（ａ）〜（ｆ）は従来法の主要工
程における状態を示す断面図である。
図において、１は半絶縁性ＧａＡｓ基板、２はｎ型Ｇａ
Ａｓ半導体層、３は・ノース電極、４はゲート電極、５
はドレイン電極、６ば第１のレジスト層、７は゛導通金
属層、８は第２のレジスト層、９；よ厚メッキＩＮ、１
０は金属層である。
なお、各図中の同一符号は同一または相当部分を示す。
代理人 大 岩 増 雄 （外２名）第１図
／導迷金、極層
矛 １ 凹
９厚メッキ眉
］０金ＭＯＷ
第２図
第２図
手続補正書（自発）FIGS. 1(a) to (j) are cross-sectional views showing the main steps of GaAsMESFE'l' having a thick plating layer according to the present invention, and FIGS. 2(a) to (f) are sectional views showing the main steps of the conventional method. It is a sectional view showing a state. In the figure, 1 is a semi-insulating GaAs substrate, 2 is an n-type GaAs substrate, and 2 is an n-type GaAs substrate.
As semiconductor layer, 3 is a north electrode, 4 is a gate electrode, 5
1 is a drain electrode, 6 is a first resist layer, 7 is a conductive metal layer, 8 is a second resist layer, 9 is a thick plating IN, 1
0 is a metal layer. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent: Masuo Oiwa (2 others) Figure 1/Doumagin, Gokuseiho 1 Concave 9 thick plated eyebrows] 0 gold MOW Figure 2 Figure 2 Procedural amendment (self-motivated)
Claims (1)
属層からなる導通金属層、この導通金属層上に所望の開
孔部を有する第１の被覆層を形成し、前記導通金属層に
通電することにより、前記第１の被覆層の開孔部に厚メ
ッキ層を施し、その後、不要な前記第１の被覆層、およ
び導通金属層を順次除去し、前記半導体基板上に選択的
に厚メッキ層を形成する半導体装置の製造方法において
、前記厚メッキ層形成後、この厚メッキ層表面から前記
第１の被覆層表面にわたり、前記導通金属層の最下層と
同種の金属層を被着し、前記導通金属層を除去すると同
時に前記厚メッキ層上の金属層を除去する工程を含むこ
とを特徴とする半導体装置の製造方法。A conductive metal layer consisting of one or more metal layers for electrolytic plating formed on a semiconductor substrate, a first coating layer having a desired opening portion formed on the conductive metal layer, and energizing the conductive metal layer. By applying a thick plating layer to the opening of the first coating layer, the unnecessary first coating layer and the conductive metal layer are sequentially removed, and a thick plating layer is selectively formed on the semiconductor substrate. In the method for manufacturing a semiconductor device in which a plating layer is formed, after the thick plating layer is formed, a metal layer of the same type as the bottom layer of the conductive metal layer is deposited from the surface of the thick plating layer to the surface of the first coating layer. . A method of manufacturing a semiconductor device, comprising the steps of removing a metal layer on the thick plating layer at the same time as removing the conductive metal layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62154109A JPS63318145A (en) | 1987-06-19 | 1987-06-19 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62154109A JPS63318145A (en) | 1987-06-19 | 1987-06-19 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63318145A true JPS63318145A (en) | 1988-12-27 |
Family
ID=15577122
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62154109A Pending JPS63318145A (en) | 1987-06-19 | 1987-06-19 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63318145A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0480313A2 (en) * | 1990-10-12 | 1992-04-15 | Daimler-Benz Aktiengesellschaft | Method of fabrication a T-gate-electrode |
| US5272111A (en) * | 1991-02-05 | 1993-12-21 | Mitsubishi Denki Kabushiki Kaisha | Method for manufacturing semiconductor device contact |
| US6649507B1 (en) * | 2001-06-18 | 2003-11-18 | Taiwan Semiconductor Manufacturing Company | Dual layer photoresist method for fabricating a mushroom bumping plating structure |
-
1987
- 1987-06-19 JP JP62154109A patent/JPS63318145A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0480313A2 (en) * | 1990-10-12 | 1992-04-15 | Daimler-Benz Aktiengesellschaft | Method of fabrication a T-gate-electrode |
| EP0480313A3 (en) * | 1990-10-12 | 1993-11-18 | Daimler Benz Ag | Method of fabrication a t-gate-electrode |
| US5272111A (en) * | 1991-02-05 | 1993-12-21 | Mitsubishi Denki Kabushiki Kaisha | Method for manufacturing semiconductor device contact |
| US6649507B1 (en) * | 2001-06-18 | 2003-11-18 | Taiwan Semiconductor Manufacturing Company | Dual layer photoresist method for fabricating a mushroom bumping plating structure |
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