JPS54115065A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS54115065A
JPS54115065A JP2324178A JP2324178A JPS54115065A JP S54115065 A JPS54115065 A JP S54115065A JP 2324178 A JP2324178 A JP 2324178A JP 2324178 A JP2324178 A JP 2324178A JP S54115065 A JPS54115065 A JP S54115065A
Authority
JP
Japan
Prior art keywords
film
electrodes
metal
plating
increase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2324178A
Other languages
Japanese (ja)
Inventor
Yasuro Mitsui
Masaaki Nakatani
Saburo Takamiya
Shigeru Mitsui
Manabu Watase
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2324178A priority Critical patent/JPS54115065A/en
Publication of JPS54115065A publication Critical patent/JPS54115065A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/4813—Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE: To increase the workability and relizbility and also to improve the increase in the degree of integration and high frequency gain, by connecting a plurality of electrodes formed with space in parallel with each other by means of evaporated matallic film.
CONSTITUTION: The plating metal pole 13 is formed on the source electrode 2 with plating which takes the first photo resist film 12 as a mask. Further, the metallic film 15 is formed on the entire surface on the second photo resist film 14. Then, the film 14 together with the metal film 15 on it are removed and the connection metal film 16 is left, connecting the metal poles 13. Finally, when the film 12 is removed, the FET in electrical contact between the source electrodes 2 is formed with the metallic film 16 formed in bridge-led shape taking the metal pole 13 on the source electrodes 12 as legs. Thus, no wire connection between the electrodes is required and no contact between the wire and electrodes is made.
COPYRIGHT: (C)1979,JPO&Japio
JP2324178A 1978-02-28 1978-02-28 Semiconductor device Pending JPS54115065A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2324178A JPS54115065A (en) 1978-02-28 1978-02-28 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2324178A JPS54115065A (en) 1978-02-28 1978-02-28 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS54115065A true JPS54115065A (en) 1979-09-07

Family

ID=12105099

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2324178A Pending JPS54115065A (en) 1978-02-28 1978-02-28 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS54115065A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57160169A (en) * 1981-03-27 1982-10-02 Fujitsu Ltd Semiconductor device
JPS6088444A (en) * 1983-10-21 1985-05-18 Nec Corp Formation of three-dimensional wiring
JPS6089944A (en) * 1983-10-24 1985-05-20 Nec Corp Method of forming three-dimensional wirings
JP2006210499A (en) * 2005-01-26 2006-08-10 Mitsubishi Electric Corp Semiconductor device and its manufacturing method

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57160169A (en) * 1981-03-27 1982-10-02 Fujitsu Ltd Semiconductor device
JPS6332275B2 (en) * 1981-03-27 1988-06-29 Fujitsu Ltd
JPS6088444A (en) * 1983-10-21 1985-05-18 Nec Corp Formation of three-dimensional wiring
JPH0226385B2 (en) * 1983-10-21 1990-06-08 Nippon Electric Co
JPS6089944A (en) * 1983-10-24 1985-05-20 Nec Corp Method of forming three-dimensional wirings
JPH0226386B2 (en) * 1983-10-24 1990-06-08 Nippon Electric Co
JP2006210499A (en) * 2005-01-26 2006-08-10 Mitsubishi Electric Corp Semiconductor device and its manufacturing method

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