JP2006210499A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which the problem of filler attack is solved and which has superior high-frequency characteristics, and to provide a manufacturing method of the device. <P>SOLUTION: A plurality of gate electrodes 4, a drain electrode 3, and a first source electrode 2 and a second source electrode 2' arranged on both sides of the drain electrode 3 across the gate electrodes 4, are formed on a GaAs substrate 1. An air bridge 5 is disposed between the first source electrode 2 and the second source electrode 2', and a part between the gate electrode 4 and the air bridge 5 is made hollow. A first opening part 14 is formed, in a region which does not overlap with the gate electrode 4 in the air bridge 5, as viewed in a plane. The first opening part 14 is plugged with a metal 9. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a hollow structure and a manufacturing method thereof.

  Since the performance of a high-frequency element is reduced due to an increase in parasitic capacitance, it is particularly necessary to reduce the capacitance between the input and output of a high-frequency signal. For this reason, conventionally, a method of reducing parasitic capacitance and reducing high-frequency characteristics by forming a hollow structure around the gate electrode using an air bridge has been adopted (see, for example, Non-Patent Document 1). ).

Gozo Makiyama, 6 others, “Improvement of HEMTIC operation speed by reducing parasitic capacitance”, IEICE Technical Report, IEICE, TECHNICAL REPORT OF IEICE ED2003-214, MW2003-242 (2004-1), p. 49-53

  However, when a high-frequency element is mounted on a plastic package or the like, there is a problem in that a high dielectric constant plastic enters the hollow structure portion, thereby increasing parasitic capacitance and reducing performance. In addition, when the plastic contacts the surface of the semiconductor through the hollow structure, there is a problem that internal stress is generated in the high-frequency element or the high-frequency element is mechanically damaged.

  A method of applying polyimide or the like to the surface of a semiconductor is known for the problem due to filler attack when mounting such a high-frequency element on a plastic package. However, this method has a problem that high-frequency characteristics are degraded due to the parasitic capacitance of polyimide. Also, the method of applying a low dielectric constant material to the semiconductor surface has been difficult to put into practical use from the viewpoint of heat resistance and process controllability.

  The present invention has been made in view of such problems. That is, an object of the present invention is to provide a semiconductor device having excellent high-frequency characteristics and a method for manufacturing the same by solving the problem of filler attack.

  Other objects and advantages of the present invention will become apparent from the following description.

  A first invention of the present application is a semiconductor device having a plurality of gate electrodes formed on a semiconductor substrate, the drain electrode formed on the semiconductor substrate, and the gate electrode sandwiched between both sides of the drain electrode. A first source electrode and a second source electrode, and an air bridge that electrically connects the first source electrode and the second source electrode, and a gap between the gate electrode and the air bridge. The air bridge is provided with an opening in a region where the air bridge does not overlap with a gate electrode when seen in a plan view, and the opening is closed with a metal.

  Further, the second invention of the present application is provided at a position facing the drain electrode across the gate electrode, the gate electrode formed on the semiconductor substrate, the drain electrode formed on the semiconductor substrate, and the gate electrode. A source electrode; a first extension extending from the drain electrode toward the source electrode; and a second extension extending from the source electrode toward the drain electrode and facing the first extension across the groove The present invention relates to a semiconductor device characterized in that a groove is provided in a region that does not overlap with a gate electrode when seen in a plan view, and the groove is closed with an insulator.

  The third invention of the present application is provided at a position facing the drain electrode across the gate electrode, the gate electrode formed on the semiconductor substrate, the drain electrode formed on the semiconductor substrate, and the gate electrode. A source electrode, and a protective film formed on the semiconductor substrate so as to embed the gate electrode, the drain electrode, and the source electrode, and the gate electrode is formed on the base and in contact with the semiconductor substrate The present invention relates to a semiconductor device that is a mushroom gate having an umbrella portion whose dimension in the current direction is larger than a base portion, and a cavity portion is provided between the semiconductor substrate and the umbrella portion.

  According to a fourth aspect of the present invention, there is provided a step of forming a gate electrode on a semiconductor substrate, a drain electrode on the semiconductor substrate, and a first source disposed on both sides of the drain electrode with the gate electrode interposed therebetween. A step of forming an electrode and a second source electrode; a step of forming an air bridge that electrically connects the first source electrode and the second source electrode; and a gate electrode as viewed in the plane of the air bridge; A step of providing a first opening in a non-overlapping region, a step of forming a protective film over the entire surface of the semiconductor substrate after the formation of the first opening, and a first opening when viewed in plan of the protective film Forming a second opening having a larger opening area than the first opening, and forming a resist film on the entire surface of the semiconductor substrate after forming the second opening; , Seeing in the plane of this resist film Forming a third opening having a larger opening area than the second opening at a position overlapping with the opening and the second opening, and on the resist film after forming the third opening The present invention relates to a method of manufacturing a semiconductor device, comprising: depositing a metal on the first and closing a first opening with the metal; and removing a resist film.

  Further, the fifth invention of the present application includes a step of forming a drain electrode and a source electrode on a semiconductor substrate, and a step of forming a first resist film covering the drain electrode and the source electrode on the semiconductor substrate. A step of forming a second resist film on the first resist film, and a first resist film reaching the first resist film at a portion sandwiched between the drain electrode and the source electrode of the second resist film. A step of forming an opening, and a second opening that reaches the semiconductor substrate and has a size in the current direction smaller than the first opening at a position overlapping the first opening as viewed in the plane of the first resist film A step of selectively etching the semiconductor substrate through the second opening to form a recess in the semiconductor substrate, a second resist film, a first opening, and a second opening Of depositing metal on the surface The metal film, the second resist film, and the first resist film are removed by a lift-off method, and a base portion that is in contact with the semiconductor substrate and an umbrella portion that is formed on the base portion and has a dimension in the current direction larger than the base portion A step of forming a gate electrode having a gate electrode, a step of forming a protective film on the semiconductor substrate so as to embed the drain electrode, the source electrode and the gate electrode, a step of exposing the protective film, and a development process. The present invention relates to a method for manufacturing a semiconductor device, characterized by including a step of removing a protective protective film and forming a hollow portion between a semiconductor substrate and an umbrella portion.

  As described above, according to the present invention, since the gate electrode that affects the high frequency characteristics is arranged in the hollow structure, it is possible to prevent the periphery of the gate electrode from being filled with a plastic having a high dielectric constant during mounting. . Therefore, increase in parasitic capacitance can be reduced, and problems such as internal stress generated in the high-frequency element and mechanical damage to the high-frequency element can be solved.

  Further, according to the present invention, since the cavity is formed around the gate electrode using the shape of the mushroom gate, a semiconductor device capable of suppressing an increase in parasitic capacitance can be easily manufactured.

Embodiment 1 FIG.
FIG. 1 is a cross-sectional view of an active portion of the semiconductor device according to the present embodiment.

  In FIG. 1, a first source electrode 2, a second source electrode 2 ′, a drain electrode 3, and a gate electrode 4 are provided on a GaAs substrate 1 as a semiconductor substrate. Here, the first source electrode 2 and the second source electrode 2 ′ are disposed on both sides of the drain electrode 3 with the gate electrode 4 interposed therebetween.

  The first source electrode 2 and the second source electrode 2 ′ are connected by an air bridge 5. A cavity 6 is formed between the air bridge 5 and the drain electrode 3 and the gate electrode 4. On the other hand, a protective film 7 made of photosensitive polyimide or the like is formed on the air bridge 5.

  In FIG. 1, the air bridge 5 is provided with a first opening 14, but the first opening 14 is closed with a metal 9. Therefore, the first source electrode 2 and the second source electrode 2 ′ are electrically connected by the air bridge 5 through the metal 9. In addition, since the first opening 14 is closed with the metal 9, the semiconductor device has a sealed hollow structure. By disposing the gate electrode 4 that affects the high frequency characteristics in this hollow structure, it is possible to prevent the periphery of the gate electrode 4 from being filled with a plastic having a high dielectric constant during mounting. Therefore, increase in parasitic capacitance can be reduced, and problems such as internal stress generated in the high-frequency element and mechanical damage to the high-frequency element can be solved.

  Next, a method for manufacturing a semiconductor device in the present embodiment will be described with reference to FIGS. 2 and 9 to 12, (a) is a plan view of the semiconductor device, and (b) is a cross-sectional view taken along the line AA ′ of (a). 2 to 12, the same reference numerals as those in FIG. 1 indicate the same parts.

  First, as shown in FIGS. 2A and 2B, the source electrode 2, the drain electrode 3, and the gate electrode 4 are formed on the active region of the GaAs substrate 1 using a known method. For example, after the gate electrode 4 is formed on the GaAs substrate 1, the drain electrode 3, and the first source electrode 2 and the second source electrode 2 ′ disposed on both sides of the drain electrode 3 with the gate electrode 4 interposed therebetween are arranged. Form.

  Next, the air bridge 5 that connects the first source electrode 2 and the second source electrode 2 ′ is formed by using an electroplating method. The air bridge 5 can be made of, for example, gold (Au), and can be formed as follows, for example.

  First, after forming the first resist film 10 on the GaAs substrate 1 shown in FIGS. 2A and 2B, an opening 8 is formed in a part of the first resist film 10 by photolithography. Then, the first source electrode 2 and the second source electrode 2 ′ are exposed (FIG. 3). Next, a plating base film 11 is formed on the first resist film 10 and the exposed source electrode 2 (FIG. 4). The plating base film 11 can be, for example, a laminated film in which an Au film having a thickness of about 200 nm is formed on a Ti film having a thickness of about 50 nm. This laminated film can be formed, for example, by vapor deposition or sputtering.

  Next, a region other than the region where the air bridge 5 of the plating base film 11 is formed is covered with the second resist film 12 (FIG. 5). Then, the GaAs substrate 1 is immersed in a gold plating solution containing a predetermined concentration of gold, and the plating base film 11 is energized to perform electroplating. As a result, Au is deposited on the exposed plating base film 11 to form an Au plating layer 13 as a metal layer (FIG. 6). The film thickness of the Au plating layer 13 can be, for example, about 2 μm to 8 μm.

  Next, after removing the unnecessary second resist film 12, the plating base film 11 exposed by the ion milling method is removed (FIG. 7). Finally, by removing the first resist film 10, the air bridge 5 connecting the source electrodes 2 can be formed (FIG. 8). The air bridge 5 formed by the method of FIGS. 3 to 8 is composed of two layers of a plating base film 11 and an Au plating layer 13, but FIG. 1 and the following FIGS. 9 (a) and 9 (b). 12A and 12B, for the sake of simplicity, the films constituting the air bridge 5 are not particularly distinguished.

  After the air bridge 5 is formed, the first opening 14 is provided by a photolithography method so that the structure shown in FIGS. 9A and 9B is obtained. Here, the position where the first opening 14 is provided is a region that does not overlap the gate electrode 4 when seen in a plan view. This is to prevent the metal 9 from adhering to the gate electrode 4 through the first opening 14 when the metal 9 is deposited in a subsequent process. In particular, in consideration of the overlay accuracy of a mask (not shown) and a resist film (not shown) when the first opening 14 is provided, the first source electrode 2 and the drain electrode 3 are used in a plan view. It is preferable to provide the first opening 14 in a region other than the region sandwiched between the sandwiched portion and the portion sandwiched between the second source electrode 2 ′ and the drain electrode 3.

  In the example of FIGS. 9A and 9B, the first opening 14 is provided above the first source electrode 2 and the second source electrode 2 ′. A first opening 14 may be provided above the drain electrode 3.

  Next, a protective film 7 (for example, a photosensitive material film such as a negative photosensitive polyimide film) is formed on the entire surface of the GaAs substrate 1. The protective film 7 physically protects the surface of the air bridge 5 and also has a function of improving moisture resistance.

  Next, in the protective film 7, a second opening 15 having an opening area larger than the first opening 14 is formed by a photolithography method at a position overlapping the first opening 14 when seen in a plan view. At this time, the portion of the protective film 8 irradiated with light is cured and becomes an unnecessary film for the developing solution, but the protective film 8 below the air bridge 5 is not cured, so that it is dissolved by performing development processing. Removed. Thereby, the structure shown to Fig.10 (a), (b) can be obtained.

  Next, a negative third resist film 16 is formed on the entire surface of the GaAs substrate 1. Then, the third resist film 16 is larger than the second opening 15 at a position overlapping the first opening 14 and the second opening 15 when viewed in plan, as in the case of the protective film 6. A third opening 17 having an opening area is formed (FIGS. 11A and 11B).

  After the third opening 17 is formed in the third resist film 16, the first opening 14 is closed with the metal 9 by the vapor deposition lift-off method to obtain the structure shown in FIGS. Specifically, the metal 9 is deposited on the third resist film 16 after the third opening 17 is formed. At this time, the metal 9 is also deposited on the second opening 15 and the first opening 14 via the third opening 17. Then, the deposited metal 9 grows in the horizontal direction in the figure, whereby the first opening 14 is closed with the metal 9. Thereafter, the third resist film 16 is removed, whereby the structures shown in FIGS. 12A and 12B are obtained.

  The high-frequency characteristics of the semiconductor element are degraded by an increase in parasitic capacitance between the gate electrode and the drain electrode and parasitic capacitance between the gate electrode and the source electrode. Here, the parasitic capacitance is determined by the electrode structure (distance and area between the electrodes) and the relative dielectric constant. Regarding the electrode structure, for example, when the distance between the electrodes is increased, the parasitic capacitance can be reduced, but on the other hand, a trade-off such as an increase in parasitic resistance occurs. For this reason, it is difficult to significantly change the electrode structure. Therefore, to reduce the parasitic capacitance without degrading other characteristics, it is effective to reduce the relative dielectric constant.

  When a semiconductor element is mounted on a plastic package, generally, a plastic having a relative dielectric constant of about 4 covers the periphery of the gate electrode, so that the high frequency characteristics of the semiconductor element are greatly deteriorated. According to the present embodiment, since the hollow portion is provided around the gate electrode, it is possible to effectively suppress the deterioration of the high frequency characteristics even after being mounted on the plastic package. In the present embodiment, it is preferable that the relative dielectric constant of the material formed around the gate electrode is as low as possible. Ideally, a material having a relative dielectric constant of about 1 is preferably used.

  Also, residual stress is generated in plastic due to thermal shrinkage during molding. For this reason, when plastic directly contacts the gate electrode having inferior mechanical strength, the gate electrode may be deformed or peeled off. According to the present embodiment, it is possible to prevent the plastic from coming into contact with the gate electrode by providing the hollow portion around the gate electrode, so that such a problem can be solved.

  FIG. 13 shows a modification of the present embodiment.

  In FIG. 13, a drain electrode 23 and a source electrode 22 provided at a position facing the drain electrode 23 with a gate electrode 24 interposed therebetween are formed on a GaAs substrate 21 as a semiconductor substrate. Further, between the source electrode 22 and the drain electrode 23, a first extending portion 25a and a second extending portion 25b having a structure similar to that of the air bridge 5 of FIG. 1 are provided. The first extension portion 25 a extends from the drain electrode 23 toward the source electrode 22, while the second extension portion 25 b extends from the source electrode 22 toward the drain electrode 23. Further, the first extension part 25a and the second extension part 25b are opposed to each other with the groove part 27 interposed therebetween. Further, a protective film 26 made of a photosensitive material film (for example, photosensitive polyimide) is formed on the GaAs substrate 21 so as to embed the first extending portion 25a and the second extending portion 25b. Has been.

  As shown in FIG. 13, the groove 27 is closed by an insulator 28 such as silicon oxide or alumina. A cavity 29 is formed between the first extension part 25 a and the second extension part 25 b and the gate electrode 24.

  The first extension part 25a and the second extension part 25b can be formed by electroplating. In this case, the first extension part 25a and the second extension part 25b are made of metal, but the source electrode 22 and the drain electrode 23 are electrically connected by closing the groove part 27 with the insulator 28. Thus, a hermetically sealed hollow structure can be formed on the gate electrode 24 without being connected.

  In FIG. 13, the groove 27 is formed above the drain electrode 23, but the groove 27 may be formed above the source electrode 22 in the present embodiment.

  The structure of FIG. 13 can also prevent the periphery of the gate electrode 24 from being filled with a high dielectric constant plastic during mounting. Therefore, increase in parasitic capacitance can be reduced, and problems such as internal stress generated in the high-frequency element and mechanical damage to the high-frequency element can be solved.

Embodiment 3 FIG.
FIG. 14 is a cross-sectional view of the semiconductor device according to the present embodiment.

  In FIG. 14, a drain electrode 33 and a source electrode 32 provided at a position facing the drain electrode 33 across the gate electrode 34 are formed on a GaAs substrate 31 as a semiconductor substrate. A protective film 35 is formed on the GaAs substrate 31 so as to bury the source electrode 32, the drain electrode 33 and the gate electrode 34.

  The gate electrode 34 is a mushroom gate, and has a base portion 34a that is in contact with the GaAs substrate 31 and an umbrella portion 34b that is formed on the base portion 34a and has a dimension in the current direction larger than that of the base portion 34a. This makes it possible to reduce the gate length while reducing the resistance of the gate electrode.

  The present embodiment is characterized in that a cavity portion 36 is provided between the umbrella portion 34 b of the gate electrode 34 and the GaAs substrate 31. With such a structure, an increase in parasitic capacitance can be suppressed.

  15 to 20 are explanatory diagrams of the method for manufacturing the semiconductor device according to the present embodiment. In these drawings, the same reference numerals as those in FIG. 14 indicate the same parts.

First, as shown in FIG. 15, after forming the source electrode 32 and the drain electrode 33 on the active region of the GaAs substrate 31, a first resist film 37 and a second resist film 38 are formed in this order. Here, the second resist film 38 is formed with a thickness larger than that of the first resist film 37. The reason for increasing the thickness of the second resist film 38 is to increase the cross-sectional area of the gate electrode 34. On the other hand, the reason why the film thickness of the first resist film 37 is reduced is that when the base portion 34a becomes longer in the direction perpendicular to the current direction, the base portion 34a near the umbrella portion 34b becomes thinner and the yield decreases. is there. The GaAs substrate 31 can be a substrate in which a semi-insulating GaAs substrate, an i-type InGaAs substrate, an n-type AlGaAs substrate, and an n ⁺ -type GaAs substrate are stacked in this order.

  Next, the second resist film 38 is patterned, and the first resist film 37 that reaches the first resist film 37 is sandwiched between the source electrode 32 and the drain electrode 33 (specifically, a portion where the gate electrode 34 is formed). The opening 39 is formed (FIG. 16).

  Further, the first resist film 37 is patterned using electron beam exposure or the like, and overlaps with the first opening 39 as viewed in the plane of the first resist film 37 (specifically, the base 34a of the gate electrode 34 is formed). A second opening 40 that reaches the GaAs substrate 31 is formed at a position where it is to be formed (FIG. 17). Here, the dimension of the second opening 40 in the current direction (the dimension in the horizontal direction in FIG. 17) is smaller than that of the first opening 39, and specifically corresponds to the dimension of the base 34a in the current direction. Set to the value you want.

  Next, the GaAs substrate 31 is selectively etched using citric acid or the like to form recesses (recesses) 41 as shown in FIG. The concave portion 41 corresponds to a portion where the hollow portion 36 is formed in the present embodiment.

  Next, when a metal such as Ti and Al is vapor-deposited, the metal is deposited on the first opening 39 and the second opening 40 on the second resist film 38 to form a metal film 42 (FIG. 19). . Here, since the dimension of the first opening 39 is larger than the dimension of the second opening 40, the base part 34a and the umbrella part 34b of the gate electrode 34 can be formed simultaneously to form a mushroom gate.

  Finally, the unnecessary metal film 42, the second resist film 38, and the first resist film 37 are removed by a lift-off method to obtain the structure shown in FIG.

  Thereafter, a protective film 35 (for example, a photosensitive material film such as a negative polyimide film) is formed on the GaAs substrate 31 so as to bury the source electrode 32, the drain electrode 33, and the gate electrode. The protective film 35 physically protects the surface of the semiconductor device and also has a function of improving moisture resistance.

  Next, when the protective film 35 is exposed with light of a predetermined wavelength, the protective film 35 is cured except for the lower part of the umbrella part 34b and becomes insoluble in the developer. Next, when development processing is performed, the lower portion of the uncured umbrella portion 34b is dissolved and removed in the developer, and a cavity portion 36 is formed between the GaAs substrate 31 and the umbrella portion 34b (FIG. 14).

  According to the present embodiment, since the cavity is formed around the gate electrode using the shape of the mushroom gate, a semiconductor device capable of suppressing an increase in parasitic capacitance can be easily manufactured.

FIG. 3 is a cross-sectional view of the semiconductor device in the first embodiment. 2A and 2B are explanatory diagrams of the method for manufacturing the semiconductor device in the first embodiment, in which FIG. 1A is a plan view, and FIG. 7 is an explanatory diagram of the method of manufacturing the semiconductor device in the first embodiment. FIG. 7 is an explanatory diagram of the method of manufacturing the semiconductor device in the first embodiment. FIG. 7 is an explanatory diagram of the method of manufacturing the semiconductor device in the first embodiment. FIG. 7 is an explanatory diagram of the method of manufacturing the semiconductor device in the first embodiment. FIG. 7 is an explanatory diagram of the method of manufacturing the semiconductor device in the first embodiment. FIG. 7 is an explanatory diagram of the method of manufacturing the semiconductor device in the first embodiment. FIG. 2A and 2B are explanatory diagrams of the method for manufacturing the semiconductor device in the first embodiment, in which FIG. 1A is a plan view, and FIG. 2A and 2B are explanatory diagrams of the method for manufacturing the semiconductor device in the first embodiment, in which FIG. 1A is a plan view, and FIG. 2A and 2B are explanatory diagrams of the method for manufacturing the semiconductor device in the first embodiment, in which FIG. 1A is a plan view, and FIG. 2A and 2B are explanatory diagrams of the method for manufacturing the semiconductor device in the first embodiment, in which FIG. 1A is a plan view, and FIG. FIG. 10 is a cross-sectional view of another semiconductor device in the first embodiment. FIG. 10 is a cross-sectional view of the semiconductor device in the second embodiment. FIG. 10 is an explanatory diagram of the semiconductor device manufacturing method according to the second embodiment. FIG. 10 is an explanatory diagram of the semiconductor device manufacturing method according to the second embodiment. FIG. 10 is an explanatory diagram of the semiconductor device manufacturing method according to the second embodiment. FIG. 10 is an explanatory diagram of the semiconductor device manufacturing method according to the second embodiment. FIG. 10 is an explanatory diagram of the semiconductor device manufacturing method according to the second embodiment. FIG. 10 is an explanatory diagram of the semiconductor device manufacturing method according to the second embodiment.

Explanation of symbols

1, 21, 31 GaAs substrate 2 First source electrode 2 ′ Second source electrode 22, 32 Source electrode 3, 23, 33 Drain electrode 4, 24, 34 Gate electrode 5 Air bridge 6, 26, 35 Protective film 7 , 29, 36 Cavity 8 Opening 9 Metal 10 First resist film 11 Plating underlayer 12 Second resist film 13 Au plating layer 14 First opening 15 Second opening 16 Third resist film 25a First extension portion 25b Second extension portion 27 Groove portion 28 Insulator 34a Base portion 35b Umbrella portion 37 First resist film 38 Second resist film 39 First opening portion 40 Second opening portion 41 Concave portion 42 Metal film

Claims (11)

A semiconductor device having a plurality of gate electrodes formed on a semiconductor substrate,
A drain electrode formed on the semiconductor substrate;
A first source electrode and a second source electrode disposed on both sides of the drain electrode with the gate electrode interposed therebetween;
An air bridge that electrically connects the first source electrode and the second source electrode;
Between the gate electrode and the air bridge is hollow,
The air bridge is provided with an opening in a region that does not overlap with the gate electrode when seen in a plan view, and the opening is closed with a metal.   The region that does not overlap with the gate electrode is a region other than a region that overlaps with a portion sandwiched between the first source electrode and the drain electrode and a portion sandwiched between the second source electrode and the drain electrode. Item 14. The semiconductor device according to Item 1.   The semiconductor device according to claim 2, wherein the opening is provided above the first source electrode and the second source electrode.   The semiconductor device according to claim 2, wherein the opening is provided above the drain electrode. A gate electrode formed on a semiconductor substrate;
A drain electrode formed on the semiconductor substrate;
A source electrode provided at a position facing the drain electrode across the gate electrode;
A first extension extending from the drain electrode toward the source electrode;
A second extension part extending from the source electrode toward the drain electrode and facing the first extension part across the groove;
The semiconductor device according to claim 1, wherein the groove is provided in a region that does not overlap with the gate electrode when viewed in plan, and the groove is closed with an insulator.   The semiconductor device according to claim 5, wherein the groove is provided above the source electrode.   The semiconductor device according to claim 5, wherein the groove is provided above the drain electrode. A gate electrode formed on a semiconductor substrate;
A drain electrode formed on the semiconductor substrate;
A source electrode provided at a position facing the drain electrode across the gate electrode;
A protective film formed on the semiconductor substrate so as to embed the gate electrode, the drain electrode and the source electrode;
The gate electrode is a mushroom gate having a base portion in contact with the semiconductor substrate and an umbrella portion formed on the base portion and having a dimension in a current direction larger than the base portion,
A semiconductor device, wherein a cavity is provided between the semiconductor substrate and the umbrella. Forming a gate electrode on the semiconductor substrate;
Forming a drain electrode on the semiconductor substrate, and a first source electrode and a second source electrode disposed on both sides of the drain electrode with the gate electrode interposed therebetween;
Forming an air bridge that electrically connects the first source electrode and the second source electrode;
Providing a first opening in a region that does not overlap the gate electrode when viewed in the plane of the air bridge;
Forming a protective film on the entire surface of the semiconductor substrate after forming the first opening;
Forming a second opening having a larger opening area than the first opening at a position overlapping with the first opening as viewed in the plane of the protective film;
Forming a resist film on the entire surface of the semiconductor substrate after forming the second opening;
Forming a third opening having an opening area larger than that of the second opening at a position overlapping the first opening and the second opening as viewed in the plane of the resist film;
Depositing a metal on the resist film after forming the third opening, and closing the first opening with the metal;
And a step of removing the resist film. The step of forming the air bridge includes:
Forming a first resist film on the semiconductor substrate so as to bury the gate electrode, the drain electrode, the first source electrode, and the second source electrode;
Forming an opening reaching the first source electrode and the second source electrode in the first resist film;
Forming a plating base film on the first resist film and the first source electrode and the second source electrode exposed from the opening;
Coating a region other than a region for forming the air bridge on the plating base film with a second resist film;
Forming a metal layer on the plating base film exposed by electroplating;
Removing the second resist film;
Removing the exposed plating underlayer; and
The method for manufacturing a semiconductor device according to claim 9, further comprising a step of removing the first resist film. Forming a drain electrode and a source electrode on a semiconductor substrate;
Forming a first resist film covering the drain electrode and the source electrode on the semiconductor substrate;
Forming a second resist film on the first resist film;
Forming a first opening reaching the first resist film in a portion sandwiched between the drain electrode and the source electrode of the second resist film;
Forming a second opening that reaches the semiconductor substrate and has a smaller dimension in the current direction than the first opening at a position overlapping the first opening as viewed in the plane of the first resist film; When,
Selectively etching the semiconductor substrate through the second opening to form a recess in the semiconductor substrate;
Depositing metal on the second resist film, the first opening, and the second opening;
The metal film, the second resist film, and the first resist film are removed by a lift-off method, and a base that is in contact with the semiconductor substrate and a dimension in the current direction that is formed on the base are larger than the base. Forming a gate electrode having a large umbrella portion;
Forming a protective film on the semiconductor substrate so as to bury the drain electrode, the source electrode, and the gate electrode;
Exposing the protective film;
And a step of removing the uncured protective film by a development process and forming a cavity between the semiconductor substrate and the umbrella.

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