JPS5935485A - Inactivation of pinhole in component layer of solar cell and the like - Google Patents
Inactivation of pinhole in component layer of solar cell and the likeInfo
- Publication number
- JPS5935485A JPS5935485A JP57145987A JP14598782A JPS5935485A JP S5935485 A JPS5935485 A JP S5935485A JP 57145987 A JP57145987 A JP 57145987A JP 14598782 A JP14598782 A JP 14598782A JP S5935485 A JPS5935485 A JP S5935485A
- Authority
- JP
- Japan
- Prior art keywords
- pinhole
- film
- resist
- photoresist
- semiconductor layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000002779 inactivation Effects 0.000 title 1
- 239000004065 semiconductor Substances 0.000 claims abstract description 25
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 22
- 238000000034 method Methods 0.000 claims abstract description 8
- 239000000470 constituent Substances 0.000 claims description 5
- 230000000415 inactivating effect Effects 0.000 claims description 2
- 239000003292 glue Substances 0.000 claims 1
- 230000001678 irradiating effect Effects 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 abstract description 9
- 239000002184 metal Substances 0.000 abstract description 9
- 230000000694 effects Effects 0.000 abstract description 7
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 239000000758 substrate Substances 0.000 abstract description 4
- 239000011521 glass Substances 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 5
- CMSGUKVDXXTJDQ-UHFFFAOYSA-N 4-(2-naphthalen-1-ylethylamino)-4-oxobutanoic acid Chemical compound C1=CC=C2C(CCNC(=O)CCC(=O)O)=CC=CC2=C1 CMSGUKVDXXTJDQ-UHFFFAOYSA-N 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 4
- 239000010931 gold Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000000615 nonconductor Substances 0.000 description 1
- 231100000252 nontoxic Toxicity 0.000 description 1
- 230000003000 nontoxic effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 230000003685 thermal hair damage Effects 0.000 description 1
- 239000012780 transparent material Substances 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Photovoltaic Devices (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、太陽電池等の構成層のピンホールを不活性化
する方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for inactivating pinholes in constituent layers of solar cells and the like.
一般に、太＠電池、コンデンサ％等の製シニ於て、前者
は半導体を、後者は誘電体を電極で挾んだサンドインチ
構造となっている。この場合、半導体や誘電体等の層に
ピンホールが存在するとピンホールを通して短絡が起る
ので、これらのデバイスや部品は働らかない、半導体膜
や誘電体膜にはピンホールの発生が容易に起るので、こ
のピンホールを介しての電圧の短絡効果によるデバイス
の機能低下は大きな問題である。Generally, when manufacturing thick batteries, capacitors, etc., the former has a semiconductor and the latter has a sandwich structure in which a dielectric is sandwiched between electrodes. In this case, if a pinhole exists in a semiconductor or dielectric layer, a short circuit will occur through the pinhole, so these devices or parts will not work, and pinholes can easily occur in the semiconductor or dielectric film. Therefore, the deterioration of device functionality due to the voltage shorting effect through this pinhole is a major problem.
従来、ピンホールによる短絡効果の除去には、太陽電池
に於ては半導体膜を厚く成膜することにより、またコン
デンサに於ては電極に高圧を印加することによりピンホ
ール部分の電極を溶かして飛ばしてしまう方法等が行な
なわれていた。Conventionally, the short circuit effect caused by pinholes has been removed by forming a thick semiconductor film in solar cells, or by melting the electrodes in the pinhole area by applying high voltage to the electrodes in capacitors. Methods were used to make it fly away.
しかし、半導体を不必要に厚く成膜することは材料と製
作時間の無駄であり金属箔を用いたコンデンサに於ての
高電圧印加によるピンホール効果の除去は半導体膜には
熱破壊を起す危険性がある等の問題点があった。However, forming an unnecessarily thick semiconductor film is a waste of materials and manufacturing time, and removing the pinhole effect by applying high voltage to a capacitor using metal foil may cause thermal damage to the semiconductor film. There were problems such as gender.
本発明は、上述の問題点を解決するために、フォトレジ
ストが電気的絶縁物であることを利用する、即ち、フォ
トリングラフィの技術を積極的に採用することにより、
ピンホールをフォトレジストで充填し、ピンホールでの
短絡効果を除去することによりデバイス及び部品の性能
と製造歩留りを向上させる方法を提供する目的でなされ
たものである。以下、本発明の実施例を太陽電池の製作
にとり図に基づき説明する。In order to solve the above-mentioned problems, the present invention takes advantage of the fact that photoresist is an electrical insulator, that is, actively employs photolithography technology.
The objective is to provide a method for filling pinholes with photoresist to improve device and component performance and manufacturing yields by eliminating pinhole shorting effects. EMBODIMENT OF THE INVENTION Hereinafter, embodiments of the present invention will be explained based on the drawings for manufacturing a solar cell.
第１図は太陽電池の構成層のピンホールを不；毒性化す
る方法の工程を説明するための図であ”本・
第１図（ａ）に示すように、ガラス基板ｌ上にネサ膜あ
るいは薄い金属膜２を堆積する。ネサ膜２は光透過性を
有し、かつ、導電性を有するＩｎ５Ｏｓ 、Ｓｎｏｗ等
を用いる。また、金属膜２は金α→、銀（Ａｇ） 、ア
ルミニウム（Ａｌ ）等を用いるが光に対して、半透明
にするために膜厚を／θＯＡ程度に薄く形成する。ざら
にネサ膜あるいは金属膜２の上に半導体８を形成する。Figure 1 is a diagram for explaining the process of making pinholes in the constituent layers of a solar cell non-toxic. Alternatively, a thin metal film 2 is deposited.The NESA film 2 is made of optically transparent and conductive material such as In5Os or Snow.The metal film 2 is made of gold α→, silver (Ag), aluminum ( Al) or the like is used, but the film thickness is formed to be as thin as /θOA in order to make it translucent to light.The semiconductor 8 is roughly formed on the NESA film or the metal film 2.
第１図０はこの半導体層８中のビンホー）Ｎ／４の状Ｍ
ｆｊ−示す。FIG. 10 shows the shape of Binho)N/4 in this semiconductor layer 8
fj-show.
次いでピンホール４がある半導体層８の上に！
フォトレジスト５を塗布すると共にピンホール４内にフ
ォトレジストが充填された状態が第１図中）に示されて
いる。ネサ膜または薄い金属膜２を通して図示矢印方向
に露光を与える。Ｎ光い部分のレジストは除去されて第
１図（Ｃ）の状１岨。Next, on the semiconductor layer 8 where the pinhole 4 is located! A state in which the photoresist 5 is applied and the pinhole 4 is filled with the photoresist is shown in FIG. Exposure is applied through the Nesa film or thin metal film 2 in the direction of the arrow shown. The resist in the N-light part is removed to form the shape shown in FIG. 1(C).
となる。即ち、第１図（Ｃ）のフォトレジスト５ｂ！ｆ
ｆ１Ｆ１ピンホール部分４にフォトレジスト５が充填１
１゛ｉれると同時に、尚かつ、ピンホール４上部にフォ
トレジストが残り、かつ、これらは硬 する。他の部分
のフォトレジストは除去されて半導体層８の表面が露出
している状態を示している。半導体層８及びフォトレジ
スト５の上に導電性（金属膜）膜６を形成すると第１図
Ｃｄ）に示す状態、となり、次いで、予めネサ膜あるい
は金属膜２・、に設けたリード電極７とオーム性電極６
上にリード電極８を設けることにより第１図（りの太陽
電池が構成される。ガラス基板ｌの太陽光を当てる側の
表面上に反射防止膜（図示せず）を被膜して太陽電池は
完成する。becomes. That is, the photoresist 5b of FIG. 1(C)! f
f1F1 Pinhole portion 4 is filled with photoresist 5 1
At the same time as the photoresist is removed, the photoresist remains above the pinhole 4 and hardens. The photoresist in other portions is removed to expose the surface of the semiconductor layer 8. When a conductive (metallic) film 6 is formed on the semiconductor layer 8 and the photoresist 5, the state shown in FIG. Ohmic electrode 6
By providing a lead electrode 8 on the top, the solar cell shown in FIG. Complete.
なお、本実施例に用いるフォトレジストはｎ型のレジス
ト、即ち、光が照射されると重合する型のものである。Note that the photoresist used in this example is an n-type resist, that is, a type that polymerizes when irradiated with light.
第１図の太陽電池に於て、２のネサ膜が、例えばｎ型半
導体ＩｎｇＯｓの場合、半導体層８はＰ型でネサ膜２の
方の禁制帯幅は半導体層３の禁制帯幅より大きく取る様
にすると高効率の窓効果を利用したヘテロ接合太陽電池
が得られる。In the solar cell shown in FIG. 1, if the NESA film 2 is, for example, an n-type semiconductor IngOs, the semiconductor layer 8 is of P type, and the forbidden band width of the NESA film 2 is larger than that of the semiconductor layer 3. If this is done, a highly efficient heterojunction solar cell utilizing the window effect can be obtained.
極めて薄い金属−膜２、例えば金（Ａｕ） 膜の場合
には、半導体層８はｎ型またはＰ型何れを用いてもよく
、゛この様にするとショットキーバリヤ太陽電池が得ら
れる・フォトレジストを塗布した半導体膜等の反対側即
ち図中１，２等が光に対して不透明な基板の場合は光の
代りにＸ線の照射露光牽行う。In the case of an extremely thin metal film 2, for example a gold (Au) film, the semiconductor layer 8 may be of either n-type or p-type; thus, a Schottky barrier solar cell is obtained. If the opposite side of the semiconductor film coated with the substrate, ie, the substrate 1 and 2 in the figure, is opaque to light, X-ray irradiation is performed instead of light.
なお、コンデンサの誘電体におけるピンホールに対して
も太陽電池の構成層の場合と同様の方法が成立するのは
もちろんである。It goes without saying that the same method as in the case of the constituent layers of a solar cell can also be applied to pinholes in the dielectric of a capacitor.
以上詳細に説明したように、本発明は太陽電池等の構成
層の半導体層等のピンホールを７オトレジスト謔光及び
その硬化技術を用いて充填りの向上を図ったものである
。As described above in detail, the present invention aims to improve the filling of pinholes in a semiconductor layer, etc., which is a constituent layer of a solar cell, etc., by using 7-photoresist photoresist and its curing technology.
ル存在する状態を示す図、第１図（ｂ）は半導体層８中
及び焼成が終了した状態の図、第１図（ｄ）は半導体及
びピンホールに充填したフォトレジスト上に導電性膜を
形成した図、第１図（ｇ）はネサ膜又は薄い金属膜とオ
ーム性電極膜に夫々リード電極を付けて太＠電池を完成
した図である。
図中、１はガラス基板、２はネサ膜または薄い金属膜、
８は半導体、４はピンホール、５はフォトレジスト、６
はオーム性電極膜、７及び８はリード電極である。
（ｄ）
↑争↑今↑↑↑FIG. 1(b) is a diagram showing the inside of the semiconductor layer 8 and the state after firing, and FIG. 1(d) is a diagram showing a state in which a conductive film is present in the semiconductor layer 8 and the photoresist filled in the pinhole. The formed diagram, FIG. 1(g), is a diagram of a completed thick@ battery by attaching lead electrodes to the Nesa film or thin metal film and the ohmic electrode film, respectively. In the figure, 1 is a glass substrate, 2 is a Nesa film or a thin metal film,
8 is a semiconductor, 4 is a pinhole, 5 is a photoresist, 6
is an ohmic electrode film, and 7 and 8 are lead electrodes. (d) ↑Conflict↑Now↑↑↑
Claims (1)
塗布し、該フォトレジストを前記ピンホールに充填せし
めると共に、前記フォトレジストで前記半導体膜を蔽う
工程と、前記フォトレジストを塗布した半導体膜等の反
対側から≠あるいはＸ糊を照射し、前記ピンホールに充
゛填せしめたフォトレジストに露光し現像、リンス、焼
成を行う工程によって、前記ピンホールを硬化したフォ
トレジストで塞ぐことを特徴とする太陽電池等の構成層
のピンホール不活性化方法。a step of applying a photoresist on a semiconductor film etc. having a pinhole, filling the pinhole with the photoresist, and covering the semiconductor film with the photoresist; The pinhole is closed with a hardened photoresist by irradiating ≠ or X glue from the opposite side, exposing the photoresist filled in the pinhole, developing, rinsing, and baking. A method for inactivating pinholes in constituent layers of solar cells, etc.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57145987A JPS5935485A (en) | 1982-08-23 | 1982-08-23 | Inactivation of pinhole in component layer of solar cell and the like |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57145987A JPS5935485A (en) | 1982-08-23 | 1982-08-23 | Inactivation of pinhole in component layer of solar cell and the like |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5935485A true JPS5935485A (en) | 1984-02-27 |
| JPS6240871B2 JPS6240871B2 (en) | 1987-08-31 |
Family
ID=15397560
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57145987A Granted JPS5935485A (en) | 1982-08-23 | 1982-08-23 | Inactivation of pinhole in component layer of solar cell and the like |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5935485A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0236936A2 (en) * | 1986-03-11 | 1987-09-16 | Siemens Aktiengesellschaft | Method for avoiding short-circuits during the production of electrical components, particularly for amorphous silicon solar cells |
| EP0603260A4 (en) * | 1991-09-13 | 1994-07-27 | United Solar Systems Corp | Photovoltaic device including shunt preventing layer and method for the deposition thereof. |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01319579A (en) * | 1988-06-20 | 1989-12-25 | Shin Etsu Chem Co Ltd | Production of cover layer film |
| JPH0379477U (en) * | 1989-12-01 | 1991-08-13 |
-
1982
- 1982-08-23 JP JP57145987A patent/JPS5935485A/en active Granted
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0236936A2 (en) * | 1986-03-11 | 1987-09-16 | Siemens Aktiengesellschaft | Method for avoiding short-circuits during the production of electrical components, particularly for amorphous silicon solar cells |
| EP0236936A3 (en) * | 1986-03-11 | 1989-03-29 | Siemens Aktiengesellschaft | Method for avoiding short-circuits during the production of electrical components, particularly for amorphous silicon solar cells |
| EP0603260A4 (en) * | 1991-09-13 | 1994-07-27 | United Solar Systems Corp | Photovoltaic device including shunt preventing layer and method for the deposition thereof. |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6240871B2 (en) | 1987-08-31 |
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