JPS5996778A - Manufacture of photoelectric conversion device - Google Patents

Manufacture of photoelectric conversion device

Info

Publication number
JPS5996778A
JPS5996778A JP57206807A JP20680782A JPS5996778A JP S5996778 A JPS5996778 A JP S5996778A JP 57206807 A JP57206807 A JP 57206807A JP 20680782 A JP20680782 A JP 20680782A JP S5996778 A JPS5996778 A JP S5996778A
Authority
JP
Japan
Prior art keywords
conductive film
photoelectric conversion
electrode
open groove
conversion device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57206807A
Other languages
Japanese (ja)
Inventor
Shunpei Yamazaki
舜平 山崎
Satsuki Watabe
渡部 五月
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP57206807A priority Critical patent/JPS5996778A/en
Priority to IN511/DEL/83A priority patent/IN160665B/en
Publication of JPS5996778A publication Critical patent/JPS5996778A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/042PV modules or arrays of single PV cells
    • H01L31/0445PV modules or arrays of single PV cells including thin film solar cells, e.g. single thin film a-Si, CIS or CdTe solar cells
    • H01L31/046PV modules composed of a plurality of thin film solar cells deposited on the same substrate
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy

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  • Life Sciences & Earth Sciences (AREA)
  • Sustainable Development (AREA)
  • Engineering & Computer Science (AREA)
  • Sustainable Energy (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Photovoltaic Devices (AREA)

Abstract

PURPOSE:To reduce a necessary area at the joint of a plurality of photoelectric conversion elements provided in series connection on a photo transmitting insulation substrate and thus simplify the process by using laser scribing method. CONSTITUTION:The first photo transmitting conductive film 2 is formed on the photo transmitting insulation substrate 1, and the first open groove 13 is formed by cutting and isolating this conductive film 2 to a plurality of segments by using a laser light. A non single crystal semiconductor layer 3 having a P-I-N or a P-N junction is formed thereon, and the second open groove 18 is formed by cutting and isolating this layer 3 and the conductive film 2 on the lower side thereof to a plurality of segments by a laser light. Further, the second conductive film 4 is formed on the surface thereof, and the third open groove 20 is formed by cutting and isolating this conductive film 4 or this and the layer 3 on the lower side thereof, resulting in the constitution of a plurality of photoelectric conversion elements each other connected in series.

Description

【発明の詳細な説明】 この発明は、P工NまたはPN接合を少なくとも1つ有
するアモルファス半導体を含む非単結晶半導体を透光性
絶縁基板上に設けられた光電変換素子(単に2子ともい
う)を?:数個直列接続して、高い電圧の発生が可能な
光電変換装置およびその作製方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a photoelectric conversion element (also simply referred to as dyad) in which a non-single-crystal semiconductor including an amorphous semiconductor having at least one P-N or PN junction is provided on a light-transmitting insulating substrate. )of? :Relates to a photoelectric conversion device that can generate high voltage by connecting several photoelectric conversion devices in series, and a method for manufacturing the same.

この発明は、複数の素子間の連結に必要な面積を従来の
マスク合わせ方式の1/10〜1/1oo、(cするた
め、レーザスクライブ方法を用いたことを特徴としてい
る。
The present invention is characterized in that a laser scribing method is used to reduce the area required for connecting a plurality of elements to 1/10 to 1/10th (c) of the conventional mask alignment method.

この発明は、連結部での電気的接合を電極を構成する被
膜の表面ではなく、側面を用いることによシ、連結部で
の必要面積を減少ぜしめたことを特徴としている・○ この発明では、従来マスク合わせ方式においてその連結
部は5〜1mmを必要としていたが、これをその1/1
0〜1/100の350〜30μ好ましくは200〜5
0μにすることにより、この連結部を10fs    
                        プ
II]〜5に・要とするハイブリッド方式ニ゛珪≦F、
光電変換装置として用いられる全パネルの光起電力見上
せしめたことを特徴とする。
This invention is characterized in that the required area at the connection part is reduced by using the side surface of the coating that constitutes the electrode instead of the surface of the coating that makes up the electrode for electrical connection at the connection part.○ This invention In the conventional mask alignment method, the connecting part required 5 to 1 mm, but this has been reduced to 1/1 of that.
0 to 1/100 of 350 to 30 μ, preferably 200 to 5
By setting it to 0 μ, this connection part can be set to 10 fs.
Part II] - 5 - Required hybrid method Niji≦F,
It is characterized by showing the photovoltaic power of all the panels used as a photoelectric conversion device.

この発明ではレーザビームスクライブ方式を用いること
によシ、合せマークを基準としてこのスフ−ライブわ1
 *アドレスをあらかじめコンピュータ(マイクロ・コ
ンピュータ)のメモリに記憶させておく【とによシ、従
来よシ知られたマスク合わせ方式で必要なマクスのすれ
、そり、合せ精度に対する製造歩留シの低下等のすべて
の製造での価格増、歩留り減の原因を一気に排除せしめ
たことを特徴とする。
In this invention, by using a laser beam scribing method, this square live 1 is created using the alignment mark as a reference.
*Storing the address in the memory of the computer (microcomputer) in advance [In addition, the mask rubbing, warping, and alignment precision required by the conventionally known mask alignment method will reduce manufacturing yield. It is characterized by eliminating all causes of price increases and yield decreases in manufacturing at once.

従来、光電変換装置(以下単に装置という)即ち同一基
板上に複数の素子を配置し、それを集積比重たはハイブ
リッド化した装置はその実施例が多く知られている。
Conventionally, many examples of photoelectric conversion devices (hereinafter simply referred to as devices), that is, devices in which a plurality of elements are arranged on the same substrate and are integrated or hybridized, are known.

例えば特開昭55−4994、特開昭55−1242’
74さらに本発明人の出1頭になる特願昭54−900
97/90098/90099 (昭和54.7.16
出願)が知られている。特にこの本発明人の出願は、半
導体を5iO−8iのへテロ接合とし、単に他のアモル
ファスシリコン半導体を用いる場合と異ならせておシさ
らにこの半導体として、アモルファス構造以外に微結晶
構造を含む水素またはノ・ロゲン元素か添加されたPN
またはP工N接合を少なくとも1つ有する非単結晶半導
体であるという特徴を有する。
For example, JP-A-55-4994, JP-A-55-1242'
74 Furthermore, the inventor filed a patent application in 1984-900 for one horse.
97/90098/90099 (Showa 54.7.16
application) is known. In particular, this application by the present inventor uses a 5iO-8i heterojunction as a semiconductor, which is different from the case where other amorphous silicon semiconductors are used. or PN added with
Alternatively, it is characterized by being a non-single crystal semiconductor having at least one P-N junction.

しかしこれら従来の発明においては、第1図にそのたて
断面図を示すが、すべてマスク合せ方式であり、合せ精
度が不十分であシ、また連結部に大きな面積を必要とし
ていた。
However, in these conventional inventions, a vertical sectional view of which is shown in FIG. 1, all of them are based on the mask alignment method, and the alignment accuracy is insufficient and a large area is required for the connecting portion.

例えば金属マスクを用い、直接選択的に導電層重たは半
導体層を作製する方式においては、この選択性を与えた
マスクが被膜形成中KO05〜3mmずれてしまう場合
がある。さらにこのマスク上に被膜成分が形成されるた
め、マスクが汚染され、またマスクがそって形成される
被膜L7J)FIL%部が明瞭でなくなる等多くの欠点
を有する。
For example, in a method of directly and selectively producing a conductive layer or a semiconductor layer using a metal mask, the mask that provides this selectivity may shift by KO05 to 3 mm during film formation. Furthermore, since a coating component is formed on this mask, the mask is contaminated, and there are many drawbacks such as the mask being warped and the coating L7J) FIL% portion formed becomes unclear.

さらにスクリーン印刷法等の基板上に全体的に形成され
た導体または半導体を独立K %%=択的にマスクを用
いてエツチング除去する方法が知られている。しかしか
かる方法においては、スクリーン印刷用のマスクの位置
合わせの工程、レジストのコーティング工程、ベーク固
化工程、4体−または半導体のエツチング工程、レジス
トの除去工程等きわめて工程に時間がかかり、そのため
製造価格上昇がまぬがれ得なかった。
Furthermore, a method is known in which a conductor or semiconductor formed entirely on a substrate is selectively etched away using a mask, such as a screen printing method. However, in this method, the process is extremely time consuming, such as the process of aligning the mask for screen printing, the process of coating the resist, the process of baking and solidifying, the process of etching the 4-body or semiconductor, and the process of removing the resist. The rise was inevitable.

しかし本発明の光電変換装置特に薄膜型の光電変換装置
にあっては、それぞれの薄膜層である電極用導電性層、
捷だ半導体層はともK 500A〜1μであシ、レーザ
スクライブ方式を用いることにより、全くマスク合わせ
を必要としないことが判明した。
However, in the photoelectric conversion device of the present invention, particularly in the thin film type photoelectric conversion device, the conductive layer for electrodes, which is each thin film layer,
It has been found that the twisted semiconductor layers each have a thickness of K500A to 1μ, and by using a laser scribing method, no mask alignment is required.

その結果従来のマスク合わせ工程のかわりに本発明にお
いてはマスクを全く用いないためスクライブ工程という
が、このスクライブ工程がきわめて簡単であるため、装
置の製造コストの低下をもるというきわめて画期的な光
電変換装置を提供することにある。
As a result, instead of the conventional mask alignment process, the present invention does not use a mask at all, so it is called a scribing process, and since this scribing process is extremely simple, it is an extremely innovative process that reduces the manufacturing cost of the device. An object of the present invention is to provide a photoelectric conversion device.

さらに本発明はこのレーザスクライブ工程を用いるに加
えて、そのスクライブラインの合せ精度に冗長(余裕)
度をもたせたことが重要である。
Furthermore, in addition to using this laser scribing process, the present invention has a redundancy (margin) in the alignment accuracy of the scribe line.
It is important to have a degree of precision.

そのため隣り合った菓子間の第1の電極(下側)と他の
素子の第2の電極(上f11電極)とが第1の電極の側
面において電気的に連結されることにより、スクライブ
ラインの開溝の位置に冗長度をもたせることができた。
Therefore, the first electrode (lower side) between adjacent sweets and the second electrode (upper f11 electrode) of the other element are electrically connected on the side surface of the first electrode, so that the scribe line is It was possible to provide redundancy in the position of the open groove.

以下に図面′に従って従来例および本発明の構造を記す
The structure of a conventional example and the present invention will be described below according to the drawing.

第1図は従来より知られたマスク合せ方式の光電変換装
置のたて断面図である。
FIG. 1 is a vertical sectional view of a conventionally known photoelectric conversion device using a mask alignment method.

図面において透光性基板(例えばガラス板)(1)上に
第1の電極を栖成する透光性導電膜(CTFと略記する
)を第1のマスク合わせ工程により進択的に形成させる
。さらに半導体層(3)を第2のマスク合わせ工程によ
り同様に選択的に形成させる。
In the drawings, a transparent conductive film (abbreviated as CTF) forming a first electrode is selectively formed on a transparent substrate (for example, a glass plate) (1) by a first mask alignment step. Further, a semiconductor layer (3) is similarly selectively formed by a second mask alignment step.

さらに第3のマスク合せ工程によシ第2の電極←)が設
けられている。
Further, a second electrode ←) is provided in the third mask alignment step.

第1図において素子(1])(31)との間に連結部α
■を有し、連結部においてはCTFの一方の側面α0を
半導体層(3)がおおい、他方のCTFの表面(1ユを
半導体層(3)がおおわ゛iτンバめ、CTFの間α→
は1〜5mm例えば3mmのすきまを必要とする。さら
に第1の電極(3’i’)と第2の電極(38)はα→
の表面で電気的に連結するが、この部分を(3つ)の第
2の電極がマスクのぼけで発生するひろがシをも含めて
ショートシてはいけないため1〜5mm例えば3mmの
間隙(6)を必要とする。これら3つのマスクには全く
のセルファライン性がないため、連結部αつにおいては
1〜8mm代表的には4mmを必要としてしまう。
In Fig. 1, there is a connection part α between elements (1] and (31).
In the connection part, the semiconductor layer (3) covers one side α0 of the CTF, and the semiconductor layer (3) covers the surface (1 unit) of the other CTF, so that α→
requires a clearance of 1 to 5 mm, for example 3 mm. Furthermore, the first electrode (3'i') and the second electrode (38) are α→
electrically connected on the surface of the mask, but this part should not be short-circuited by the (three) second electrodes, including the wide area caused by blurring of the mask. 6) is required. Since these three masks have no self-alignment properties, the connecting portions α require 1 to 8 mm, typically 4 mm.

さらにこれK1mm以下とすると、そのマスク合わせ精
度はきわめて屓宥であシ、歩留シが極端に低下してしま
う。この連結部αつの間隙を5m、m以上とすると、例
えば20cmX60cmに巾15Inmの素子有効面積
は周辺部を考慮すると75%にとどまってしまっていた
Furthermore, if K is less than 1 mm, the mask alignment accuracy will be extremely poor and the yield will be extremely reduced. If the gap between the connecting parts α is set to 5 m or more, the effective area of a device measuring, for example, 20 cm x 60 cm and a width of 15 Inm remains at 75% when the peripheral area is taken into account.

本発明はかかる工程の複雑さを排除し、有効面積が85
〜97係例えば92%KC1で高めることができるとい
うきわめて画期的な光電変換装置を提供することにある
The present invention eliminates such process complexity and reduces the effective area to 85.
An object of the present invention is to provide an extremely innovative photoelectric conversion device that can increase the KC1 to 97%, for example, 92% KC1.

以下に図面に従ってその詳細を示す。The details are shown below according to the drawings.

第2図は本発明の製造工程を示すたて断面図である。FIG. 2 is a vertical sectional view showing the manufacturing process of the present invention.

図面において透光性基板(1)例えばガラス板(例えば
厚さ1.2mm長さく図面では左右方向) 6o c 
m。
In the drawing, the transparent substrate (1) is, for example, a glass plate (for example, 1.2 mm thick and long in the left and right direction in the drawing) 6o c
m.

巾20 c m)を用いた。さらにこの上面に全面にわ
たって透光性導電膜例えば工TO(1500^)+Sn
O。
A width of 20 cm) was used. Furthermore, a light-transmitting conductive film such as TO(1500^)+Sn is applied to the entire upper surface.
O.

(200〜400大)またはハロゲン元素が添加された
酸化スズを主成分とする透光性導電膜(1500〜zo
ooi)を真空蒸着法、LPcVD法またはプラズマC
VD法またはスプレー法により形成させた。
(200 to 400 scale) or a transparent conductive film whose main component is tin oxide added with a halogen element (1500 to 400 scale)
ooi) by vacuum evaporation method, LPcVD method or plasma C
It was formed by a VD method or a spray method.

この後この基板の下側または上側により YAGレーザ
加工加工日本レーザ製)により出力5〜8W出力を加え
、スポラ1−v3.o〜’70 pf代表的にはスクラ
イビングにより形成された開溝は、巾約50μ長さ20
cmとし、各素子(31)<1◇を構成する巾は10〜
20mm例えば15mm (1つのセグメントは15m
mX20cmとする)、とした。かくして第1の電極を
構成するc T F (2)を切断分離して開溝を形成
した0この後この上面にプラズマCVD法またはLPC
!VD法によりPNまたはP工N接合を有する非単結晶
半導体層を0.2〜0.7μ代表的には0.4〜0.5
μの厚さに形成させた。その代表例はP型半導体(Si
xO,、x =0.250〜150X)−1型アモルフ
ァスまたはセミアモルファスシリコン半導体(0,4〜
0.5μ)−N型の微結晶(100〜200Å)を有す
る半導体よりなる]一つのP工N接合を有する非単結晶
半導体、またはP型半導体(SixC!+−リーN型、
P型Si半導体−1型S IX G e、−g半導体−
N型S1半導体よシなる2つのP工N接合と1つのPN
接合を有するタンテム型のP工NP工NIIIIIII
IPIN接合の半導体である。
After that, an output of 5 to 8 W was applied to the lower or upper side of this substrate using YAG laser processing (manufactured by Nippon Laser), and an output of 5 to 8 W was applied to the lower or upper side of the substrate. o~'70 pf Typically, the open groove formed by scribing is approximately 50μ in width and 20μ in length.
cm, and the width of each element (31) < 1◇ is 10~
20mm, e.g. 15mm (one segment is 15m)
m x 20 cm). In this way, the cTF (2) constituting the first electrode was cut and separated to form an open groove.
! A non-single crystal semiconductor layer having a PN or P-N junction is formed by the VD method to a thickness of 0.2 to 0.7μ, typically 0.4 to 0.5μ.
It was formed to a thickness of μ. A typical example is a P-type semiconductor (Si
xO,, x = 0.250~150X)-1 type amorphous or semi-amorphous silicon semiconductor (0,4~
A non-single crystal semiconductor having one P-N junction, or a P-type semiconductor (SixC!+-Lee N type,
P-type Si semiconductor - 1-type S IX G e, -g semiconductor -
Two P-N junctions and one PN made of N-type S1 semiconductor
Tantem-type P-type NP-type NIIIIII with joint
It is an IPIN junction semiconductor.

かかる非単結晶半導体層(3)を全面に均一の膜厚で形
成させた。さらに第2図(B) K示される如く、第1
の開溝の4方向に第2の開溝(181を第2のレーザス
クライブ工程により形成させた。このレーザはガラス(
1)の下方同型たはこの基板の上方のいずれから行なっ
てもよいO かくして第2の開溝(IgIは第1の電極の側面を鴨(
9)を露出させた。この第2の開基のa+面(9)は第
1の電極(1・の側面(1かよりfL側であればよく、
その極端な例として、図面に示される如く、第1の電極
(31)の内部に入ってしまってもよい。さらに従来例
に示される如く、第1の電極の表面(1・υを露呈させ
ることは必ずしも必要ではなく、レーザ光が5〜IOW
で多少J31 ?−11)、このOT’Fをすべて除去
してしまっぐ側面(第2図(B)) −cあっ□4何ら
実用よ問題はない。即ちレーザ光の出カッ<1170強
さに余裕を与えることができることが本発明の工業的応
用の際きわめて重要である。
Such a non-single crystal semiconductor layer (3) was formed to have a uniform thickness over the entire surface. Furthermore, as shown in Figure 2 (B) K, the first
Second open grooves (181) were formed in four directions of the open grooves by a second laser scribing process.
1) can be done either from the lower side of the substrate or from above this substrate.
9) was exposed. The a+ face (9) of this second open group may be on the fL side of the first electrode (1),
As an extreme example, it may enter inside the first electrode (31) as shown in the drawings. Furthermore, as shown in the conventional example, it is not necessarily necessary to expose the surface (1·υ) of the first electrode, and the laser beam is
So some J31? -11) The aspect of removing all this OT'F (Fig. 2 (B)) -c Ah □4 There is no problem in practical use. That is, it is extremely important for the industrial application of the present invention to be able to provide a margin for the intensity of the laser light output <1170.

第2図において、さらにこの上面に第2図(c)に示さ
れる如く、史面電極を形成し、さらに第3のレーザスク
ライブ法の切断分離用の開溝00を設けた。
In FIG. 2, a surface electrode was further formed on this upper surface as shown in FIG. 2(c), and an opening groove 00 for cutting and separation in the third laser scribing method was provided.

この第2の電極は透光性導電膜を’700〜1400久
工To (J!化インジュームスズ〕を形成し、さらに
その上面に銀を300〜3000^の厚さに形成し、さ
らにその上面にアルミ、ニュームまたはアルミニューム
とニッケルとの二層膜を形成させた。例えば工TOを1
050λ、銀を1oooX、さらにニッケルる。さらに
ニッケルは外部引出し電極(ト)との密着性を向上させ
るためのものである。これらは電子ビーム蒸着法または
プラズマCVD、法を用いて半導体層を劣化させる30
0’0以下の温度で形成させた。
This second electrode is made by forming a transparent conductive film with a thickness of 300 to 3000 mm on its upper surface, and then forming a layer of silver on its upper surface to a thickness of 300 to 3000 mm. A double-layer film of aluminum, newium, or aluminum and nickel was formed on the top surface.
050λ, add 1oooX silver, and add nickel. Furthermore, nickel is used to improve adhesion with the external lead electrode (g). These methods degrade semiconductor layers using electron beam evaporation or plasma CVD.
It was formed at a temperature of 0'0 or less.

この工Toは半導体と1吋イ6との反応による1雀性の
向上にも役立っている。
This To is also useful for improving the performance by the reaction between the semiconductor and the I6.

かくの如き裏面電極をレーザ光を上方より照射した場合
を以上においては示している。このレーザ光は半導体層
を少しえぐり出しpAZb2y、素子(31)フ (11)間の開溝部での残存金属によるリークの発生を
防止した。このえぐり出しは第1の電極用のCTFKま
で到達しないことが好ましく、この半導体層弁のレーザ
出力に余S    a、=が工業上重要である。
The above example shows a case where such a back electrode is irradiated with laser light from above. This laser light slightly gouged out the semiconductor layer to prevent leakage due to residual metal in the open groove between pAZb2y and element (31) and f (11). It is preferable that this gouging does not reach the CTFK for the first electrode, and the remainder S a,= of the laser output of this semiconductor layer valve is industrially important.

かくして第2図(c) K示される如く、複数の素子(
31)、(1υを連結部αうで直列接続する光電変換装
置を作ることができた。
Thus, as shown in FIG. 2(c), a plurality of elements (
31), (We were able to create a photoelectric conversion device in which 1υ were connected in series at the connecting part α.

第2図(D)はさらに本発明を光電変換装置として完成
させんとしたものであり、即ちパッシベーション膜とし
てプラズマ気相法によシ窒化珪素膜(2)を500〜2
00OAの厚さに形成した。さらに外部引出し端子(イ
)を周辺部(5)Kで設けた。これらにポリミイド、ポ
リアミド、カプトンまたはエポキシ等の有機樹脂(2)
を充填した。
FIG. 2(D) shows the attempt to further complete the present invention as a photoelectric conversion device, that is, a silicon nitride film (2) of 50 to 2
It was formed to a thickness of 00OA. Furthermore, an external lead terminal (A) was provided at the peripheral portion (5)K. Organic resins such as polymide, polyamide, kapton or epoxy (2)
filled with.

かくして照射光(1■に対しこの実施例の如き基板(6
0cmX20cm) において各素子を14.35mm
Thus, for each irradiation light (1), the substrate as in this example (6
0cm x 20cm), each element is 14.35mm
.

連結部150μ外部引出し電極部10mm、周辺部4m
mにより実質的K 580mmX192mm内に40段
を有し有効面積(19Ym m X 14゜35mmx
4ot=1xo27mL即ち91.8%)を得ることが
できた。その結果セグメントが10.6係の変換効率を
有する場合、パネルにて9゜7% (AMI (1oo
mw/Cm) Kて11.6Wの出力電力を有せしめる
ことができた。
Connection part 150μ External extraction electrode part 10mm, peripheral part 4m
Effective area (19Ym m x 14゜35mm x
4ot=1xo27mL, or 91.8%). As a result, if the segment has a conversion efficiency of 10.6, the panel will have a conversion efficiency of 9.7% (AMI (1oo
mw/Cm) K, it was possible to have an output power of 11.6W.

これは従来のマスク合せ方式で行なった場合の55%(
40段の場合)K比べてきわめて著しい効果毎  ・ である。さらK【マスクを用いないため、大面積パネル
の製造工程に°おいて伺らの工業上の支障がなく、大電
力発生用の大面積低価格大量生産用にきわめて適してい
る。
This is 55% (
(In the case of 40 stages) The effect is extremely significant compared to K. Moreover, since no mask is used, there is no industrial problem in the manufacturing process of large-area panels, making it extremely suitable for large-area, low-cost mass production for generating large amounts of power.

さらに第2図(D) において、レーザ出力を強めにす
ると、開溝部の周辺の切れがよいが、この際下部を多少
損傷しても実用上全く問題はない。
Furthermore, in FIG. 2(D), when the laser output is increased, the peripheral part of the groove can be cut better, but there is no practical problem even if the lower part is slightly damaged.

特に第1の電極と第2の電極との電気的連結を第1の電
極の側部で行なうことができるため、このコンタクト部
の面積を十分少なくさせることができた。
In particular, since the first electrode and the second electrode can be electrically connected at the side of the first electrode, the area of the contact portion can be sufficiently reduced.

また第2図(B) K示しであるが、半導体層(3)の
レーザスクライブを1本の開溝線とすると、電極は(3
2)のみとなるが、これ1i開考的にイ介支ず1ど(3
3)の電流をさらに有効に利用することも可能である。
In addition, as shown in FIG. 2(B) K, if the laser scribe of the semiconductor layer (3) is one groove line, the electrode will be (3
2), but this 1i conceptually does not support 1d(3).
It is also possible to use the current in 3) more effectively.

第3図、第4図、第5図は3回のレーザスクライブの位
置関係を示したたて断面図および如く平面図である。番
号等は第2図と同様である。
FIGS. 3, 4, and 5 are a vertical sectional view and a plan view showing the positional relationship of three laser scribes. Numbers etc. are the same as in FIG. 2.

第3図は連結部αJにおいて第2の゛レーザスクライブ
工程を基板の上方より行ない、開溝0QKおいが第1の
電極(2)、第2の電極よシも周辺部で犬きくな砺鉱第
1の電極をおおいかクシ、それらの電極間でのリーク電
流の発生を防止している。
Fig. 3 shows that the second laser scribing process is performed from above the substrate at the connecting part αJ, and the open groove 0QK is the same as the first electrode (2) and the second electrode as well. The first electrode is covered or combed to prevent leakage current between the electrodes.

第4図は第1の開溝部0埠、第2の開溝部α杓とが部に
必要なロス面積を最少((シたもので、:LOC1μま
たは60μの連結部を有せしめることができた。
Figure 4 shows that the first open groove part 0 and the second open groove part α have the minimum loss area ((), and it is possible to have a connecting part with an LOC of 1μ or 60μ. did it.

第5図は第3図、第4図の中間で、一般的な連結部のた
て断面図を示している。この図面において第1、第2の
開溝部50〜30μ、第3の開溝部′75〜50μにお
いて、150μ〜100μの連結部の巾を有せしめるこ
とができた。
FIG. 5 is located midway between FIGS. 3 and 4, and shows a vertical sectional view of a typical connecting portion. In this figure, the width of the connecting portion was 150μ to 100μ in the first and second opening grooves 50 to 30μ and the third opening groove 75 to 50μ.

以上のYAGレーザのスポット層をその出力3〜の連結
部をよシ小さく1、ひいtは光電変換装置としての有効
面積を向上させることができた。
By making the spot layer of the YAG laser as described above smaller than the connecting portion between its outputs 3 and 3, it was possible to improve the effective area as a photoelectric conversion device.

第6図は外部引出し電極部を拡大して示したものである
FIG. 6 is an enlarged view of the external lead electrode section.

第6図(A)は第2図に対応しているが、外部引出し電
極(5)はハンダ付02)によシ上側電極(4)と連結
している。さらに第6図(B)は下側の第1の電極に連
結したジヨイント04)が第2の電極材料により設けら
れ、ハンダ(42)を介して外部引出し電極α3)によ
り設けられている。本来の第2の電極(4)は第3の開
溝部(ハ)によシ切断され、その切断面は窒化珪素膜に
よシハツシベーションされている。
FIG. 6(A) corresponds to FIG. 2, but the external lead-out electrode (5) is connected to the upper electrode (4) through soldering 02). Furthermore, in FIG. 6(B), a joint 04) connected to the first electrode on the lower side is provided by a second electrode material, and is provided by an external lead electrode α3) via a solder (42). The original second electrode (4) is cut by the third groove (c), and the cut surface is etched with a silicon nitride film.

1角(樹脂モールド(イ)は引出し電極(5)、(43
)固定用におおわれており、さらにこのパネル例えば4
0cmX20cm ’4たは60cmX20cmを6ケ
または4ケ直tKl+ Kアルミサツシ枠によりパッケ
ージされ、120cmX40crnのN E D O規
格のパネルを設けることが可能である。
One corner (resin mold (a) has lead electrodes (5), (43)
) is covered for fixation, and this panel, for example 4
It is possible to package 0 cm x 20 cm '4 or 60 cm x 20 cm with 6 or 4 straight tKl+K aluminum sash frames, and provide a 120 cm x 40 crn NED O standard panel.

またとのNEDO規格のパネルはシーフレックスによシ
他のガラス板を遅xの上側にはりあわせた合わせガラス
とし、その間に光電変換装置を配置尽 し、籠等に対いし強度の増加をはかることを有効である
In addition, the NEDO standard panel is made of laminated glass made by laminating another glass plate on the top of the slow x, and a photoelectric conversion device is placed between them to increase the strength against cages etc. That is valid.

第2図〜第6図において光入射は下側のガラス板よシと
した。しかし本発明はその光入射側を下側に限定するも
のではない。
In FIGS. 2 to 6, light was incident through the lower glass plate. However, the present invention does not limit the light incident side to the lower side.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の光電変換装置のたて断面図であるO 第2図は本発明の光電変換装置の製造工程を示すたて断
面図である。 智杵出b′1′1人 令4 (A )                     
   CBンイ6鎚
FIG. 1 is a vertical cross-sectional view of a conventional photoelectric conversion device. FIG. 2 is a vertical cross-sectional view showing the manufacturing process of the photoelectric conversion device of the present invention. Tomoki Izuru b'1'1 person order 4 (A)
CB 6 hammers

Claims (1)

【特許請求の範囲】[Claims] 1 透光性絶縁基板上に第1の電極を構成する第1の透
光性導電膜を形成する工程と、該第1の導電膜を複数の
セグメン)Kレーザ光を用いて切断分離し第1の開溝を
形成する工程と、前記導電膜よおよび前記溝上KP工N
tたはPN接合を少なくとも1つ有する非単結晶導電膜
とをレーザ光により複数のセグメントに切断分離して第
2の開溝°を形成する工程と前記非単結晶半導体表面お
よび前記切断面の゛非単結晶半導体と第1の導電膜との
表面に第2の導電膜を形成する工程と、該第2の導電膜
、または該導電膜およびその下側の前記非単結晶半導体
とをレーザ光により切断分離して第3の開溝を形成する
工程とにより、複数の光電変換素子を構成し、かつ該複
数の光電変換素子を互いに電気的に直列接続して同一絶
縁基板上に形成させたことを特徴とする光電変換装置作
製方法。
1. A step of forming a first transparent conductive film constituting a first electrode on a transparent insulating substrate, and cutting and separating the first conductive film into a plurality of segments using a K laser beam. Step 1 of forming an open groove, and forming a KP process on the conductive film and the groove.
a step of cutting and separating a non-single crystal conductive film having at least one t or PN junction into a plurality of segments using a laser beam to form a second open groove; ``The step of forming a second conductive film on the surface of the non-single crystal semiconductor and the first conductive film, and the step of forming the second conductive film, or the conductive film and the non-single crystal semiconductor below it with a laser. A plurality of photoelectric conversion elements are formed by cutting and separating with light to form a third open groove, and the plurality of photoelectric conversion elements are electrically connected in series to each other and formed on the same insulating substrate. A method for manufacturing a photoelectric conversion device, characterized in that:
JP57206807A 1982-11-24 1982-11-24 Manufacture of photoelectric conversion device Pending JPS5996778A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP57206807A JPS5996778A (en) 1982-11-24 1982-11-24 Manufacture of photoelectric conversion device
IN511/DEL/83A IN160665B (en) 1982-11-24 1983-07-27

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57206807A JPS5996778A (en) 1982-11-24 1982-11-24 Manufacture of photoelectric conversion device

Publications (1)

Publication Number Publication Date
JPS5996778A true JPS5996778A (en) 1984-06-04

Family

ID=16529411

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57206807A Pending JPS5996778A (en) 1982-11-24 1982-11-24 Manufacture of photoelectric conversion device

Country Status (2)

Country Link
JP (1) JPS5996778A (en)
IN (1) IN160665B (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6059785A (en) * 1983-09-12 1985-04-06 Semiconductor Energy Lab Co Ltd Photoelectric conversion device and manufacture thereof
JPS60100482A (en) * 1983-11-05 1985-06-04 Semiconductor Energy Lab Co Ltd Manufacture of photoelectric converting semicoductor device
JPS60111419A (en) * 1983-10-27 1985-06-17 ア−ルシ−エ− コ−ポレ−ション Method of coating amorphous semiconductor material layer from gas in positive column of glow discharge
JPS6174376A (en) * 1984-09-19 1986-04-16 Fuji Electric Co Ltd Thin-film photovoltaic element
JPS61116884A (en) * 1984-11-12 1986-06-04 Semiconductor Energy Lab Co Ltd Manufacture of photoelectric conversion semiconductor device
FR2577716A1 (en) * 1985-02-15 1986-08-22 Teijin Ltd INTEGRATED SOLAR BATTERIES AND METHOD FOR MANUFACTURING SAME
JPS63215082A (en) * 1987-03-04 1988-09-07 Hitachi Ltd Amorphous solar cell

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57176778A (en) * 1981-03-31 1982-10-30 Rca Corp Solar battery array

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57176778A (en) * 1981-03-31 1982-10-30 Rca Corp Solar battery array

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6059785A (en) * 1983-09-12 1985-04-06 Semiconductor Energy Lab Co Ltd Photoelectric conversion device and manufacture thereof
JPH0566754B2 (en) * 1983-09-12 1993-09-22 Handotai Energy Kenkyusho
JPS60111419A (en) * 1983-10-27 1985-06-17 ア−ルシ−エ− コ−ポレ−ション Method of coating amorphous semiconductor material layer from gas in positive column of glow discharge
JPH0533526B2 (en) * 1983-10-27 1993-05-19 Rca Corp
JPS60100482A (en) * 1983-11-05 1985-06-04 Semiconductor Energy Lab Co Ltd Manufacture of photoelectric converting semicoductor device
JPH0476227B2 (en) * 1983-11-05 1992-12-03 Handotai Energy Kenkyusho
JPS6174376A (en) * 1984-09-19 1986-04-16 Fuji Electric Co Ltd Thin-film photovoltaic element
JPH0531315B2 (en) * 1984-09-19 1993-05-12 Fuji Electric Co Ltd
JPS61116884A (en) * 1984-11-12 1986-06-04 Semiconductor Energy Lab Co Ltd Manufacture of photoelectric conversion semiconductor device
FR2577716A1 (en) * 1985-02-15 1986-08-22 Teijin Ltd INTEGRATED SOLAR BATTERIES AND METHOD FOR MANUFACTURING SAME
JPS63215082A (en) * 1987-03-04 1988-09-07 Hitachi Ltd Amorphous solar cell
JPH0583198B2 (en) * 1987-03-04 1993-11-25 Hitachi Ltd

Also Published As

Publication number Publication date
IN160665B (en) 1987-07-25

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