JPH0415631B2 - - Google Patents

Info

Publication number
JPH0415631B2
JPH0415631B2 JP57206809A JP20680982A JPH0415631B2 JP H0415631 B2 JPH0415631 B2 JP H0415631B2 JP 57206809 A JP57206809 A JP 57206809A JP 20680982 A JP20680982 A JP 20680982A JP H0415631 B2 JPH0415631 B2 JP H0415631B2
Authority
JP
Japan
Prior art keywords
electrode
photoelectric conversion
semiconductor
conversion element
mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57206809A
Other languages
Japanese (ja)
Other versions
JPS5996780A (en
Inventor
Shunpei Yamazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP57206809A priority Critical patent/JPS5996780A/en
Priority to US06/554,762 priority patent/US4529829A/en
Priority to US06/554,807 priority patent/US4527006A/en
Priority to US06/554,763 priority patent/US4593152A/en
Priority to GB08331396A priority patent/GB2133214B/en
Priority to EP83307191A priority patent/EP0111402B1/en
Priority to GB08331397A priority patent/GB2133215B/en
Priority to KR1019830005552A priority patent/KR900004824B1/en
Priority to GB08331398A priority patent/GB2133617B/en
Priority to AU21659/83A priority patent/AU554459B2/en
Priority to GB08331330A priority patent/GB2133213B/en
Priority to AU21658/83A priority patent/AU553135B2/en
Priority to DE83307191T priority patent/DE3382709T2/en
Priority to EP83307192A priority patent/EP0113959B1/en
Priority to DE8383307192T priority patent/DE3382695T2/en
Priority to KR1019830005594A priority patent/KR900004823B1/en
Priority to US06/555,317 priority patent/US4518815A/en
Publication of JPS5996780A publication Critical patent/JPS5996780A/en
Priority to US06/620,177 priority patent/US4710397A/en
Priority to US06/620,171 priority patent/US4670294A/en
Priority to US06/620,098 priority patent/US4586241A/en
Priority to US06/620,462 priority patent/US4528065A/en
Priority to US06/760,957 priority patent/US4593151A/en
Priority to US06/760,873 priority patent/US4638108A/en
Priority to US06/776,806 priority patent/US4631801A/en
Priority to US06/846,514 priority patent/US4686760A/en
Publication of JPH0415631B2 publication Critical patent/JPH0415631B2/ja
Granted legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/1446Devices controlled by radiation in a repetitive configuration
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14643Photodiode arrays; MOS imagers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/036Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes
    • H01L31/0392Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including thin films deposited on metallic or insulating substrates ; characterised by specific substrate materials or substrate features or by the presence of intermediate layers, e.g. barrier layers, on the substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/042PV modules or arrays of single PV cells
    • H01L31/0445PV modules or arrays of single PV cells including thin film solar cells, e.g. single thin film a-Si, CIS or CdTe solar cells
    • H01L31/046PV modules composed of a plurality of thin film solar cells deposited on the same substrate
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Sustainable Development (AREA)
  • Sustainable Energy (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Photovoltaic Devices (AREA)

Description

【発明の詳細な説明】 この発明は、PIN接合を少なくとも1つ有する
アモルフアス半導体を含む非単結晶半導体が透光
性絶縁基板上に設けられた光電変換素子(単に素
子ともいう)を複数個電気的に直列接続した、高
い電圧の発生が可能な光電変換装置およびその作
製方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention provides electrical conversion of a plurality of photoelectric conversion elements (also simply referred to as elements) in which a non-single crystal semiconductor including an amorphous semiconductor having at least one PIN junction is provided on a transparent insulating substrate. The present invention relates to a photoelectric conversion device that is connected in series and can generate a high voltage, and a method for manufacturing the same.

この発明は、複数の素子間の連結に必要な面積
を従来のマスク合わせ方式の1/10〜1/100にする
ために、レーザスクライブ方式を用いたことを特
徴としている。
The present invention is characterized in that a laser scribing method is used to reduce the area required for connecting multiple elements to 1/10 to 1/100 of the conventional mask alignment method.

この発明は、第1および第2の素子の電気的連
結を行う第2の開溝を、PIN接合を有する非単結
晶半導体とその下の第1の電極とを除去してしま
い、第1の素子の第1の電極の側面に第2の素子
の第2の電極を連結するものであり、その際、こ
の第2の開溝は第1の素子の第2の電極の内部に
わたらせて設けることにより、第1の素子、第2
の素子のそれぞれの第1の電極間の電気的アイソ
レイシヨンをより完全にすることを目的としてい
る。
In this invention, the second groove for electrically connecting the first and second elements is removed by removing the non-single crystal semiconductor having the PIN junction and the first electrode therebelow. A second electrode of a second element is connected to a side surface of a first electrode of the element, and in this case, the second groove is provided to extend inside the second electrode of the first element. By this, the first element, the second
The purpose of this invention is to achieve more complete electrical isolation between the respective first electrodes of the elements.

このため第1および第2の素子の第2の電極を
分離する開溝は、第1の素子の半導体上にわたつ
て設けることにより、製造上の歩留り向上の冗長
度を設けたことを特徴としている。
For this reason, the groove separating the second electrodes of the first and second elements is provided over the semiconductor of the first element, thereby providing redundancy to improve manufacturing yield. There is.

この発明は、連結部での電気的接合を第1の素
子の第1の電極を構成する透光性導電膜(CTF
という)の側面に第2の素子の第2の電極を延在
して側面に密接せしめて用いることにより、連結
部での必要面積を減少せしめたことを特徴として
いる。
In this invention, the electrical connection at the connecting portion is made using a transparent conductive film (CTF) that constitutes the first electrode of the first element.
The second electrode of the second element is extended to the side surface of the device and used in close contact with the side surface of the device, thereby reducing the area required at the connecting portion.

このため第1および第2の素子の半導体を分離
する開溝は、第1の素子の第1の電極位置上にわ
たつて設け、LSの走査の揺らぎによる製造上の
冗長度(余裕度)を与えることを特徴としてい
る。
For this reason, the groove that separates the semiconductors of the first and second elements is provided over the first electrode position of the first element to reduce manufacturing redundancy (margin) due to fluctuations in LS scanning. It is characterized by giving.

従来、マスク合わせ方式において、その連結部
は5〜1mmの巾を必要としていたが、これをその
1/10〜1/100の350〜30μm好ましくは200〜50μと
することにより、この連結部を10〜50段必要とす
るハイブリツド方式において、光電変換装置とし
て用いられる全パネルの光起電力発生用の面積
(有効面積または実効面積という)が、従来の75
〜50%より97〜90%にまで高められ、実効変換効
率を10〜20%も実質的に向上せしめたことを特徴
とする。
Conventionally, in the mask alignment method, the connecting portion required a width of 5 to 1 mm, but by making this width 1/10 to 1/100 of that, 350 to 30 μm, preferably 200 to 50 μm, this connecting portion can be made wider. In a hybrid system that requires 10 to 50 stages, the area for photovoltaic generation (referred to as effective area or effective area) of all panels used as photoelectric conversion devices is 75
It is characterized by increasing the effective conversion efficiency from ~50% to 97~90%, substantially improving the effective conversion efficiency by 10~20%.

この発明ではレーザビームスクライブ方式を用
いることにより、合わせマークを基準としてこの
スクライブされるアドレスを予めコンピユータ
(マイクロ・コンピユータ)のメモリに記憶させ
ておくことにより、従来より知られたマスク合わ
せ方式で必要なマスクのずれ、そり、合わせ精度
に対する製造歩留りの低下等のすべての製造での
価格増、歩留り減の原因を一気に排除せしめたこ
とを特徴とする。
In this invention, by using a laser beam scribing method, the address to be scribed using the alignment mark as a reference is stored in advance in the memory of a computer (microcomputer), which is not necessary in the conventional mask alignment method. It is characterized by eliminating at once all causes of price increases and yield decreases in manufacturing, such as mask misalignment, warping, and decreases in manufacturing yields due to alignment accuracy.

従来、光電変換装置(以下単に装置という)即
ち同一基板上に複数の素子を配置し、それを集積
化またはハイブリツド化した装置はその実施例が
多く知られている。
Conventionally, many examples of photoelectric conversion devices (hereinafter simply referred to as devices), that is, devices in which a plurality of elements are arranged on the same substrate and are integrated or hybridized, are known.

例えば特開昭55−4994、特開昭55−124274さら
に本発明人の出願になる特願昭54−90097/
90098/90099(昭和54.7.16)が知られている。
For example, JP-A No. 55-4994, JP-A No. 55-124274, and Japanese Patent Application No. 54-90097 filed by the present inventor.
90098/90099 (July 16, 1972) is known.

例えば本発明人の出願になる特許願は、半導体
をSixC1-x−Siのヘテロ接合とし、単に他のアモ
ルフアス・シリコン半導体を用いる場合と異なら
せており、さらにこの半導体として、アモルフア
ス構造以外に微結晶構造を含む水素またはハロゲ
ン元素が添加されたPIN接合を少なくとも1つ有
する非単結晶半導体を集積化またはハイブリツド
化したものであるという特徴を有する。
For example, in the patent application filed by the present inventor, the semiconductor is a SixC 1-x -Si heterojunction, which is different from the case where other amorphous silicon semiconductors are used, and furthermore, this semiconductor has a structure other than an amorphous structure. It is characterized in that it is an integrated or hybridized non-single crystal semiconductor having at least one PIN junction to which hydrogen or halogen elements containing a microcrystalline structure are added.

しかしこれら従来の発明においては、第1図に
その縦断面図を示すか、すべてマスク合わせ方式
であり、合わせ精度が不十分でまた連結部に大き
な面積を必要としていた。
However, in these conventional inventions, as shown in FIG. 1, which is a vertical cross-sectional view, all of them employ a mask alignment method, which results in insufficient alignment accuracy and requires a large area for the connecting portion.

例えば金属マスクを用いた場合、直接選択的に
導電層または半導体層を作製する方式においては
この選択性を与えたマスクが被膜形成中に0.5〜
3mmずれてしまう場合がある。さらにこのマスク
上に被膜成分が形成されるため、マスクが汚染さ
れ、またマスクがそつて形成される被膜の周端部
が明瞭でなくなり、隣合つた電極間のクロストー
ク(リーク電流)の発生の要因となる等多くの欠
点を有するものであつた。
For example, in the case of using a metal mask, in a method for directly selectively producing a conductive layer or a semiconductor layer, the mask that provides this selectivity is used during film formation.
There may be a deviation of 3 mm. Furthermore, since a film component is formed on this mask, the mask becomes contaminated, and the mask is warped, making the peripheral edge of the film formed unclear, resulting in crosstalk (leakage current) between adjacent electrodes. It had many drawbacks, such as being a factor in

さらに従来公知のスクリーン印刷法等は、基板
上に全体的に形成された導体または半導体を独立
に選択的にマスクを用いてエツチング除去する方
法である。しかしかかる方法においては、スクリ
ーン印刷用のマスクの位置合わせの工程、レジス
トのコーテイング工程、ベーク固化工程、導体ま
たは半導体のエツチング工程、レジストの除去工
程等きわめて工程に時間がかかり、そのため製造
価格の上昇が免れ得なかつた。
Furthermore, conventionally known screen printing methods and the like are methods in which conductors or semiconductors formed entirely on a substrate are independently and selectively etched away using a mask. However, in this method, the process is extremely time consuming, including the process of aligning the mask for screen printing, the process of coating the resist, the process of baking and solidifying, the process of etching the conductor or semiconductor, and the process of removing the resist, which increases the manufacturing cost. could not be avoided.

しかし本発明の光電変換装置特に薄膜型の光電
変換装置にあつては、それぞれの薄膜層である電
極用導電層、または半導体層はともにそれぞれ
500Å〜1μmであり、レーザスクライブ方式を用
いることにより、まつたくマスク合わせを必要と
しないで作製することが可能となつた。
However, in the photoelectric conversion device of the present invention, particularly in the thin film type photoelectric conversion device, each of the thin film layers, the conductive layer for electrodes or the semiconductor layer, is
It has a thickness of 500 Å to 1 μm, and by using a laser scribing method, it has become possible to manufacture it without the need for mask alignment.

その結果、従来のマスク合わせ工程のかわりに
本発明においては、マスクをまつたく用いないた
めスクライブ工程というが、このスクライブ工程
がマイクロ・コンピユータを併用することにより
きわめて簡単かつ高精度であり、装置の製造コス
トの低下をもたらした。そのため500円/Wの製
造も可能となり、その製造規模の拡大により100
〜200円/Wも可能となるというきわめて画期的
な光電変換装置を提供することによる。
As a result, in place of the conventional mask alignment process, in the present invention, the scribing process is called a scribing process because no masks are used, but this scribing process is extremely simple and highly accurate due to the combined use of a microcomputer. This resulted in a reduction in manufacturing costs. Therefore, it is possible to manufacture products for 500 yen/W, and by expanding the manufacturing scale, 100 yen/W is possible.
By providing an extremely innovative photoelectric conversion device that can be sold for up to 200 yen/W.

さらに本発明においてはこのレーザスクライブ
工程を用いるに加えて、そのスクライブラインの
合わせ精度に冗長(余裕)度をもたせたことが重
要である。そのため隣合つた素子間の第1の電極
(下側)と他の素子の第2の電極(上側電極)と
が第2の電極より延在したリードにより第1の電
極とその側面において電気的に連結させることに
より、スクライブラインの開溝の位置に冗長度を
持たせることができた。
Furthermore, in the present invention, in addition to using this laser scribing process, it is important to provide a degree of redundancy (margin) in the alignment accuracy of the scribe lines. Therefore, the first electrode (lower side) between adjacent elements and the second electrode (upper electrode) of the other element are electrically connected to the first electrode and its side surface by the lead extending from the second electrode. By connecting it to the scribe line, it was possible to provide redundancy in the position of the open groove of the scribe line.

以下に図面に従つて従来例および本発明の構造
を記す。
A conventional example and the structure of the present invention will be described below according to the drawings.

第1図は従来より知られたマスク合わせ方式の
光電変換装置の縦断面図である。
FIG. 1 is a longitudinal sectional view of a conventionally known photoelectric conversion device using a mask alignment method.

図面において透光性基板(例えばガイス板)1
上に第1の電極を構成する透光性導電膜(CTF
と略記する)を第1のマスク合わせ工程により選
択的に形成させる。さらに半導体層3を第2のマ
スク合わせ工程により同様に選択的に形成させ
る。さらに第3のマスク合わせ工程により第2の
電極4が設けられている。
In the drawing, a translucent substrate (e.g. Geiss plate) 1
A transparent conductive film (CTF) constituting the first electrode is placed on top.
) are selectively formed by the first mask alignment step. Further, the semiconductor layer 3 is similarly selectively formed by a second mask alignment step. Further, a second electrode 4 is provided by a third mask alignment step.

第1図において素子11,31との間に連結部
12を有し、連結部においてはCTFの一方の側
面16を半導体層3が覆い、他方のCTFの表面
14を半導体層3が覆わないようにするため、
CTFの間13は1〜5mm例えば3mmの〓間を必
要とする。さらに第1の電極37と第2の電極3
8の第2の電極がマスクのぼけで発生するひろが
りをも含めてシヨートしてはいけないため、1〜
5mm例えば3mmの間〓6を必要とする。これら3
つのマスクには全くのセルフアライン性がないた
め、連結部12においては1〜8mm代表的には4
mmを必要としてしまう。さらにこれを1mm以下を
するとそのマスク合わせ精度はきわめて厳密であ
り、歩留りが極端に添加してしまう。この連結部
12の間〓を5mm以上とすると、例えば20cm×60
cmに巾15mm(20cm×15mm)の素子、端子5mmを作
製せんとすると、20段の直接接続ができるのみで
ある。またこの連結部の間〓を3mmとしても33段
であり、連結部では全部で延べ10cm(200cm2の面
積)の損失になり、その結果有効面積は周辺部を
考慮すると75%にとどまつてしまつていた。
In FIG. 1, there is a connecting part 12 between the elements 11 and 31, and in the connecting part, the semiconductor layer 3 covers one side surface 16 of the CTF, and the semiconductor layer 3 does not cover the surface 14 of the other CTF. In order to
During CTF 13, a distance of 1 to 5 mm, for example 3 mm, is required. Furthermore, the first electrode 37 and the second electrode 3
Since the second electrode of No. 8 must not be shot, including the spread caused by the blurring of the mask,
For example, 6 is required between 5mm and 3mm. These 3
Since two masks do not have any self-alignment properties, the connecting portion 12 is typically 1 to 8 mm.
mm is required. Furthermore, if this is less than 1 mm, the mask alignment accuracy will be extremely strict, and the yield will be extremely reduced. If the distance between the connecting parts 12 is 5 mm or more, for example, 20 cm x 60
If we try to fabricate an element with a width of 15 mm (20 cm x 15 mm) and a terminal of 5 mm in cm, we can only connect 20 stages directly. In addition, even if the distance between the connecting parts is 3 mm, there are 33 stages, which results in a total loss of 10 cm (area of 200 cm 2 ) at the connecting parts, and as a result, the effective area remains at 75% when the peripheral area is taken into account. It was on.

本発明はかかる工程の複雑さを排除し、有効面
積が86〜97%例えば92%にまで高めることができ
るというきわめて画期的な光電変換装置を提供す
ることにある。
The object of the present invention is to provide an extremely innovative photoelectric conversion device that eliminates the complexity of such a process and can increase the effective area by 86 to 97%, for example, to 92%.

また、第2の電極4の間〓6または半導体3の
間〓(7と6の一部)を形成する際に、マスクと
接する面が平坦ではなくパターンのために凹凸が
存在し、より一層マスクのぼけがひろがつてしま
い連結部の面積が広くなつてしまつた。
In addition, when forming the area between the second electrodes 4 (6) or between the semiconductors 3 (part of 7 and 6), the surface in contact with the mask is not flat but has unevenness due to the pattern, which makes it even worse. The blur of the mask became wider and the area of the connecting part became wider.

以下に図面に従つてその実施例の詳細を示す。 Details of the embodiment will be shown below with reference to the drawings.

第2図は本発明の製造工程を示す縦断面図であ
る。
FIG. 2 is a longitudinal sectional view showing the manufacturing process of the present invention.

図面において絶縁表面を有する基板例えば透光
性基板1即ちガラス板(例えば厚さ1.2mm、長さ
(図面では左右方向)60cm、巾20cm)を用いた。
さらにこの上面に全面にわたつて透光性導電膜例
えばITO(約1500Å))+SnO2(200〜400Å)また
はハロゲン元素が添加された酸化スズを主成分と
する透光性導電膜(1500〜2000Å)を真空蒸着
法、LP CVD法またはプラズマCVD法またはス
プレー法により形成させた。この後この基板の下
側または上側より、YAGレーザ加工機(日本レ
ーザ製)により出力5〜8W出力を加え、スポツ
ト径30〜70μmφ代表的には50μmφをマイク
ロ・コンピユータを制御して照射し、その走査に
よりスクライブライン用開溝13を形成させ、各
素子間に第1の電極2を作製した。
In the drawing, a substrate having an insulating surface, such as a transparent substrate 1, ie, a glass plate (for example, thickness 1.2 mm, length (in the left-right direction in the drawing) 60 cm, and width 20 cm) was used.
Furthermore, a transparent conductive film such as ITO (approximately 1500 Å) + SnO 2 (200 to 400 Å) or a transparent conductive film whose main component is tin oxide doped with a halogen element (1500 to 2000 Å) is applied over the entire upper surface. ) was formed by vacuum evaporation, LP CVD, plasma CVD, or spraying. After that, a YAG laser processing machine (manufactured by Nippon Laser) applies an output of 5 to 8 W to the bottom or top of this substrate, and irradiates a spot diameter of 30 to 70 μm (typically 50 μm) by controlling a microcomputer. By this scanning, an open groove 13 for a scribe line was formed, and a first electrode 2 was produced between each element.

スクライビングにより形成された開溝13は巾
約50μm長さ20cm深さは第1の電極それぞれを完
全に切断分離した。このため図面において明らか
なごとく、基板1の一部を抉る(凹部を形成す
る)こともあつた。かくして第1の素子31およ
び第2の素子11を構成する巾は10〜20mmとし
た。
The open grooves 13 formed by scribing were approximately 50 μm wide, 20 cm long, and 20 cm deep, completely cutting and separating each of the first electrodes. For this reason, as is clear from the drawings, a portion of the substrate 1 was sometimes gouged out (a recess was formed). Thus, the width of the first element 31 and the second element 11 was set to 10 to 20 mm.

以上のレーザスクライブ方式により、第1の電
極を構成するCTF2を複数の矩形の領域(それ
ぞれがそれぞれの素子の第1電極となる)に切断
分離して開溝を形成した。この後この上面にプラ
ズマCVD法またはLP CVD法によりPIN接合を
有する非単結晶半導体層3を0.2〜1.0μm代表的
には0.4〜0.5μmの厚さに形成させた。その代表
例はP型半導体(SixC1-xX=0.850〜150Å)−I
型アモルフアスまたはセミアモルフアスのシリコ
ン半導体(0.4〜0.5μm)−N型の微結晶(100〜
200Å)を有する半導体よりなる1つのPIN接合
を有する非単結晶半導体、またはP型半導体
(SixC1-x)−I型、N型、P型Si半導体−I型
SixGe1-x半導体−N型Si半導体よりなる2つの
PIN接合と1つのPN接合を有するタンデム型の
PINPIN………PIN接合の半導体3である。
Using the above laser scribing method, the CTF 2 constituting the first electrode was cut and separated into a plurality of rectangular regions (each serving as the first electrode of each element) to form open grooves. Thereafter, a non-single crystal semiconductor layer 3 having a PIN junction was formed on the upper surface by plasma CVD or LP CVD to a thickness of 0.2 to 1.0 μm, typically 0.4 to 0.5 μm. A typical example is P-type semiconductor (SixC 1-x X=0.850~150Å)-I
Type amorphous or semi-amorphous silicon semiconductor (0.4~0.5μm) - N type microcrystal (100~
200 Å), or P-type semiconductor (SixC 1-x ) - I-type, N-type, P-type Si semiconductor - I-type
SixGe 1-x semiconductor - two types of N-type Si semiconductor
Tandem type with PIN junction and one PN junction
PINPIN: PIN junction semiconductor 3.

かかる非単結晶半導体3を全面にわたつて均一
の膜厚で形成させた。さらに第2図Bに示される
ごとく、第1の開溝13の左方向側に第2の開溝
18を50μmの巾に100〜500μの距離をわたらせ
て第2のレーザスクライブ工程により形成させ
た。このレーザはガラス1の下方向またはこの基
板の上方のいずれからも行つてよい。
The non-single crystal semiconductor 3 was formed to have a uniform thickness over the entire surface. Furthermore, as shown in FIG. 2B, a second open groove 18 was formed on the left side of the first open groove 13 with a width of 50 μm and a distance of 100 to 500 μm by a second laser scribing process. . The laser may be applied either from below the glass 1 or from above the substrate.

かくして第2の開溝18は第1の電極の側面
8,9を露出させた。この第2の開溝により形成
された第1の電極の右側の側面9の存在は第1の
電極37の側面16より左側の第1の素子の第1
の電極位置上にわたつて設けられていることが特
徴である。そして第2図Bに示されるごとく、第
1の電極31の内部に入つてしまうことにより、
第1の電極の側面を8,9と露出せしめている。
かくすることにより第1の素子の第1の電極37
の一部が第2の開溝の右側に残存している。かか
る残存領域がない場合、レーザ光の高熱(〜2000
℃)によりCTF2よりもはるかに加工されやす
いため、第1の開溝13に充填された半導体が吹
き飛んでしまう。そのため第1および第2の素子
の第1の電極間のアイソレイシヨンが不可能にな
る。このことより第2図Bに示すごとく、第2の
開溝が第1の電極の内部に入つて設けられている
ことはきわめて重要である。この9の部分に残存
するCTFは50〜500μmの巾を有せしめた。
The second open groove 18 thus exposed the side surfaces 8, 9 of the first electrode. The presence of the right side surface 9 of the first electrode formed by the second groove causes the first electrode of the first element on the left side of the side surface 16 of the first electrode 37 to
It is characterized by being provided over the electrode positions. Then, as shown in FIG. 2B, by entering the inside of the first electrode 31,
The side surfaces 8 and 9 of the first electrode are exposed.
By doing so, the first electrode 37 of the first element
A part of it remains on the right side of the second open groove. If there is no such residual area, the high heat of the laser light (~2000
CTF2 is much easier to process than the CTF2, so the semiconductor filled in the first groove 13 is blown away. Therefore, isolation between the first electrodes of the first and second elements becomes impossible. For this reason, it is extremely important that the second groove is provided inside the first electrode, as shown in FIG. 2B. The CTF remaining in this portion 9 had a width of 50 to 500 μm.

さらに本発明は従来例に示されるごとく、第1
の電極の表面14(第1図参照)を露呈させるも
のではなく、レーザ光が5〜10Wで多少強すぎて
このCTF37の深さ方向のすべてを除去してし
まい、その結果側面8に第2図Cで第2の電極3
8を密接させても実用上何等問題はない。即ちレ
ーザ光の出力パルスの強さに余裕を与えることが
できることが本発明の工業的応用の際きわせて重
要である。
Furthermore, as shown in the conventional example, the present invention
It does not expose the surface 14 of the electrode (see Figure 1), but the laser beam is a little too strong at 5 to 10 W and removes the entire CTF 37 in the depth direction, resulting in a second layer on the side surface 8. Second electrode 3 in figure C
There is no practical problem even if 8 are placed closely together. That is, it is extremely important for the industrial application of the present invention that a margin can be given to the intensity of the output pulse of the laser beam.

第2図において、さらにこの上面に第2図Cに
示されるごとく、裏面の第2の電極4を形成し、
さらに第3のレーザスクライブ法の切断分離用の
第3の開溝20を設けた。
In FIG. 2, a second electrode 4 on the back surface is further formed on this top surface as shown in FIG. 2C,
Furthermore, a third groove 20 for cutting and separation in the third laser scribing method was provided.

この第2の電極4は透光性導電膜を700〜1400
Åの厚さにITO(酸化インジユームスズ)により
形成し、さらにその上面に反射性金属の銀を300
〜3000Åの厚さに形成した。さらにその上面にア
ルミニユームまたはアルミニユームとニツケルと
の2層膜を形成させた。例えばITOを1050Å、銀
を1000Å、さらにニツケルを1500Åの3層構造と
した。このITOと銀は裏面側での入射光10の反
射を促し、600〜800nmの長波長光を有効に光電
変換させるためのものである。さらにニツケルは
外部引き出し電極23との密着性を向上させるた
めのものである。これらは電子ビーム蒸着法また
はプラズマCVD法を用いて半導体層を劣化させ
ない300℃以下の温度で形成させた。
This second electrode 4 is made of a transparent conductive film with a thickness of 700 to 1400
It is made of ITO (indium tin oxide) to a thickness of 300 Å, and a reflective metal silver is coated on the top surface.
Formed to a thickness of ~3000 Å. Furthermore, a two-layer film of aluminum or aluminum and nickel was formed on the upper surface. For example, it has a three-layer structure of ITO of 1050 Å, silver of 1000 Å, and nickel of 1500 Å. The ITO and silver are used to promote reflection of incident light 10 on the back surface side and to effectively photoelectrically convert long wavelength light of 600 to 800 nm. Furthermore, nickel is used to improve adhesion with the external extraction electrode 23. These were formed using an electron beam evaporation method or a plasma CVD method at a temperature of 300° C. or lower, which does not deteriorate the semiconductor layer.

このITOは半導体3と裏面電極4との化学反応
による信頼性低下の防止、即ち信頼性の向上にも
役立つている。
This ITO is also useful for preventing a decrease in reliability due to a chemical reaction between the semiconductor 3 and the back electrode 4, that is, improving reliability.

かくのごとき裏面電極をレーザ光を上方より照
射して第2の電極を切断分離して第3の開溝20
(巾50μm)を形成した場合を示している。この
レーザ光は半導体特に上面に密接するNまたはP
型の半導体層をもえぐりだしI型半導体まで到達
せしめ40隣合つた第1の素子31第2の素子1
1間の開溝部での残存金属または導電性半導体に
よるクロストーク(リーク電流)の発生を防止し
た。
The back electrode is irradiated with a laser beam from above to cut and separate the second electrode to form a third open groove 20.
(width 50 μm) is shown. This laser light is applied to N or P which is in close contact with the semiconductor, especially the top surface.
40 Adjacent first element 31 Second element 1
The occurrence of crosstalk (leakage current) due to residual metal or conductive semiconductor in the open grooves between 1 and 2 was prevented.

特にこの半導体3がP型半導体層42、I型半
導体層43、N型半導体層44と例えば1つの
PIN接合を有し、このN型半導体層が微結晶また
は多結晶構造を有する。その電気伝導度が1〜
200(Ωcm)-1と高い伝導度を持つ場合、本発明の
N型半導体層をえぐり出し除去し、凹部に半導体
を設けて、リーク電流発生を防止することはきめ
て重要であつた。このえぐりだしはI型半導体層
を越え、第1の電極用のCTFにまで達成しなく
てもよい。本発明はレーザ光により開溝形成を第
2の電極のみでなく、その下側の0.2μm以上ある
I型半導体層の厚さ分の余裕を開溝部20の形成
の作業工程にもたせることが工業上重要である。
In particular, this semiconductor 3 has a P-type semiconductor layer 42, an I-type semiconductor layer 43, an N-type semiconductor layer 44, and, for example, one
It has a PIN junction, and this N-type semiconductor layer has a microcrystalline or polycrystalline structure. Its electrical conductivity is 1~
When the conductivity is as high as 200 (Ωcm) -1 , it is extremely important to scoop out and remove the N-type semiconductor layer of the present invention and provide a semiconductor in the recess to prevent leakage current generation. This gouging does not have to go beyond the I-type semiconductor layer and reach the CTF for the first electrode. According to the present invention, not only the second electrode can be used to form grooves using laser light, but also the work process for forming the groove portion 20 can have a margin corresponding to the thickness of the I-type semiconductor layer that is 0.2 μm or more below the second electrode. Industrially important.

かくして第2図Cに示されるごとく、複数の素
子31,11を連結部で直列接続する光電変換装
置を作ることができた。
In this way, as shown in FIG. 2C, a photoelectric conversion device in which a plurality of elements 31 and 11 were connected in series at a connecting portion could be manufactured.

第2図Dはさらに本発明を光電変換装置として
完成させんとしたものであり、即ちパツシベイシ
ヨン膜としてプラズマ気相法により窒化珪素膜2
1を500〜2000Åの厚さに形成させ、各素子間の
リーク電流の発生を防いだ。さらに外部引き出し
端子23を周辺部5にて設けた。これらのポリイ
ミド、ポリアミド、カプトンまたはエポキシ等の
有機樹脂22を充填した。
FIG. 2D shows an attempt to further complete the present invention as a photoelectric conversion device, that is, a silicon nitride film 2 is made by plasma vapor phase method as a passivation film.
1 was formed to a thickness of 500 to 2000 Å to prevent leakage current between each element. Further, an external lead terminal 23 is provided at the peripheral portion 5. An organic resin 22 such as polyimide, polyamide, Kapton or epoxy was filled.

かくして照射光10に対し、この実施例のごと
き基板(60cm×20cm)において各素子を巾14.35
mm、連結部の巾150μm、外部引き出し電極部の
巾10mm、周辺部4mmにより、有効面積(192mm×
14.35mm×40段、1102cm2即ち91.8%)を得ること
ができた。その結果、セグメントが10.6%の変換
効率を有する場合、パネルにて9.7%(AMI(100
mW/cm2)にて11.6Wの出力電力を有せしめるこ
とができた。
Thus, for irradiation light 10, each element has a width of 14.35 cm on a substrate (60 cm x 20 cm) as in this example.
The effective area (192 mm x
14.35 mm x 40 stages, 1102 cm 2 or 91.8%). As a result, if the segment has a conversion efficiency of 10.6%, the panel has a conversion efficiency of 9.7% (AMI (100
It was possible to have an output power of 11.6W at mW/cm 2 ).

これは従来のマスク合わせ方式で行つた場合の
55%(40段の場合)に比べてきわめて著しい効果
である。さらに金属マスクをまつたく用いないた
め、大面積パネルの製造工程において何等の工業
上の支障がなく、大電力発生用の大面積低価格大
量生産用にきわめて適している。
This is the same as when using the conventional mask matching method.
This is an extremely significant effect compared to 55% (for 40 stages). Furthermore, since no metal mask is used, there is no industrial problem in the manufacturing process of large-area panels, making it extremely suitable for large-area, low-cost mass production for generating large amounts of power.

本発明の構造をとれば、第1の開溝、第2の開
溝及び第3の開溝の形成時に下地表面な平坦であ
りレーザ加工が均一に行なえる為に連結部分の加
工寸法精度を向上させることができ、さらには連
結部分(非発電部分)の面積を小さくすることが
可能であつた。
With the structure of the present invention, when forming the first open groove, the second open groove, and the third open groove, the base surface is flat and laser processing can be performed uniformly, so that the processing dimensional accuracy of the connecting portion can be improved. Furthermore, it was possible to reduce the area of the connecting portion (non-power generating portion).

以上の実施例において明らかなように、本発明
により第2の電極を形成するためのレーザスクラ
イブ法での切断分離により、第2の電極下のNま
たはP型半導体層をも同時に除去したため、この
2つの電極間のリーク電流が10-3mA/cmより
10-9A/cmにまで下げることができた。このため
一般民生用においては、第2図Dの窒化珪素膜コ
ーテイング21を省略することも可能となつた。
As is clear from the above examples, the N or P type semiconductor layer under the second electrode was also removed at the same time by cutting and separating using the laser scribing method to form the second electrode according to the present invention. Leakage current between two electrodes is less than 10 -3 mA/cm
We were able to lower it to 10 -9 A/cm. Therefore, for general consumer use, it has become possible to omit the silicon nitride film coating 21 shown in FIG. 2D.

さらにまた連結部に関しては、第1の電極の側
面で隣の素子の第2の電極と連結を行うため、こ
の連結部(コンタクト部)の必要面積を従来方法
に比べて1/10以下に十分少なくさせ得るため、ひ
いてはパネルの有効面積の向上に役立つことがで
きた。
Furthermore, regarding the connection part, since the first electrode is connected to the second electrode of the adjacent element on the side surface, the area required for this connection part (contact part) is reduced to 1/10 or less compared to the conventional method. As a result, the effective area of the panel can be improved.

以上のYAGレーザのスポツト層をその出力3
〜5W(30μm)、5〜8W(50μm)で用いた場合で
あるが、さらにそのスポツト径を技術思想におい
て小さくすることにより、この連結部をより小さ
く、ひいては光電変換装置としての有効面積をよ
り向上させることができるという進歩性を有して
いる。
The spot layer of the YAG laser with more than 3 outputs
~5W (30μm) and 5~8W (50μm), but by further reducing the spot diameter based on the technical concept, this connection part can be made smaller and the effective area as a photoelectric conversion device can be further increased. It has an inventive step in that it can be improved.

第3図は電卓用等の大きなパネルより小さな光
電変換装置を同時に多量製造せんとした時の外部
引出し電極部を拡大して示したものである。
FIG. 3 is an enlarged view of the externally drawn electrode portion when photoelectric conversion devices smaller than a large panel for a calculator or the like are to be manufactured in large quantities at the same time.

第3図Aは第2図に対応しているが、外部引き
出し電極部5は導電性ゴム電極47に接触するパ
ツド49を有し、このパツド49は第2の電極
(上側電極)4と連結している。この時、電極4
7の加圧が強すぎてパツド49がその下の第1の
電極2と半導体3を突き抜けてシヨートしないよ
うに開溝13が設けられている。また外側部は開
溝18′,20′で切断分離されている。さらに第
3図Bは下側の第1の電極2に連結した他のパツ
ド48が第2の電極材料により18″にて連結し
て設けられている。さらにパツド48は導電性ゴ
ム電極46と接触しており、外部に電気的に連結
している。ここでも開溝18′,18″,20″,
20によりパツド48はまつたく他の光電変換
装置と電気的に分離されており、この装置間のガ
ラス切断を後工程により行うことにより、1つの
パネルで合わせ用マスクをまつたく用いることな
しに多数の光電変換装置を作ることができるとい
う特徴を有する。例えば20cm×60cmのパネルにて
6cm×1.5cmの光電変換装置(電卓用)を作らん
とすると、一度に130個の電卓用太陽電池を作る
ことができることがわかる。つまり光電変換装置
は有機樹脂モールド22で電極部5,45を除い
て覆われており、この後小電力用太陽電池を作る
場合はガラス切りで切断すればよい。またさらに
このパネル例えば40cm×20cmまたは60cm×20cmを
6ケまたは4ケ直列にアルミサツシ枠内に組み合
わせることによりパツケージされ、120cm×40cm
のNEDO規格の大電力用のパネルを設けること
が可能である。
FIG. 3A corresponds to FIG. 2, but the external lead-out electrode section 5 has a pad 49 that contacts the conductive rubber electrode 47, and this pad 49 is connected to the second electrode (upper electrode) 4. are doing. At this time, electrode 4
The groove 13 is provided to prevent the pad 49 from penetrating the first electrode 2 and the semiconductor 3 thereunder due to too strong pressure. Further, the outer portion is cut and separated by open grooves 18' and 20'. Further, in FIG. 3B, another pad 48 connected to the first electrode 2 on the lower side is connected at 18" by a second electrode material. Furthermore, the pad 48 is connected to the conductive rubber electrode 46. are in contact and are electrically connected to the outside. Again, the open grooves 18', 18'', 20'',
20, the pad 48 is electrically isolated from other photoelectric conversion devices, and by cutting the glass between these devices in a post-process, a large number of sheets can be formed in one panel without using a matching mask. It has the feature of being able to make photoelectric conversion devices of For example, if you try to make a 6cm x 1.5cm photoelectric conversion device (for a calculator) using a 20cm x 60cm panel, you will find that you can make 130 calculator solar cells at once. That is, the photoelectric conversion device is covered with the organic resin mold 22 except for the electrode parts 5 and 45, and if a small power solar cell is to be made after this, it can be cut using a glass cutter. Furthermore, this panel can be packaged by combining 6 or 4 pieces of 40cm x 20cm or 60cm x 20cm in series within an aluminum sash frame, making it 120cm x 40cm.
It is possible to install a high power panel that meets the NEDO standard.

またこのNEDO規格のパネルはシーフレツク
スにより他のガラス板を本発明の光電変換装置の
反射面側(図面では上側)にはりあわせて合わせ
ガラスとし、その間に光電変換装置を配置し、風
圧、雨等に対し機械強度の増加を図ることも有効
である。
In addition, this NEDO standard panel is made by laminating another glass plate with Seaflex to the reflective surface side (upper side in the drawing) of the photoelectric conversion device of the present invention, and the photoelectric conversion device is placed between them. It is also effective to increase mechanical strength.

第2図〜第3図において光入射は下側のガラス
板よりとした。しかし本発明はその光の入射側を
下側に限定するものではない。
In FIGS. 2 and 3, light was incident from the lower glass plate. However, the present invention does not limit the light incident side to the lower side.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の光電変換装置の縦断面図であ
る。第2図は本発明の光電変換装置の製造工程を
示す縦断面図である。第3図は本発明の他の光電
変換装置の外部引出し電極部分を拡大して示した
縦断面図である。
FIG. 1 is a longitudinal sectional view of a conventional photoelectric conversion device. FIG. 2 is a longitudinal sectional view showing the manufacturing process of the photoelectric conversion device of the present invention. FIG. 3 is a vertical sectional view showing an enlarged external lead electrode portion of another photoelectric conversion device of the present invention.

Claims (1)

【特許請求の範囲】[Claims] 1 絶縁基板表面を有する基板上に第1の電極
と、該電極上にPIN接合を少なくとも1つ有する
非単結晶半導体と、該半導体上に第2の電極とを
有する光電変換素子を複数個互いに電気的に直列
接続せしめるとともに、前記複数の光電変換素子
の一端の光電変換素子と他端の光電変換素子に連
結してそれぞれに外部引き出し電極部を設けた構
造に関し、前記一端の光電変換素子の第2の電極
より延在した外部引き出し電極部はその下に前記
非単結晶半導体と、その下の基板上に前記一端の
光電変換素子の第1の電極とは開溝により電気的
に分離された前記第1の電極と同一の導電材料が
設けられるとともに、前記他端の光電変換素子に
連結して設けられた外部引き出し電極部は、前記
他端の光電変換素子との間に設けられた開溝によ
り、前記他端の光電変換素子の第1の電極に連結
した第2の電極と同一材料の外部引き出し電極部
が設けられ、該第2の電極部下には前記半導体お
よび第1の電極と同一の導電材料が前記基板上に
設けられるとともに、該外部引き出し電極部は前
記他端に設けられた光電変換素子の第2の電極と
開溝により分離されたことを特徴とする光電変換
装置。
1. A plurality of photoelectric conversion elements each having a first electrode on a substrate having an insulating substrate surface, a non-single crystal semiconductor having at least one PIN junction on the electrode, and a second electrode on the semiconductor. Regarding the structure in which the plurality of photoelectric conversion elements are electrically connected in series, and the photoelectric conversion element at one end of the plurality of photoelectric conversion elements is connected to the photoelectric conversion element at the other end, and an external extraction electrode portion is provided for each, the photoelectric conversion element at one end of the plurality of photoelectric conversion elements is The external extraction electrode portion extending from the second electrode is electrically separated from the non-single-crystal semiconductor and the first electrode of the photoelectric conversion element at one end on the substrate below by an opening groove. The external lead electrode section is provided with the same conductive material as the first electrode, and is connected to the photoelectric conversion element at the other end, and is provided between the photoelectric conversion element at the other end. An external extraction electrode portion made of the same material as the second electrode connected to the first electrode of the photoelectric conversion element at the other end is provided by the open groove, and the semiconductor and the first electrode are provided under the second electrode. A photoelectric conversion device characterized in that the same conductive material is provided on the substrate, and the external lead electrode part is separated from the second electrode of the photoelectric conversion element provided at the other end by an open groove. .
JP57206809A 1982-11-24 1982-11-24 Photoelectric conversion device Granted JPS5996780A (en)

Priority Applications (25)

Application Number Priority Date Filing Date Title
JP57206809A JPS5996780A (en) 1982-11-24 1982-11-24 Photoelectric conversion device
US06/554,762 US4529829A (en) 1982-11-24 1983-11-23 Photoelectric conversion device
US06/554,807 US4527006A (en) 1982-11-24 1983-11-23 Photoelectric conversion device
US06/554,763 US4593152A (en) 1982-11-24 1983-11-23 Photoelectric conversion device
EP83307192A EP0113959B1 (en) 1982-11-24 1983-11-24 Photoelectric conversion device
KR1019830005594A KR900004823B1 (en) 1982-11-24 1983-11-24 Photo electronic conversion device and manufacturing method thereof
GB08331397A GB2133215B (en) 1982-11-24 1983-11-24 Photoelectric conversion device and its manufacturing method
KR1019830005552A KR900004824B1 (en) 1982-11-24 1983-11-24 Photo-electronic conversion device and manufacturing method thereof
GB08331398A GB2133617B (en) 1982-11-24 1983-11-24 Photoelectric conversion device and method of manufacture
AU21659/83A AU554459B2 (en) 1982-11-24 1983-11-24 Photoelectric conversion device
GB08331330A GB2133213B (en) 1982-11-24 1983-11-24 Photoelectric conversion device and method of manufacturing the same
AU21658/83A AU553135B2 (en) 1982-11-24 1983-11-24 Photoelectric conversion device
DE83307191T DE3382709T2 (en) 1982-11-24 1983-11-24 Photovoltaic converter.
GB08331396A GB2133214B (en) 1982-11-24 1983-11-24 Photoelectric conversion device and its manufacturing method
DE8383307192T DE3382695T2 (en) 1982-11-24 1983-11-24 PHOTOVOLTAIC CONVERTER.
EP83307191A EP0111402B1 (en) 1982-11-24 1983-11-24 Photoelectric conversion device
US06/555,317 US4518815A (en) 1982-11-24 1983-11-25 Photoelectric conversion device
US06/620,177 US4710397A (en) 1982-11-24 1984-06-13 Photoelectric conversion device and its manufacturing method
US06/620,171 US4670294A (en) 1982-11-24 1984-06-13 Photoelectric conversion device and its manufacturing method
US06/620,098 US4586241A (en) 1982-11-24 1984-06-13 Photoelectric conversion device manufacturing method
US06/620,462 US4528065A (en) 1982-11-24 1984-06-14 Photoelectric conversion device and its manufacturing method
US06/760,957 US4593151A (en) 1982-11-24 1985-07-31 Photoelectric conversion device
US06/760,873 US4638108A (en) 1982-11-24 1985-07-31 Photoelectric conversion device
US06/776,806 US4631801A (en) 1982-11-24 1985-09-17 Method of making photoelectric conversion device
US06/846,514 US4686760A (en) 1982-11-24 1986-03-31 Method of making photoelectric conversion device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57206809A JPS5996780A (en) 1982-11-24 1982-11-24 Photoelectric conversion device

Related Child Applications (2)

Application Number Title Priority Date Filing Date
JP58168556A Division JPS5996783A (en) 1983-09-12 1983-09-12 Photoelectric conversion device
JP62135544A Division JPS62295467A (en) 1987-05-29 1987-05-29 Photoelectric convertor

Publications (2)

Publication Number Publication Date
JPS5996780A JPS5996780A (en) 1984-06-04
JPH0415631B2 true JPH0415631B2 (en) 1992-03-18

Family

ID=16529442

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57206809A Granted JPS5996780A (en) 1982-11-24 1982-11-24 Photoelectric conversion device

Country Status (1)

Country Link
JP (1) JPS5996780A (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS603164A (en) * 1983-06-21 1985-01-09 Sanyo Electric Co Ltd Manufacture of photovoltaic device
JPS60100481A (en) * 1983-11-05 1985-06-04 Semiconductor Energy Lab Co Ltd Photoelectric converting semiconductor device
JPH0535363U (en) * 1991-07-04 1993-05-14 和則 浅場 File
JP4863823B2 (en) * 2006-09-12 2012-01-25 矢崎総業株式会社 Connector lock structure

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56152278A (en) * 1980-04-28 1981-11-25 Sanyo Electric Co Ltd Device for generating photo-electromotive force

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56152278A (en) * 1980-04-28 1981-11-25 Sanyo Electric Co Ltd Device for generating photo-electromotive force

Also Published As

Publication number Publication date
JPS5996780A (en) 1984-06-04

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