JPS6018973A - Photoelectric conversion semiconductor device - Google Patents

Photoelectric conversion semiconductor device

Info

Publication number
JPS6018973A
JPS6018973A JP58128270A JP12827083A JPS6018973A JP S6018973 A JPS6018973 A JP S6018973A JP 58128270 A JP58128270 A JP 58128270A JP 12827083 A JP12827083 A JP 12827083A JP S6018973 A JPS6018973 A JP S6018973A
Authority
JP
Japan
Prior art keywords
electrode
cell
photoelectric conversion
electrodes
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58128270A
Other languages
Japanese (ja)
Other versions
JPH0518273B2 (en
Inventor
Shunpei Yamazaki
舜平 山崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP58128270A priority Critical patent/JPS6018973A/en
Priority to US06/630,063 priority patent/US4594471A/en
Priority to DE8484304808T priority patent/DE3470819D1/en
Priority to GB08417904A priority patent/GB2146173B/en
Priority to KR1019840004120A priority patent/KR900005126B1/en
Priority to EP84304808A priority patent/EP0134669B1/en
Publication of JPS6018973A publication Critical patent/JPS6018973A/en
Priority to US06/720,291 priority patent/US4603470A/en
Priority to US08/005,170 priority patent/US5332680A/en
Priority to US08/013,209 priority patent/US5332450A/en
Publication of JPH0518273B2 publication Critical patent/JPH0518273B2/ja
Priority to US08/222,954 priority patent/US5500051A/en
Priority to US08/505,960 priority patent/US5567249A/en
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02Details
    • H01L31/0224Electrodes
    • H01L31/022408Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/1446Devices controlled by radiation in a repetitive configuration
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14665Imagers using a photoconductor layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy
    • Y02E10/547Monocrystalline silicon PV cells
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Photovoltaic Devices (AREA)

Abstract

PURPOSE:To enhance the apparent value of the titled device by a method wherein, when a photoelectric conversion cell is brought into compound form on the substrate having a photoelectric conversion cell on the insulated surface, the disconnected wire between the adjoining cells is formed at 100mum or below, and the electrodes located at the upper part and the lower part of the adjoining cells are joined at the aperture located inside the non-single crystal semiconductor layer. CONSTITUTION:ITO 3 is vapor-deposited on a glass plate 2, a groove 16 of 20-50mum in width is provided using a YAG laser, and cell regions 11 and 13 and external connection terminals 8 and 9 are formed. Amorphous SixC1-x 4 having uniform pin structure is deposited, a penetrated hole 15 of 10-70muphi is provided on a layer 4 and a lower electrode 3 using a laser light (ITO+Al) 5 for the upper electrode is coated, and at the coupled part, the lower electrode 3 and the upper electrode 5 of the cell 11 are ohmic-contacted 17 on the side face of the electrode 3 using the penetrated hole 15, and they are series-connected. Then, a microscopic groove 19 is provided at the point approximately 50mum on the cell 13 side using a YAG laser, an electrode metal 5 and a part of a semiconductor layer 4 are removed, and an oxidizing process is performed, and an insulating material is formed. Lastly, Si resin is coated, and the semiconductor device is completed. According to this constitution, the effective area of the cell can be increased, and the isolated groove between cells can not be seen from the side of glass, thereby enabling to increase the commercial value of the semiconductor device.

Description

【発明の詳細な説明】 この発明は、光電変換素子またはセル(以下単にセルと
いう)を絶縁表面を有する基板上に複合化するに関し、
隣合ったセル間の切断線(開溝)を肉眼では十分見分け
にくい100μ以下とし、装置全体としての視覚的商品
価値を向上させることを目的としている。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to combining photoelectric conversion elements or cells (hereinafter simply referred to as cells) on a substrate having an insulating surface.
The cutting line (opening groove) between adjacent cells is set to 100 μm or less, which is difficult to distinguish with the naked eye, and the purpose is to improve the visual commercial value of the device as a whole.

このため、本発明においては、活性領域に設けられたセ
ルにおける透光性基板上の第1の電極と、この電極上に
光照射により光起電力を発生する非単結晶半導体と、該
半導体上の第2の電極とのそれぞれを、概略同一形状、
概略同配置(セルフレジストレイジョン)構造とするこ
とにより、複合化の合わせ精度のズレによる製造上の歩
留り低下を避けるとともに、このセルフレジストレイジ
ョン(以下SGという)をレーザ光を用いたスクライブ
方式によるため、各セル間を100μ以下(0,1mm
以下)好ましくは10〜100μとすることができた。
Therefore, in the present invention, a first electrode on a transparent substrate in a cell provided in an active region, a non-single crystal semiconductor that generates a photovoltaic force by light irradiation on this electrode, and a and the second electrode of approximately the same shape,
By adopting a structure with approximately the same arrangement (self-registration region), we can avoid a decrease in manufacturing yield due to deviations in alignment accuracy during compounding, and also because this self-registration region (hereinafter referred to as SG) is created by a scribing method using a laser beam. , 100μ or less (0.1mm) between each cell
(hereinafter) preferably 10 to 100μ.

従来、非単結晶半導体即ちアモルファスシリコンを含む
非単結晶シリコンを主成分としたPIN接合、ヘテロ接
合またはPINPIN・・・PIN接合と複数のPIN
、PN接合を積層して設ける接合方式により光起電力を
光照射により発生させんとしていた。
Conventionally, PIN junctions, heterojunctions, or PINPINs...PIN junctions and multiple PINs have been made mainly of non-single crystal semiconductors, that is, non-single crystal silicon including amorphous silicon.
, an attempt was made to generate photovoltaic force by light irradiation using a bonding method in which PN junctions were stacked.

しかしかかる接合を有する半導体の上下の電極は直列接
続をするため、1つのセルの下側電極と隣のセルの上側
電極とを電気的に連結させなければならず、かつ各セル
間は互いに電気的にアイソレイトされていることを必要
な条件としていた。
However, since the upper and lower electrodes of a semiconductor having such a junction are connected in series, the lower electrode of one cell must be electrically connected to the upper electrode of the adjacent cell, and each cell is electrically connected to each other. The necessary condition was that the system be isolated.

第1図は従来構造の代表的な例を示している。FIG. 1 shows a typical example of a conventional structure.

第1図(A)は光電変換装置(30)を透光性基板(2
)を下側にした背面より見た平面図である。
FIG. 1(A) shows a photoelectric conversion device (30) connected to a light-transmitting substrate (2).
) is a plan view seen from the back with the side facing downward.

図面において光照射により光起電力を発生する活性領域
(14)と、各セル(1)、(1’)を連結する連結部
(18)を盲する非活性領域(15)とを有する。第1
図(A)のA−λ、B−B’の縦断面図を対応させて(
B )、(C)に示されていることより明らかなごとく
、従来例においては、活性領域において各セル(1)、
(1’)はガラス基板(2)上の第1の電極の透光性導
電膜(CTF )の(3)は各セル間で互いに分離され
ている。また半導体(4)は各セル間にて互いに連結さ
れている。また非活性領域において、セル(1)の上側
電極は、セル(1)の下側電極と連結部(12)で連結
し、これを繰り返し5つのセルを外部電極(8>、< 
9 )間にて直列接続をさせている。このセルの数、大
きさは設計仕様によって決められる。
In the drawing, it has an active region (14) that generates photovoltaic force upon irradiation with light, and an inactive region (15) that blinds the connecting portion (18) that connects each cell (1), (1'). 1st
The vertical cross-sectional views of A-λ and B-B' in Figure (A) are made to correspond (
As is clear from FIGS. B) and (C), in the conventional example, each cell (1),
(1') is a transparent conductive film (CTF) of the first electrode on the glass substrate (2), and (3) is separated between each cell. Further, the semiconductors (4) are connected to each other between each cell. Further, in the inactive region, the upper electrode of the cell (1) is connected to the lower electrode of the cell (1) by the connecting part (12), and this is repeated to connect the five cells to the external electrodes (8>, <
9) A series connection is made between the two. The number and size of these cells are determined by design specifications.

しかしこの従来構造は一見半導体(4)が1枚であるた
め製造歩留りが高いように見える。しかし実際には3種
類(第1の導電膜のパターニング用の第1のマスク、非
活性領域形成のための第2のマスク、第2の導電膜のパ
ターニング用の第3のマスク)のマスクを用いるが、そ
のマスクにおいて第1のマスクと第3のマスクとがセル
ファライン方式でないため、マスクずれを起こしやすい
However, at first glance, this conventional structure appears to have a high manufacturing yield because there is only one semiconductor (4). However, in reality, three types of masks are used (a first mask for patterning the first conductive film, a second mask for forming a non-active region, and a third mask for patterning the second conductive film). However, since the first mask and the third mask are not of the self-line type, mask misalignment is likely to occur.

このずれ(即ち金属マスクにおいては1〜3111mの
ずれはごく当然である)により、セルの有効面積が20
〜40%も実質的に減少してしまうことが判明した。さ
らにマスクを用いるため、第1図(B)の活性領域での
電極間の開溝であるアイソレイション領域は、0.2〜
1mm例えば0.5 mmを有するため、セルrjJを
10mmとする時、2mmずれるとするとセル中(15
)は8mmとなり、アイソレイション中(12)は2.
5nonとなってしまい、20%近くも有効面積が減少
してしまう。
Due to this deviation (that is, a deviation of 1 to 3111 m is quite natural for a metal mask), the effective area of the cell is 20
A substantial reduction of ~40% was found. Furthermore, since a mask is used, the isolation region, which is the opening between the electrodes in the active region of FIG.
1 mm, for example, 0.5 mm, so when cell rjJ is 10 mm, if there is a deviation of 2 mm, the inside of the cell (15
) is 8mm, and during isolation (12) is 2.
5non, and the effective area decreases by nearly 20%.

このため上下の電極の組合せをセルフレジストレイジョ
ン化することがその効率の向上のために強くめられてい
た。
For this reason, it has been strongly recommended that the combination of upper and lower electrodes be made into a self-registration region in order to improve its efficiency.

また第1図の従来例においては、基板に非活性領域(1
5)が設けられ、この非活性領域は基板全体における2
0〜30%も占めてしまう。このためプロセス上の効率
が低くなり、ひいては製造コストの低下を図ることがで
きない。
Furthermore, in the conventional example shown in FIG.
5) is provided, and this non-active region covers two parts of the entire substrate.
It accounts for 0-30%. For this reason, process efficiency decreases, and it is not possible to reduce manufacturing costs.

このため非活性領域が存在しない光電変換装置を作るこ
とがきわめて重要であった。
For this reason, it is extremely important to create a photoelectric conversion device that does not have non-active regions.

本発明はかかる目的を成就するためになされたものであ
る。即ち本発明においては、光照射面側からは複数の第
1の電極の分離用の開溝(lJ5〜70μ)が見られる
のみである。さらに第1図(A)における領域(15)
のごとき非活性領域かまったく存在せず、連結部が即ち
各セルのアイソレイション領域を構成せしめている。加
えてレーザ・スクライブ(以下単にLSという)を用い
るマスクレスプロセスであるため、第1の開溝をテレビ
モニターで積層して、その開溝を基準として所定の位置
に光学的にバターニングを行ういわゆるコンピュータ・
エイデツド・セルフレジストレイジョン方式を採用する
ことが可能になった。
The present invention has been made to achieve this object. That is, in the present invention, only the opening grooves (1J5 to 70μ) for separating the plurality of first electrodes can be seen from the light irradiation surface side. Further, area (15) in FIG. 1(A)
There are no inactive regions such as , and the connecting portions constitute the isolation regions of each cell. In addition, since it is a maskless process that uses a laser scribe (hereinafter simply referred to as LS), the first groove is laminated on a TV monitor, and optical patterning is performed at a predetermined position using the groove as a reference. So-called computer
It is now possible to use the aided self-registration method.

また第1のセルの第1の電極と、第2のセルの第2の電
極との連結部のコンタクトは、基板の半導体内部(この
第2図では中央部)に設け、透光性導電膜の実効的なシ
ート抵抗をきわめて小さくできる。この結果、連結部を
セルの外側に設けなかったことにより、著しくその有効
面積の効率の向上を図ることができた。
Further, a contact between the first electrode of the first cell and the second electrode of the second cell is provided inside the semiconductor of the substrate (in the center in FIG. 2), and is connected to a transparent conductive film. The effective sheet resistance can be made extremely small. As a result, since the connecting portion was not provided outside the cell, it was possible to significantly improve the efficiency of its effective area.

さらにこのコンタクトが隣合うセル間の半導体をすべて
切断する構造で開溝を作るのではなく、その開溝(10
〜60μφ)を1つまたは複数個不連続に設けることに
より、この開溝の存在がガラス面側より実質的に肉眼で
見い出し得す、商品的にスクライブラインが目障りにな
らないようにできたという他の特徴を有する。
Furthermore, instead of creating an open trench with a structure in which this contact cuts all the semiconductor between adjacent cells, the open trench (10
By discontinuously providing one or more grooves (up to 60μφ), the presence of these grooves can be seen with the naked eye from the glass surface side, and the scribe line does not become an eyesore on the product. It has the characteristics of

またコンタクトが開孔であるため、その孔の側周辺のす
べての側面が第1の電極と第2の電極との連結部を構成
させることができ、この部分での接触抵抗を1Ω以下に
下げることができた。
In addition, since the contact is an open hole, all the sides around the hole can form a connecting part between the first electrode and the second electrode, reducing the contact resistance in this part to 1Ω or less. I was able to do that.

本発明はかかる多くの特徴を有するものであって、以下
に図面に従ってその詳細を記す。
The present invention has many such features, and details thereof will be described below with reference to the drawings.

第2図は本発明の光電変換装置の製造工程および装置を
示すものである。
FIG. 2 shows the manufacturing process and apparatus of the photoelectric conversion device of the present invention.

図面において、基板は絶縁性表面を有する基板(例えば
ガラス)を用いた。この図面は4つのセルを直列接続せ
しめた場合である。即ち本発明の光電変換装置は活性領
域(14)を同一基板に10〜500ケ同時に有するよ
り大きい20cm X 60cmの基体を用いていた。
In the drawings, a substrate (eg, glass) having an insulating surface is used as the substrate. This drawing shows a case where four cells are connected in series. That is, the photoelectric conversion device of the present invention uses a larger substrate of 20 cm x 60 cm, which has 10 to 500 active regions (14) on the same substrate.

各セルでは、第1の導電膜を基体全面に形成した。さら
にこの導電膜を所定の形状にレーザ(ここでは1.06
μまたは0.53μの波長のYAG 、または0.48
8および0.563の波長のアルゴン・レーザ)スクラ
イブをマイクロコンピュータにより記憶され制御された
パターンに従ってスクライブを行って第1の開溝(16
)を形成した。そしてセル領域(11)、<13)およ
び外部接続用電極部(8>、< 9 ”)を形成させた
。このレーザ光の直径が一般的に30〜50μ(構造的
には3μも可能であるが、歩留りを考慮して焦点距離の
比較的長い30μを用いた)であるため、第1の開溝の
中は10〜70μ好ましくは20〜50μとさせた。
In each cell, a first conductive film was formed over the entire surface of the base. Furthermore, this conductive film is shaped into a predetermined shape using a laser (here, 1.06
YAG with a wavelength of μ or 0.53μ, or 0.48
The first open groove (16
) was formed. Then, a cell region (11), <13) and an electrode part for external connection (8>, <9'') were formed.The diameter of this laser beam is generally 30 to 50μ (3μ is also possible from a structural standpoint). However, considering the yield, a relatively long focal length of 30μ was used), so the inside of the first open groove was set to 10 to 70μ, preferably 20 to 50μ.

第2図(A)の平面図またA−A’における縦断面図を
示す。(A−1)において、第1の透光性導電膜(CT
Fという)による第1の電極(3)を基板(2)上に形
成させた。
A plan view of FIG. 2(A) and a longitudinal sectional view taken along line AA' are shown. In (A-1), the first transparent conductive film (CT
A first electrode (3) was formed on the substrate (2).

このCTPはITO(酸化スズを10%以下含有した酸
化インジューム)または酸化スズを単層または多層に積
層し形成している。一般には公知の電子ビーム蒸着法を
用いて500〜2500人の厚さに形成させた。
This CTP is formed by stacking ITO (indium oxide containing 10% or less of tin oxide) or tin oxide in a single layer or in multiple layers. Generally, it is formed to a thickness of 500 to 2,500 layers using a well-known electron beam evaporation method.

次に第2図(B)に示すごとく、光照射により光起電力
を発生する非単結晶半導体を、この電極(3人開溝(1
6)のすべての上面に均質の膜厚に形成させる。さらに
第2の開孔(15)をレーザ光により形成させた第2図
(B)の13−B、C−C’の縦断面図を(13−1)
、(B−2)に対応して示している。
Next, as shown in FIG.
6) A uniform film thickness is formed on all the upper surfaces. Furthermore, a vertical cross-sectional view of 13-B and CC' in FIG.
, (B-2).

この半導体(4)は例えば5ixC+−4(0< x 
< 1一般にはx =0.7〜0.8 )のP型を約1
00人の厚さに、さらに■型の水素またはハロゲン元素
が添加された珪素を主成分とする半導体を0.4〜0.
6μの厚さに、さらにN型の微結晶化した珪素またはN
型の5ixC+−x (0< x < I X 〜0.
9 )を主成分とする半導体のPIN接合構造とした。
This semiconductor (4) is, for example, 5ixC+-4 (0< x
< 1 In general, the P type with x = 0.7 to 0.8) is about 1
A semiconductor whose main component is silicon to which hydrogen or a halogen element is added is added to a thickness of 0.4 to 0.00 mm.
6μ thick and further N-type microcrystalline silicon or N
5ixC+-x (0< x < IX ~0.
9) as a main component of the semiconductor PIN junction structure.

もちろんこれをP (SixC1−< x =0.7〜
0.8 ) I (St)−N (μC3i ) −P
 (SixC,、x =0.7〜0.8 ) 1(Si
xGe+−q x =0.6〜0.8 ) −N (#
C5i )といヮたPINPIN構造のタンデム構造と
してもよい。
Of course, this is P (SixC1-< x =0.7~
0.8 ) I (St)-N (μC3i)-P
(SixC,, x =0.7~0.8) 1(Si
xGe+-qx=0.6~0.8)-N(#
It may also be a tandem structure of PINPIN structure such as C5i).

次に第2図(C)のパターンを形成させた。第2図(C
)のD−D’、E−E’に対応した縦断面図を(C−1
>、(C−2)に示している。この図面より明らかなご
とく、連結部(12)において、セル(13)の第1の
電極(3)とセル(11)の第2の電極(5)とがオー
ム接触を第2の開溝(15)を介してしている。特に連
結部(12)におけるコンタクI−(17)は、第2の
開孔(15)により作られた第1の電極の側面で成就さ
れ、いわゆるサイドコンタクト構造を有している。即ち
2つのセルはわずか10〜70μφの第2の開化の号イ
ドコンタクトで十分であり、この部分に第2の電極を構
成する材料を密接さセで電気的に直列接続をさせている
。 (C−1)の縦断面図より明らかなごとく、半導体
(4)上に第2の電極(5)が形成されているにすぎな
い。この第2の電極はITOを100〜1300人例え
ば1050人の厚さに設り、さらにアルミニュームを主
成分とする金属を500〜2000人の厚さに形成させ
た。勿論信頼性を重視しない場合はITOを除去しても
よい。またこの電極はITOのみでも十分であった。
Next, the pattern shown in FIG. 2(C) was formed. Figure 2 (C
) is a longitudinal cross-sectional view corresponding to D-D' and E-E' of (C-1
>, shown in (C-2). As is clear from this drawing, in the connecting portion (12), the first electrode (3) of the cell (13) and the second electrode (5) of the cell (11) make ohmic contact with each other through the second open groove ( 15). In particular, the contact I-(17) in the connection part (12) is achieved on the side surface of the first electrode created by the second opening (15) and has a so-called side contact structure. In other words, it is sufficient for the two cells to have a second open electrode contact with a diameter of only 10 to 70 μΦ, and the material constituting the second electrode is electrically connected in series to this portion in close contact. As is clear from the longitudinal cross-sectional view of (C-1), the second electrode (5) is merely formed on the semiconductor (4). This second electrode was formed by forming ITO to a thickness of 100 to 1,300, for example, 1,050, and further forming a metal whose main component was aluminum to a thickness of 500 to 2,000. Of course, if reliability is not important, ITO may be removed. Moreover, ITO alone was sufficient for this electrode.

裏面電極の反射性を利用して特性改良を図るには、前記
したITO÷AIまたはITO+Agが好ましかった。
In order to improve the characteristics by utilizing the reflectivity of the back electrode, the above-mentioned ITO÷AI or ITO+Ag was preferable.

この後、第2図(C)においてレーザスタライブ(19
)を行った。これはYAGレーザ(波長1.06μ、0
.53μ)を第2の導電膜を形成した後、テレビモニタ
ーにて第1の開溝をモニターしつつ、それより50〜2
00μ第2のセル側(13)にはいった位置にて開溝を
作った。レーザ光の平均出力0.3〜0.5すとし、ビ
ーム径30〜50μφビーム走査スピード1〜10m 
/分一般には3m/分として行った。
After this, the laser star live (19
) was carried out. This is a YAG laser (wavelength 1.06μ, 0
.. After forming the second conductive film of 53μ), while monitoring the first open groove on a TV monitor,
An open groove was made at a position on the 00μ second cell side (13). The average output of the laser beam is 0.3 to 0.5, the beam diameter is 30 to 50 μφ, and the beam scanning speed is 1 to 10 m.
/min Generally, the speed was set at 3 m/min.

そしてこの開溝(19)は第2の導電膜をその下の半導
体の少なくとも一部を除去して酸化して絶縁物として形
成した。
The trench (19) was formed by removing at least a portion of the underlying semiconductor of the second conductive film and oxidizing it to form an insulator.

この図面より明らかなごとく、絶縁表面を有する透゛光
性基板(2)上に第1の電極(3)、半導体(4)、第
2の電極(5)が中10〜100μ好ましくは20〜5
0μのスクライブライン(16)により概略同一形状に
同一配置を有して設けられている。
As is clear from this drawing, the first electrode (3), the semiconductor (4), and the second electrode (5) are arranged on a transparent substrate (2) having an insulating surface with a diameter of 10 to 100 μm, preferably 20 to 20 μm. 5
The scribe lines (16) having a diameter of 0 μ are provided in approximately the same shape and in the same arrangement.

第2図(C)において、これらの上面に有機樹脂(22
)例えばシリコーン、エポキシまたはポリイミドを1〜
20μの厚さにコーティングして完成させている。
In FIG. 2(C), organic resin (22
) For example, silicone, epoxy or polyimide from 1 to
It is completed by coating it to a thickness of 20μ.

その結果、この図面より明らかなごとく、この光電変換
装置は、例えば図面に示されているごと< 、1cm 
x5cmの光電変換装置を同じ大きさのガラス基板上に
1つ作るのではなく 、20cm X 20cmまたは
20cm X 60cmまたは40cm X 40cm
の大きなガラス基体に一度に多数の光電変換装置の基板
上に作ることが可能となった。そして最後にこれらを1
つずつの光電変換装置にガラス切りで分割すればよい。
As a result, as is clear from this drawing, this photoelectric conversion device is
Instead of making a single x5cm photoelectric conversion device on the same size glass substrate, we can create a 20cm x 20cm or 20cm x 60cm or 40cm x 40cm photoelectric conversion device.
It has become possible to fabricate multiple photoelectric conversion devices on a large glass substrate at once. And finally these 1
It can be divided into individual photoelectric conversion devices using a glass cutter.

このためには、従来より知られた活性領域と非活性領域
とを作るのではなく、すべて実質的に活性領域のみであ
り、また第1の電極、半導体および第2の電極を基体上
にきわめて単純に均質な被膜を形成することが可能であ
り、その中に連結部を有する本発明構造が効率(同一基
板で作り得る良品数量)できわめて優れている。
To this end, instead of creating an active region and a non-active region as conventionally known, all are essentially active regions and a first electrode, a semiconductor and a second electrode are formed on the substrate. It is possible to simply form a homogeneous film, and the structure of the present invention having a connecting portion therein is extremely superior in efficiency (number of good products that can be produced with the same substrate).

もちろん、大面積の同一基体上に多数(100〜1oo
o個)の光電変換装置基板を作製し、最後に分割するこ
とは第1図の従来例においても不可能ではない。しかし
かかる場合はマスクの基板の合わせ精度を要求したり、
またマスクの基板からの浮きが発生することがきわめて
嫌われるため、従来方法においては自ずからの限界があ
った。
Of course, a large number (100 to 100
Even in the conventional example shown in FIG. 1, it is not impossible to produce o photoelectric conversion device substrates and finally divide them. However, in such cases, precision of alignment of the mask substrate is required,
Furthermore, since it is extremely difficult for the mask to lift off from the substrate, conventional methods have their own limitations.

また第2図<C>において明らかなごとく、セルの有効
面積は連結部(12)の10〜300μ中のきわめてわ
ずかな部分を除いて他のすべてが有効であり、実効面積
は90%以上を得ることができ、従来例の80%に比べ
本発明構造は格段に優れたものであった。
Furthermore, as is clear from Fig. 2 <C>, the effective area of the cell is all but a very small part of the 10 to 300 μm of the connecting part (12), and the effective area is more than 90%. The structure of the present invention was significantly superior to 80% of the conventional example.

電卓用の第2図に示されるごとき光電変換装置のパター
ンにおいては、各開溝、開孔はY方向またはスポットの
みであり、複数のバターニングを必要としない。このた
め本来複雑なパターン作製および面積的なパターンを特
長とするマスク仕様のスクリーニング印刷法ではなく、
本発明のごとき溝または孔の従来法がむしろ有効面積向
上、レーザ光のスキ中ンスピード向上(生産性の向乍)
に優れている。
In the pattern of a photoelectric conversion device for a calculator as shown in FIG. 2, the grooves and holes are only in the Y direction or spots, and multiple patterning is not required. For this reason, instead of using mask-specific screening printing methods, which originally feature complex pattern creation and areal patterns,
The conventional method of forming grooves or holes as in the present invention actually improves the effective area and speed of laser light penetration (improving productivity).
Excellent.

これらのことを考慮すると、本発明は以下の大きな特長
を有することが判明した。
Taking these things into consideration, it has been found that the present invention has the following major features.

即ち、本発明は〔1〕大面積基体に同時に多数の光電変
換装置を作り、これを分割して各基板上に1つの光電変
換装置を作る方式を採用することが可能となった。この
ため、従来よりも1/3〜115の価格での製造が可能
である。〔2〕第1の開溝と第2の開孔、第3の開溝と
がコンピュータにより制御されたセルフレジストレイジ
ョン方式のため、セルの有効面積が大きく、かつその同
一ハツチで作られた各光電変換装置間のバラツキが少な
い〔3〕マスクレス工程であるため、製造歩留りが高い
〔4〕各セル間分離の第1の開溝のスクライブラインの
中が10〜50μときわめて小さく、かつ第2の開孔も
10〜50μφときわめて小さく、また第3の開溝はガ
ラス面側からはまったく見えない。その結果、肉眼によ
りバイブリソ1−化がされていることを確認され得す、
高付加商品価値を与えることができた。
That is, the present invention makes it possible to adopt a method [1] in which a large number of photoelectric conversion devices are simultaneously fabricated on a large-area substrate, and one photoelectric conversion device is fabricated on each substrate by dividing the photoelectric conversion devices. Therefore, it is possible to manufacture the device at a price of 1/3 to 115 times lower than that of the conventional method. [2] Since the first groove, second hole, and third groove are self-registered and controlled by a computer, the effective area of the cell is large, and each cell made of the same hatch is There is little variation between photoelectric conversion devices [3] The manufacturing yield is high because it is a maskless process [4] The inside of the scribe line of the first groove for isolation between each cell is extremely small, 10 to 50μ, and The second opening is also very small, 10 to 50 μφ, and the third opening is not visible at all from the glass surface side. As a result, it can be confirmed with the naked eye that vibrisolization has been carried out.
We were able to provide high added product value.

第2図において、第2の開孔(15)は1つのみを半導
体内部の特に中央付近に存在させた。しかしこの開孔ば
、複数ケ(2〜4ケ)を破線的にY方向に第1および第
3の開溝の間に作製しても、また櫛目形状に半導体(3
)の内部に第1の開溝(16)にそって形成させてもよ
い。
In FIG. 2, only one second opening (15) is present inside the semiconductor, particularly near the center. However, even if a plurality of openings (2 to 4 openings) are made between the first and third opening grooves in the Y direction along the broken line, the semiconductor (3
) may be formed along the first open groove (16).

また第1の開溝(16)、第2の開孔(15)、第3の
開溝の位置関係は、それらにより作られる連結部(12
)のl」が狭ければ狭い程好ましい。しかし実用的には
30〜100μを有し、セルの中(11)、(13)が
1cm (10,000μ)であるに比べると、1%し
か有効照射面積の減少をもたらさなかった。このためそ
れらの開溝、開孔を互いに50%まで重なりあわせるこ
とも可能である。
In addition, the positional relationship of the first opening groove (16), the second opening hole (15), and the third opening groove is determined by the connecting portion (12
) is preferably as narrow as possible. However, in practice, it has a diameter of 30 to 100μ, which results in a reduction in effective irradiation area of only 1% compared to the 1 cm (10,000μ) in cells (11) and (13). Therefore, it is possible to overlap the grooves and holes by up to 50%.

以上の説明は本発明の第2図のパターンには限定されな
い。セルの数、大きさはその設計仕様によって定められ
るものである。また半導体はプラズマCVD法、減圧C
VD法、光CVD法または光プラズマCVD法を用いた
The above description is not limited to the pattern of FIG. 2 of the present invention. The number and size of cells are determined by the design specifications. In addition, semiconductors are manufactured by plasma CVD method, reduced pressure C
A VD method, a photo-CVD method, or a photo-plasma CVD method was used.

非単結晶シリコンを主成分とするPIN接合、ヘテロ接
合、タンデム接合のみに限らず多くの構造への応用が可
能である。
Applications are possible not only to PIN junctions, heterojunctions, and tandem junctions that have non-single crystal silicon as the main component, but also to many structures.

本発明において、照射光は第2図(C)の(10)に示
すごとく下側より照射するものとした。しかしこの基板
を金属箔とし、この上面に耐熱性無機絶縁膜を形成した
可曲性の絶縁表面を有する基板を用いることも有効で゛
ある。即ら可曲性金属膜−絶縁膜一第1の電極−半導体
一第2の電極−半導体第2の電極構造を有せしめ、少な
くとも第2の電極を透光性とした。
In the present invention, the irradiation light is irradiated from below as shown in (10) of FIG. 2(C). However, it is also effective to use a substrate having a flexible insulating surface, which is made of metal foil and a heat-resistant inorganic insulating film is formed on the upper surface. That is, a flexible metal film-insulating film-first electrode-semiconductor-second electrode-semiconductor second electrode structure was provided, and at least the second electrode was made translucent.

かくする時上面よりの光照射方式を採用することが可能
になった。
In this case, it became possible to adopt a light irradiation method from the top.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の光電変換装置の縦断面図である。 第2図は本発明の光電変換装置の平面図および縦断面図
を製造工程に従って示したものである。 特許出願人 上二二 ュ
FIG. 1 is a longitudinal sectional view of a conventional photoelectric conversion device. FIG. 2 shows a plan view and a longitudinal sectional view of the photoelectric conversion device of the present invention according to the manufacturing process. Patent Applicant No. 22

Claims (1)

【特許請求の範囲】 ■、絶縁表面を有する基板上に配列された複数の第1の
電極、該第1の電極および該電極間の間隙上に設けられ
た光照射により光起電力を発生させる非単結晶半導体、
および前記第1の電極に対応して前記半導体上に設けら
れた複数の第2の電極とを有する複数の光電変換、素子
を備え、隣合う素子の第1および第2の電極は前記非単
結晶半導体内部に設けられた開孔により電気的に連結し
た連結部を有することを特徴とする光電変換半導体装置
。 2、特許請求の範囲第1項において、連結部は非単結晶
半導体に設けられた開孔と概略同一形状の開孔が第1の
電極に設りられ、該第1の電極の側部に第2の電極を構
成する材料が密接して設けられたことを特徴とする光電
変換半導体装置。
[Claims] (1) A plurality of first electrodes arranged on a substrate having an insulating surface, a photovoltaic force generated by light irradiation provided on the first electrodes and the gap between the electrodes. non-single crystal semiconductor,
and a plurality of photoelectric conversion elements having a plurality of second electrodes provided on the semiconductor corresponding to the first electrodes, the first and second electrodes of adjacent elements are connected to the non-single electrodes. A photoelectric conversion semiconductor device characterized by having a connecting portion electrically connected through an opening provided inside a crystalline semiconductor. 2. In claim 1, the connecting portion is provided with an opening in the first electrode having approximately the same shape as the opening provided in the non-single crystal semiconductor, and on a side of the first electrode. A photoelectric conversion semiconductor device characterized in that materials constituting the second electrode are provided in close contact with each other.
JP58128270A 1983-07-12 1983-07-13 Photoelectric conversion semiconductor device Granted JPS6018973A (en)

Priority Applications (11)

Application Number Priority Date Filing Date Title
JP58128270A JPS6018973A (en) 1983-07-13 1983-07-13 Photoelectric conversion semiconductor device
US06/630,063 US4594471A (en) 1983-07-13 1984-07-12 Photoelectric conversion device
EP84304808A EP0134669B1 (en) 1983-07-13 1984-07-13 Photoelectric conversion device and its manufacturing method
GB08417904A GB2146173B (en) 1983-07-13 1984-07-13 Photoelectric conversion device and manufacture thereof
KR1019840004120A KR900005126B1 (en) 1983-07-13 1984-07-13 Photo electron conversion device and manufacturing method thereof
DE8484304808T DE3470819D1 (en) 1983-07-13 1984-07-13 Photoelectric conversion device and its manufacturing method
US06/720,291 US4603470A (en) 1983-07-13 1985-04-05 Method of making plurality of series connected solar cells using multiple groove forming processes
US08/005,170 US5332680A (en) 1983-07-12 1993-01-15 Method of making photoelectric conversion device
US08/013,209 US5332450A (en) 1983-07-13 1993-02-01 Photoelectric conversion device
US08/222,954 US5500051A (en) 1983-07-13 1994-04-05 Photoelectric conversion device
US08/505,960 US5567249A (en) 1983-07-13 1995-07-24 Photoelectric conversion device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58128270A JPS6018973A (en) 1983-07-13 1983-07-13 Photoelectric conversion semiconductor device

Publications (2)

Publication Number Publication Date
JPS6018973A true JPS6018973A (en) 1985-01-31
JPH0518273B2 JPH0518273B2 (en) 1993-03-11

Family

ID=14980681

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58128270A Granted JPS6018973A (en) 1983-07-12 1983-07-13 Photoelectric conversion semiconductor device

Country Status (1)

Country Link
JP (1) JPS6018973A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60100481A (en) * 1983-11-05 1985-06-04 Semiconductor Energy Lab Co Ltd Photoelectric converting semiconductor device
JPS60117649A (en) * 1983-11-16 1985-06-25 ア−ルシ−エ− コ−ポレ−ション Photocell array
JPS60200577A (en) * 1984-03-26 1985-10-11 Semiconductor Energy Lab Co Ltd Photoelectric converting semiconductor device
US5421908A (en) * 1992-12-28 1995-06-06 Fuji Electric Co., Ltd. Thin-film solar cell and method for the manufacture thereof
JP2010012519A (en) * 2001-08-10 2010-01-21 First Solar Inc Method and apparatus for laser scribing glass sheet substrate coatings

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5753986A (en) * 1980-07-25 1982-03-31 Eastman Kodak Co
JPS57176778A (en) * 1981-03-31 1982-10-30 Rca Corp Solar battery array

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5753986A (en) * 1980-07-25 1982-03-31 Eastman Kodak Co
JPS57176778A (en) * 1981-03-31 1982-10-30 Rca Corp Solar battery array

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60100481A (en) * 1983-11-05 1985-06-04 Semiconductor Energy Lab Co Ltd Photoelectric converting semiconductor device
JPH0476226B2 (en) * 1983-11-05 1992-12-03 Handotai Energy Kenkyusho
JPS60117649A (en) * 1983-11-16 1985-06-25 ア−ルシ−エ− コ−ポレ−ション Photocell array
JPH0548634B2 (en) * 1983-11-16 1993-07-22 Rca Corp
JPS60200577A (en) * 1984-03-26 1985-10-11 Semiconductor Energy Lab Co Ltd Photoelectric converting semiconductor device
JPH065775B2 (en) * 1984-03-26 1994-01-19 株式会社半導体エネルギー研究所 Photoelectric conversion semiconductor device
US5421908A (en) * 1992-12-28 1995-06-06 Fuji Electric Co., Ltd. Thin-film solar cell and method for the manufacture thereof
JP2010012519A (en) * 2001-08-10 2010-01-21 First Solar Inc Method and apparatus for laser scribing glass sheet substrate coatings

Also Published As

Publication number Publication date
JPH0518273B2 (en) 1993-03-11

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