JPS59193075A - Manufacture of photoelectric conversion semiconductor device - Google Patents
Manufacture of photoelectric conversion semiconductor deviceInfo
- Publication number
- JPS59193075A JPS59193075A JP58067969A JP6796983A JPS59193075A JP S59193075 A JPS59193075 A JP S59193075A JP 58067969 A JP58067969 A JP 58067969A JP 6796983 A JP6796983 A JP 6796983A JP S59193075 A JPS59193075 A JP S59193075A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- semiconductor
- photoelectric conversion
- open groove
- groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
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- 229910001887 tin oxide Inorganic materials 0.000 description 3
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- 230000001590 oxidative effect Effects 0.000 description 2
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- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/042—PV modules or arrays of single PV cells
- H01L31/0445—PV modules or arrays of single PV cells including thin film solar cells, e.g. single thin film a-Si, CIS or CdTe solar cells
- H01L31/046—PV modules composed of a plurality of thin film solar cells deposited on the same substrate
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
Landscapes
- Engineering & Computer Science (AREA)
- Life Sciences & Earth Sciences (AREA)
- Sustainable Development (AREA)
- Sustainable Energy (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Photovoltaic Devices (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は、光照射により光起’4力を発生し・)る接
合を少なくとも1つ有するアモルファス半導体を含む非
単結晶半導体を透光性絶紅基板十に設けた光電変換素子
(単に素子ともいう)を複数個電気的に直列接続した、
高い電圧の発生の可能な光電変換装置の作製方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION The present invention provides a non-single-crystal semiconductor including an amorphous semiconductor having at least one junction that generates a photovoltaic force upon irradiation with light, on a translucent scarlet substrate. A device in which multiple photoelectric conversion elements (also simply called elements) are electrically connected in series.
The present invention relates to a method for manufacturing a photoelectric conversion device capable of generating high voltage.
この発明は、複数の素子間の連結に必要な面積を従来の
マスク合わせ方式の1 /10−1 /100にするた
め、マスクレス・プロセスであってレーザスクライブ方
式(以下LSという)を用いたことを特徴としている。This invention uses a laser scribing method (hereinafter referred to as LS), which is a maskless process, in order to reduce the area required for connecting multiple elements to 1/10-1/100 of the conventional mask alignment method. It is characterized by
本発明の装置におりる素子の配置、大きさ、形状は設計
仕様によって決められる。The arrangement, size, and shape of the elements in the device of the present invention are determined by design specifications.
しかし本発明の内容を節単にするため、以下の詳細な説
明においては、第1の素子の下側(基板側)の第1の電
極と、その右隣りに配置した第2の素子の第2の電極(
半導体上即ち基板から離れた側)とを電気的に直列接続
さゼた場合のパターンを基として記す。However, in order to simplify the content of the present invention, in the following detailed description, the first electrode on the lower side (substrate side) of the first element and the second electrode of the second element disposed on the right side thereof will be described. electrode (
The description is based on the pattern when electrically connected in series on the semiconductor (that is, on the side away from the substrate).
本発明はLSにより非単結晶半導体上の第2の電極を各
素子毎に第3の開溝を設けて分割する際、この電極のみ
ならずその下側に設けられた非m結晶半導体Jiをも除
去して第1の電極の少な(とも一部を露呈して設りるこ
とにより、LSにより第2の電極の金属部分が半導体中
に異常拡散して残存することによる半導体特にPINの
接合界面の接合特性の悪化と、ひいてはLSでの製造歩
留りの低下を防ごうとするものである。In the present invention, when dividing the second electrode on a non-single crystal semiconductor by providing a third trench for each element using LS, not only this electrode but also the non-m crystal semiconductor Ji provided below the second electrode is divided. By removing a small portion of the first electrode and exposing a small portion of the first electrode, the metal portion of the second electrode is abnormally diffused into the semiconductor due to LS and remains, thereby preventing the junction of semiconductors, especially PIN. This is intended to prevent deterioration of the bonding characteristics at the interface and, by extension, a decrease in the manufacturing yield of LS.
本発明は、第2の電極を非単結晶半導体に密接して金属
を設i−するのではなく、導電性酸化膜を設け、さらに
この股上に反射性金属を21−構造に形成せしめること
により、LSの際、光ダj1に。1、す& i7.l;
か半導体中に異常拡散をすることを防き、さ’) by
この一部の金属が拡散してもその半導体j冑を含んで瞬
時に除去してしまうことを特長としている。In the present invention, instead of forming the second electrode with metal in close contact with the non-single crystal semiconductor, a conductive oxide film is provided, and a reflective metal is further formed in a 21-structure on this crotch. , during LS, to light da j1. 1, Su & i7. l;
or prevent abnormal diffusion into semiconductors.
A feature of this method is that even if some of the metal diffuses, it is instantly removed, including the semiconductor particles.
本発明はさらに、この第2の電4Qaを構成さ一部るた
めの第3の開溝をLSにより作製するに際し この電極
間でのリーク電流をIOA/cm以十に−lしめること
を特長としている。The present invention is further characterized in that when the third groove for forming the second electrode 4Qa is fabricated by LS, the leakage current between the electrodes is reduced to less than IOA/cm. It is said that
本発明は、複数の素子を同一基板に集積化するに際し、
第2の電極の素子間の分割を容易にし、且つ分割3′る
領域(第3の開溝)との分割(アイソレイション)を完
全にするため、第20市4)’riをCOと間のjIさ
を規定して車に車・謂1、r−の電極としての特性向上
のみならず、複合集積化にスJしても生産性歩留り向上
のため最適化したごとをBj 徴としている。In the present invention, when integrating a plurality of elements on the same substrate,
In order to facilitate the division between the elements of the second electrode and to complete the division (isolation) with the divided region (third open groove), the The Bj characteristic is that it has been optimized not only to improve the characteristics as an electrode for cars, but also to improve productivity and yield even when integrated into composites. .
この発明はLS力式によるマスクレス工程で、ちって、
この製造工程においては前工程で形成された開溝を50
〜300倍に拡大してテレビシ31ン等に映し、このモ
ニターされた開溝をコンビ人−タ(マイクロコンピュー
タ)内にアドレスさ一部る。This invention is a maskless process using the LS force method.
In this manufacturing process, the open grooves formed in the previous process are
The image is enlarged up to 300 times and displayed on a television screen, etc., and the monitored opening groove is addressed into a microcomputer.
さらにこのインプットされた情報を基準としてそこより
のンフト量とメモリに記憶させた情報とを合わセで、こ
の−1−程で作られる開溝の位置を規定する。Furthermore, using this input information as a reference, the position of the open groove created by this -1- degree is defined by combining the amount of lift from there and the information stored in the memory.
そしてこの規定された位置にLS用のレーザー光例えば
波長1.09のYAGレーザ(焦点距離40mm、レー
ザ光径2ゾ)を照射させる。Then, a laser beam for LS, for example, a YAG laser having a wavelength of 1.09 mm (focal length 40 mm, laser beam diameter 2 zo) is irradiated onto this defined position.
さらにそれを05〜10m/分例えば5m/分の速さで
移動せしめ、前]二程と従属関係の開溝を作製せしめる
。Further, it is moved at a speed of 05 to 10 m/min, for example, 5 m/min, to create an open groove in a dependent relationship with the previous step.
かくのこと<LSをマイクロコンピュータと糾の合わゼ
ることにより、希望値に対して15 以ド実験的には
5以下の誤差しかない高精度で次工程の開溝を作製する
ことができる。By combining the LS with a microcomputer, it is possible to produce grooves in the next step with high precision, with an error of less than 15% compared to the desired value, but experimentally less than 5%.
即ち、本発明のLSは、実質的にコンピュータ制御され
たセルファライン方法を行うことができるという超高精
度方式であるという他の特長ををする。That is, the LS of the present invention has another feature that it is an ultra-high precision method that can perform a substantially computer-controlled self-line method.
このため従来より知られたマスク合ね上方式で必然的な
マスクのずれ、そり、合ね一部4’ii1.Dl tこ
スj−(−る製造歩留りの低下等の全ての製造7のI+
lli J各J1す、歩留り減の原因を一気に排除ゼし
ぬたことを′l′IIQとする。For this reason, the conventional mask fitting method inevitably causes mask misalignment, warping, and part of the fitting 4'ii1. Dl tkosj-(-) All production 7 I+ such as decrease in production yield, etc.
'l'IIQ indicates that the causes of yield reduction were not eliminated all at once.
しかしこれら従来の発明においては、第1図にその縦断
面図を示ずが、ずべてマスク合わ−U力式であり、合わ
せ精度が不十分てまた連結部に人ご、な面積を必要とし
ていた。However, in these conventional inventions, although the longitudinal cross-sectional view is not shown in FIG. there was.
例えば金属マスクを用いた場合、直接選択的に導電層ま
たは半導体層を作製する方式においてシ:Lこの選択性
を与えたマスクが被膜形成中に0.3〜2+nm 1’
れてしまう場合がある。For example, when a metal mask is used, in a method of directly selectively producing a conductive layer or a semiconductor layer, the mask giving this selectivity is
There are cases where it gets lost.
さらにこのマスクLに破j殴成分か形成さね、イ)ため
、マスクが汚染され、またマスクにそ−、で形成される
被膜の周端部が明瞭−(なくなり、VA合一、た電極間
のクロストーク(リーク電流)の発4F二の要因となる
等多くの欠点を自するものであった。In addition, the mask L is contaminated due to the formation of fracture components (a), and the peripheral edge of the coating formed on the mask is clear (disappeared, VA coalescence occurs, and the electrodes are exposed). It has many drawbacks, such as the generation of crosstalk (leakage current) between the two.
本発明は、従来のマスク合わせ工程のかわりGこマスク
を全く用いないマスクレス工程てあ−、で、きわめて簡
単かつ高精度であり、装置の製造−lストの低下をもた
らし、そのため500円/Wの製造も可能となり、その
製造規模の拡大により100〜200円/Wも可能に成
ったというきわめて画期的な光電変換装置を提供するこ
とにある。The present invention is a maskless process that does not use any masks in place of the conventional mask alignment process, and is extremely simple and highly accurate, resulting in a reduction in manufacturing costs of the equipment, and therefore costs less than 500 yen/ The purpose of the present invention is to provide an extremely innovative photoelectric conversion device that can now be manufactured using W, and by expanding its manufacturing scale, it has become possible to sell for 100 to 200 yen/W.
以Fに図面に従って従来例および本発明の構造を記す。Hereinafter, structures of a conventional example and the present invention will be described according to the drawings.
第1図は従来より知られたマスク合わせ方式の本発明の
光電変換装置の作製工程を示す縦断面図群である。FIG. 1 is a group of longitudinal sectional views showing the manufacturing process of a photoelectric conversion device of the present invention using a conventionally known mask alignment method.
図面において透光性基Mf!、(例えばガラス板)(1
)上に第1の電極を構成する透光性導電膜(CT Fと
略記する)を第1のマスク合ね七工程により選択的に形
成する。In the drawing, the transparent group Mf! , (e.g. glass plate) (1
) A transparent conductive film (abbreviated as CTF) constituting the first electrode is selectively formed on the first mask by seven steps.
さらに半導体1m(3)を第2のマスク合ね七り程によ
り同様に選択的に形成させる。Furthermore, semiconductor 1m(3) is selectively formed in the same manner by using a second mask.
さらに第3のマスク合わせ工程により第2の電極(4)
が設けられる。Furthermore, the second electrode (4) is formed by a third mask alignment process.
is provided.
第1図において、素子(11) (31)との間に連
)
結部(12)を有し、連結部においてはCTFの一方の
側面(16)を半導体層(3)が覆い、他方のCTFの
表面(14)を半導体IW(3)が覆わないよ−)Cご
するため、CTFの間(J3)は1〜5111111例
え+、UI 3 jnmの隙間を必要とする。In FIG. 1, a semiconductor layer (3) covers one side surface (16) of the CTF, and a semiconductor layer (3) covers one side surface (16) of the CTF at the connection portion. Since the semiconductor IW (3) does not cover the surface (14) of the CTF, a gap of 1 to 5111111 + UI 3 jnm is required between the CTFs (J3).
さらに第1の電極(37)と第2の電極(38)は(1
4)の表面で電気的に連結Jるが1、二の部うj:!:
(39)の第2の電極がマスク0月よりζ光41Jる1
広がりをも含めてノヨートしてはいりないため、1〜5
mm例えば3mmの間隙(6)を必要と′づる。Furthermore, the first electrode (37) and the second electrode (38) are (1
4) Electrically connected on the surface of the first and second parts:! :
The second electrode of (39) is ζ light 41Jru1 from the mask 0 month
1 to 5 because it is not necessary to spread out or spread.
For example, a gap (6) of 3 mm is required.
特にこの第2の電極(39)が第1の電447 (37
)とショートしないよう乙こするために、露−ij L
ノご半導体表面(28)での合わセ祐度は製造歩留り乙
こきわめ゛ζ重要であり、結果として連結rζ1iN2
)が広くなってしまった。In particular, this second electrode (39) is connected to the first electrode 447 (37
) to prevent short circuit with L.
The degree of bonding on the semiconductor surface (28) is extremely important for manufacturing yield, and as a result, the coupling rζ1iN2
) has become wider.
加えて第1の′8i極(37)と第2の71iiサス(
:1r))は半導体表面(28)を経てリークしゃJ’
< 、(Iru・Q・1)1の低下をもたらしてしま
っていた。In addition, the first '8i pole (37) and the second 71ii suspension (
:1r)) should leak through the semiconductor surface (28) J'
< , (Iru・Q・1) This resulted in a decrease of 1.
本発明は、製造プロセス上において(131等の新たな
工程を加えることなしに、第1の71i+’M (37
)と第2の電極(39)との間の半導体の表面をパノソ
ヘイション膜で覆い、かつその1−わたり7朶さ」(第
1の開溝の中央部と第3の開溝の中央部との距離として
この明細書において定義する)を20〜400とするこ
とにより、電極間リークを除去した構造とすることは、
製造歩留りの向にに優れたものであった。加えて特に本
発明においては、第1および第2の素子の第2の電極間
の距離を金属かマイブレイトしてしまうことを防くため
、第2の電極とその下の半導体層を完全に除いてしまう
ことにより第2の電極を構成する金属が残存して接合部
にリークが発生してしまうことを防くとともに、LSを
実行しやすくしたもので、この電極、開溝によりLS方
式によるマスクレスプロセスを完成せしめたものである
。The present invention provides the first 71i+'M (37
) and the second electrode (39), and cover the surface of the semiconductor between the first and second electrodes (39) with a panosolysis film, and By setting the distance (defined in this specification as the distance between
It was excellent in terms of manufacturing yield. In addition, particularly in the present invention, in order to prevent the distance between the second electrodes of the first and second elements from becoming metal or mibrate, the second electrode and the semiconductor layer thereunder are completely removed. This prevents the metal constituting the second electrode from remaining and causing leakage at the joint, and also makes it easier to carry out LS. This completes the response process.
本発明はかかる目的にそったものである。The present invention meets this objective.
又従来例において、この連結部の間隙を3mmとして例
えば20cm X 60cmに中15mm (20cm
X 15mm)の素子端部5mmを作製せんとすると
、33段接続となり、連結部では全部で延べ10cm
(200cm’の面積)の損失となり、その結果有効面
積は周辺部を考慮すると75%にとどまってしまった。In the conventional example, the gap between the connecting parts is set to 3 mm, for example, 15 mm (20 cm) in the 20 cm x 60 cm.
If you try to make a 5mm element end (X 15mm), there will be 33 stages of connections, and the total connection area will be 10cm.
(area of 200 cm'), and as a result, the effective area remained at 75% considering the peripheral area.
本発明はかかる工程の複層1ざをυ1]徐し2、自りノ
面積が86〜97%例えば92%にまで高めることがて
き加えてコ不りクをCOとし、さらにわたり深さをり。In the present invention, by reducing the thickness of the multilayer layer in such a process, the self-area can be increased to 86 to 97%, for example, 92%, and in addition, the thickness can be changed to CO, and the depth can be further increased.
えることにより、製造歩留りを従来のX、り60 %
t−rす87%にまで高め葛ことができるといつ画期的
な光電変換装置を提供することにある。By increasing the manufacturing yield by 60% compared to conventional
The objective is to provide an epoch-making photoelectric conversion device that can increase the T-R to 87%.
以下に図面に従って本発明の訂iI++を示J′。The revision iI++ of the present invention is shown below according to the drawings.
第2図は本発明の製造工程を示す縦断面図である。FIG. 2 is a longitudinal sectional view showing the manufacturing process of the present invention.
図面において透光性基板(1)例えばガラス板(例えば
厚さ0.6〜2.2mm例えば1,211m 、IMさ
〔図面では左右力向) 60cm、「1120cm)を
用いた。In the drawings, a translucent substrate (1), for example, a glass plate (for example, thickness 0.6 to 2.2 mm, e.g. 1,211 m, IM size (left and right direction in the drawings) 60 cm, "1120 cm") was used.
さらにこの上6面に全面にわたって込光性、v、!′1
.ii股\
例えばITO(M化インシュ−ム酸化スス混合物、即ち
酸化スズを酸化インジュ−ム中に1(川((jけ6添力
目したl央) (500−1500人) +5nOL
(200−40OA)または弗素等のハロゲン元素が添
加された1俊化スズを主成分とする透光性導電膜(15
00〜2000Å)を真空蒸着法、LPCv1〕法、プ
ラズマCν1)法、フメFCVD法またはスプレー法に
より形成さセた。In addition, the upper 6 surfaces are completely light-filled, v! '1
.. ii For example, ITO (M-formed insium soot oxide mixture, that is, tin oxide in indium oxide) (500-1500 people) +5nOL
(200-40OA) or a transparent conductive film (15
00 to 2000 Å) by vacuum evaporation method, LPCv1] method, plasma Cv1) method, FCVD method, or spray method.
この後ごの基板の下側または上側より、YAGレーザ加
工1a (ロ本レーザ製)により出力0.3〜3W(焦
点距離40mm)を加え、スボソl−径30〜70*’
代表的には397Aをマイクロコンピュータにより制f
all シて、出力よりレーザ光を照射して、その走査
によりスフライフライン用の第1の開溝(13)を形成
さセ、各素子間領域(31)、 (11)に第1の電極
(2)を作製した。After this, an output of 0.3 to 3 W (focal length 40 mm) is applied from the bottom or top of the substrate using YAG laser processing 1a (manufactured by Rohon Laser), and
Typically, the 397A is controlled by a microcomputer.
Then, a laser beam is irradiated from the output, and the first groove (13) for the short fly line is formed by scanning, and the first electrode is placed in each inter-element region (31), (11). (2) was produced.
LSにより形成された第1の開a(13)は、巾約30
A長さ20cm深さは第1の電極それぞれを完全に/
切断分離した。The first opening a (13) formed by LS has a width of about 30 mm.
A length of 20 cm and a depth of each of the first electrodes were completely cut/separated.
このため図面において明らかなごとく、基板(1)の一
部が300〜1300Aの深さでえぐられたく四部(6
0)を形成する)。For this reason, as is clear from the drawing, a portion of the substrate (1) is hollowed out at a depth of 300 to 1300A, and four parts (6
0)).
か(して第1の素子(31)および第2の素子(11ン
を構成する領域の巾は5〜40mm例えば1.5 m
mとした。The width of the area constituting the first element (31) and the second element (11) is 5 to 40 mm, for example 1.5 m.
It was set as m.
以上LS方式により、第1の電極を構成する透光性導電
膜(CTF)(2)を切断分離して第1の開溝を形成し
た。Using the LS method described above, the transparent conductive film (CTF) (2) constituting the first electrode was cut and separated to form the first groove.
この後この上面にプラズマcvr+?7;、フメトCV
I)法またはLPCVD法によりPNまたはP I N
lj妾合を自ずは0.57の厚さに形成さゼた。After this, plasma cvr+ on this top surface? 7;, Fumet CV
I) PN or PIN by method or LPCVD method
The lj joint was naturally formed to a thickness of 0.57.
その代表例!、t )) Q :144体(SixC1
−x x”0.Fl約1ooスン(42) −I型アモ
ルファスまたはセミアモルファスのシリコン半導体(約
0.ン) C4:l) −N型の微結晶く約200人
)をもする半導体(14) 、iりなる一つのPIN接
合を有する非単結晶半導体、11ミたは1)型半導体(
SixC) −1型、N型、■〕型Si″I′礎体−■
型5JxGeIJ導体−N型S1半導体よりなる2つの
PTNfp合と1つのI’ll接合を有するタンデノ・
型のPINFIN、、、、、IIIN接合の半導体(3
)である。A typical example! , t )) Q: 144 bodies (SixC1
-x ), a non-single crystal semiconductor with one PIN junction, 11 or 1) type semiconductor (
SixC) -1 type, N type, ■] type Si''I' foundation body -■
A tandenoid with two PTNfp junctions and one I'll junction made of type 5JxGeIJ conductor-N type S1 semiconductor.
Type PINFIN, , III junction semiconductor (3
).
かかる非単結晶半導体(3)を全面にわたって均一の膜
厚で形成させた。Such a non-single crystal semiconductor (3) was formed to have a uniform thickness over the entire surface.
さらに第2図(13)に示されるごとく、第1の開m
(13)の左方向側(第1の素子側)にわたって第2の
開溝(18)を第2のLS王程にj′り形成さゼた。Furthermore, as shown in FIG. 2 (13), the first opening m
A second open groove (18) was formed over the left side (first element side) of (13) with a length of about the length of the second LS.
この図面では第1および第2の開溝(13) (18
)り
の中心間を20〜30ノ例えば59ずらしている。In this drawing, the first and second open grooves (13) (18
) are shifted by 20 to 30 degrees, for example, by 59 degrees.
このレーザ光の照射はガラス(1)の下方向またはこの
基板の上方のいずれからも行ってよかった。The laser beam irradiation could be performed either from below the glass (1) or from above the substrate.
かくして第2の開溝(18)は第1の電極の側面(8)
、(9)を露出させた。The second open groove (18) thus forms a side surface (8) of the first electrode.
, (9) were exposed.
この第2の開溝の側面(9)は第1の素子の第1の電極
の側面(」6)より左(!11であればよく、10〜1
0少第1の電極例にンフI−させた。即も第1の素子の
第1の電極位置上にわたって設けられていることが特徴
である。The side surface (9) of this second open groove is to the left (!11, 10 to 1
The first electrode example was made to have a low temperature. It is characterized in that it is provided over the first electrode position of the first element.
そしてごの代表的な例として、第2図(B)に示される
ごとく、第1の電極(37)の内部(9)に入ってしま
ってもよい。As a typical example, the wire may enter the inside (9) of the first electrode (37) as shown in FIG. 2(B).
さらに本発明は従来例に示されるごとく、第1の@極の
表面(14) (第1図参照)のみを露呈させてもよ
いが、製造歩留りの向上のためにレーザ光が1〜3W例
えば2Wで多少強ずぎて、このCTF (37)の深さ
方向のすべてを1徐去してしまい、その結果、側面(8
)に第2図(C)で第2の電極(38)とのコネクタが
密接してもその1妾触低抗が特に大きくなる等のことが
なく、実用上前等問題はない。即ち、レーザ光の出力パ
ルスの強さまた開溝の深さのバラツキに対し、製造−1
の余裕を与えることができることが本発明のJ二朶的応
用の際きわめて重要である。Further, in the present invention, as shown in the conventional example, only the surface (14) of the first @ pole (see Fig. 1) may be exposed. 2W was a little too strong, and the entire depth direction of this CTF (37) was removed by 1, and as a result, the side surface (8
), even if the connector with the second electrode (38) is brought into close contact with the second electrode (38) in FIG. In other words, manufacturing-1
It is extremely important to be able to provide a margin of
第2図において、ざらにこの上面に第2図(0)に示さ
れるごとく、裏面の第2の?Ji極(4)よ、よびコネ
クタ(30)を形成し7、さらに第3の1.Sでの切…
i分離用の第3の開溝(20)をji7k。In FIG. 2, there is a second ? on the back side, as shown in FIG. 7, and a third 1. Cut at S...
ji7k the third open groove (20) for i separation.
この第2の電極(4)は本発明の特にである導電酸化膜
(Co) (45)を用いた。その厚さは50〜15
00 Aの厚さに形成させた。For this second electrode (4), a conductive oxide film (Co) (45), which is particularly used in the present invention, was used. Its thickness is 50-15
It was formed to a thickness of 0.00A.
このCOとして、ここではITO(1!tJ化インシ人
−ム酸化スズを主成分とする混合物) (45)を形
成した。このCOとして酸化インジ2−ムを主成介入し
て形成させるととも可能であった。この結果、半導体に
密接して(45) (45’)を自−已し7めた。さ
らにその上面は反射用金属(RM) (4(i)の銀
またはアルミニュームを主成分とした金属とした。例え
(J珪素か1%以l・代表的には0.1〜1車量%添加
されたアルミニュームを300〜3000 人の厚さに
形成した。As this CO, ITO (a mixture whose main component is 1!tJ incininium tin oxide) (45) was formed here. This CO could be formed by intervening as a main component of indium oxide. As a result, (45) (45') were self-disconnected in close contact with the semiconductor. Furthermore, the upper surface is made of reflective metal (RM) (4(i), a metal whose main component is silver or aluminum. % doped aluminum was formed to a thickness of 300 to 3000.
このCOと閣の組合ゼは同時に裏面側での長波長光の反
射を促して600〜800nmの長波長光を有効に光電
変換さ・ヒるためにも合わせて有効である。This combination of CO and cabinet is also effective for promoting the reflection of long wavelength light on the back side and effectively photoelectrically converting long wavelength light of 600 to 800 nm.
さらにこのl?MJ二にニッケルを形成すると、電極部
(5)での外部引出し電極(23)との密着性を向上さ
せることができる。Furthermore, this l? By forming nickel on MJ2, it is possible to improve the adhesion between the electrode portion (5) and the external lead electrode (23).
これらは電子ビーム蒸′:4法またはPCVD法、ツメ
1−CVD法、フメト・プラズマCVD法を含むCVD
法を用いて半導体j−を劣化さゼないため、350’C
以下の温度で形成させた。These include electron beam evaporation: 4 method or PCVD method, Tsume 1-CVD method, and CVD method including fumet plasma CVD method.
350'C to avoid deteriorating the semiconductor j- using the method
Formed at the following temperatures:
本発明は、特にLSO際、第3の開溝を第1の素子領域
(31)にわたって設け、第1の素子の開放電圧が発生
ずる電極(39) (38)間の距離をレーザ直径の
20〜599代表的には3シとして、約3?離間せしめ
、加えてその第1の開溝と第3の開溝の中心間の距離で
ある「わたり深さ」を20〜40?とし、さらに第2の
開溝とは2ケ以上と大きく取ったことを特長としている
。即ら第ζ)の1111旨+X+7 (20)の中心は
第2の開溝(30)の中心に比べて20〜3す好ましく
は30〜10g7I−代表的には5オの深さ各5二第1
の素子側にわたって設けている。Particularly in LSO, the present invention provides a third open groove across the first element region (31), and the distance between the electrodes (39) and (38) where the open circuit voltage of the first element is generated is set to 20% of the laser diameter. ~599 Typically, it is about 3? In addition, the "crossing depth", which is the distance between the centers of the first open groove and the third open groove, is 20 to 40? Furthermore, it is characterized by having two or more large second open grooves. That is, the center of 1111+X+7 (20) of No. 1st
It is provided over the element side.
このわたり深さは1iii記したごとく、二1ンピュー
タのメモリにその深さをインゾノ1−″」−ろことによ
り光学モニターにより第1の開溝をモニターシムから、
第3の開溝をLSにより作製するごとに、フ、り高精度
にコンピュータ :Zントロールをし −Iニルフレジ
ストレイジョンを行うごとを本発明の’Bf kとして
いる。As mentioned in 1iii, the depth of this crossing is recorded in the memory of the 21 computer by means of an optical monitor and the first opening groove from the monitor shim.
Each time a third open groove is produced by LS, a high-precision computer:Z control is performed, and each time -I Nilfregistration is performed.
さらにこの第3の開溝の深さを1゛1りに第2の宙、’
ftt<を1徐去するのめでなくその一部の半J (
A−1−をM、去し第1の電極をもその一部に露呈セし
ぬること乙、:lより、開溝形成の際のLSの照射強度
(パ・ノー密度)のバラツキにより、第2の電極の一部
が残る・して、電気的に2つの素子が分離できなくなる
ことを防いだ。特にこのレーザー−光の強度は!、S−
(のスキャンスビ−1・がスキャンの開始、終了11h
において遅いため、結果的に定常スピ−−−1に比・\
て強−づさ・乙パワー か照射されてしまう。かかる領
域では第2の電極の除去にその−1・側の半導体層まで
除去してしまうことは自シJであった。もちろんこの時
第1の電極を除去してしまっては直列の連結ができない
ため、明らかに禁止される。またこの半導体の一部かス
キャンスピーートが大きい領域(パワー密度が小さい領
域)では残存してしても、リークが10 (A /cm
)以下においては実用上まったく問題にならなかったと
いう大きな特徴をイ1していた。Furthermore, the depth of this third groove is increased by 1.
It is not necessary to remove ftt< by 1, but to remove half of that part (
By removing A-1- and exposing part of the first electrode, due to the variation in the LS irradiation intensity (P/N density) when forming the open groove, This prevents a portion of the second electrode from remaining and making it impossible to electrically separate the two elements. Especially the intensity of this laser light! ,S-
(scansbee-1 starts scanning, ends 11h)
As a result, the steady speed is slow compared to 1.
It will be irradiated with strong power. In such a region, when removing the second electrode, it is inevitable that the semiconductor layer on the -1 side of the second electrode would also be removed. Of course, if the first electrode is removed at this time, series connection will not be possible, so this is clearly prohibited. Furthermore, even if some parts of the semiconductor remain in areas where the scan speed is high (areas with low power density), the leakage rate is 10 (A/cm).
) In the following, the major feature was that it did not pose any practical problems.
かくのごとく第2の電極をレーザ光を上刃より照射して
切断分離して開溝(20)を形成した場合を示している
。This shows the case where the second electrode is cut and separated by irradiating laser light from the upper blade to form an open groove (20).
このレーザ光は半導体特に第2の電極の下面に密接する
非単結晶半導体をもえくり出し除去し、その下の第1の
電極にまで至らしめた。このため第1の電極を耐熱性の
酸化スズを主成分とすると、ともに透光性であるため、
この第1の電極を残しレーザ光の熱エネルギーを吸収し
やすい半導体を第2の電極用材料とともに除去せしめて
第3の開溝を形成した。このことによりLSの最大の欠
点である出力(パワー密度W/(訓う1lill ia
l+をしにくい、Lいう欠点を実質的に除去することか
でさた。This laser light carved out and removed the semiconductor, especially the non-single crystal semiconductor that was in close contact with the lower surface of the second electrode, and reached the first electrode therebelow. For this reason, if the first electrode is made of heat-resistant tin oxide as its main component, since both are translucent,
The semiconductor, which easily absorbs the thermal energy of the laser beam, was removed together with the second electrode material, leaving the first electrode, to form a third groove. This leads to the biggest drawback of LS, the output (power density W/(learning1lill ia
This was done by essentially eliminating the disadvantage of L, which makes it difficult to perform l+.
特にこの半導体(3)か1〕41ジオ専体1ri (4
2ン、■型半導体1−(43) 、N型半導体Iff
(44)上例えば1つのI)IN接合を有ゼしめ、この
j刈外眠F′2ρ体層が微結晶または多結晶構造を自す
る、いわゆるその電気伝導度が1〜200 (Acm
)と高い伝導度を持つ場合、これらの半導体Jgを同
時に1ケ:人しでり。Especially this semiconductor (3) or 1] 41 Geo exclusive 1ri (4
2, ■ type semiconductor 1-(43), N type semiconductor Iff
(44) For example, there is one I)IN junction, and this F'2ρ body layer has a microcrystalline or polycrystalline structure, so-called electrical conductivity is 1 to 200 (Acm
) and high conductivity, one of these semiconductors Jg at the same time.
まうことにより、素Yを構成ず’:I ’I”#体内に
金属原子が残存する可能性を完全に除去でき、さりにこ
のスクライブした珪素系の表向に酸化物路ul)勿例え
ば酸化珪素(34)のバソンー、イノヨン脱を赤外光熱
による酸化により1役&Jてリ−り′)i流光′−1全
防止することは、高信頼性のためにきわめて白−ノであ
った。It is possible to completely eliminate the possibility that metal atoms remain in the body without forming the element Y, and in addition, it is possible to completely eliminate the possibility that metal atoms remain in the body. It was extremely difficult to completely prevent the desorption of silicon (34) by infrared photothermal oxidation in order to achieve high reliability.
さらに製造歩留り的にリークが10〜lOΔ/cmある
準不良装置(全体の5〜10%自する)に関し2ては、
この後弗酸1:硝酸3.#酸5を水Gてさらに5〜10
倍希釈して表面部のみを軽くエソチンクして、開溝部の
珪素を化学的に500 ・〜2000への、朶さに金属
不純物を除去することはリークの低減に有効であった。Furthermore, regarding semi-defective devices (5 to 10% of the total) with a leakage rate of 10 to 10Δ/cm in terms of manufacturing yield, 2.
After this, 1 part hydrofluoric acid and 3 parts nitric acid. # Add 5 acid to water G and add 5 to 10
It was effective in reducing leakage to chemically reduce the silicon in the open grooves to 500 to 2000 by diluting the silicon layer twice and lightly esotinking only the surface area, and to remove metal impurities in the pores.
かくして第2図(C)に示されるごとく、複数の素子(
31) (11)を連結部で直接接続する光電変換装
置を作ることかできた。Thus, as shown in FIG. 2(C), a plurality of elements (
31) We were able to create a photoelectric conversion device that directly connects (11) at the connecting part.
第2図(D)はさらに本発明を光電変換装置として完成
させんとしたものである。即らバ・ノシヘイソヨン映と
してプラズマ気相法により窒化珪素膜(21)を500
〜2000人の厚さに均一に形成さ一已、各素子間のリ
ーク電流の湿気等の吸着による発生をさらに防いだ。FIG. 2(D) shows an attempt to further complete the present invention as a photoelectric conversion device. That is, 500% of the silicon nitride film (21) was deposited using a plasma vapor phase method as a film.
It is formed uniformly to a thickness of ~2,000 mm, further preventing leakage current between each element from occurring due to adsorption of moisture, etc.
さらに外部引出し端子(23)を周辺部(5)にて設り
た。Furthermore, an external lead-out terminal (23) was provided at the peripheral portion (5).
これらにポリイミド、ポリアミド、カプトンまたはエポ
キシ等の自機樹脂(22)を充填した。These were filled with an in-house resin (22) such as polyimide, polyamide, Kapton or epoxy.
斯くして照射光(10)にスJしこの実施例のごとき基
板(60cmメ20cm)において各素子を中14.3
5mmX192 mmの短冊上に設り、さらに連結部の
rll150、外部引出し電極部の中10mm、周辺部
4+nmにより、実質的に580mmK192mm内に
40段を有し、有効面積(192m+n X 14.3
5mm 40 段 1102cmLIill ”バ
月、8%) を得ることができた。In this way, the irradiation light (10) is applied to each element on a substrate (60 cm by 20 cm) as in this example.
It is installed on a strip of 5 mm x 192 mm, and further has 40 stages within 580 mm K 192 mm due to rll 150 of the connecting part, 10 mm inside of the external extraction electrode part, and 4 + nm of the peripheral part, and has an effective area (192 m + n x 14.3
5mm, 40 steps, 1102cmLIll, 8%) was obtained.
その結果、セグメンIか10.8%(1、[)5q1n
)の変換効率を有する場合、パネルにて6.8%(理論
的には9.7%になるが、40段歯列連結のlit抗る
こ、上り実効変換効率か低下した)(八Ml (]O
OmW / cm’) )にて、73.8Wの出力電力
を有セしぬることができた。As a result, segment I was 10.8% (1, [)5q1n
), the panel has a conversion efficiency of 6.8% (theoretically it is 9.7%, but due to the 40-stage tooth row connection, the effective upstream conversion efficiency has decreased) (8Ml (]O
OmW/cm')), it was possible to achieve an output power of 73.8W.
さらにこのパネルを1500の高温放置う〜ス)−を行
うと1000時間を経て10%以下例えばパネル数20
1ダにて最悪4%、X −1,7%の出力像]−シかみ
られなかった。Furthermore, when this panel is left at a high temperature for 1500 hours, the percentage decreases to less than 10% after 1000 hours, for example, when the number of panels is 20.
At worst, the output image was 4% at 1 da, and the output image of -1.7% could not be seen.
これは従来のマスフカ式を用いて信東旧ノ1う一ストを
同一条件にて行う時、10時間で1リノ作不良パネル数
が17枚も発生してじようごとを考えZ) t:、驚異
的な値であった。This is due to the fact that when we used the conventional mass-scattering method to perform the Shinto Old No. 1 under the same conditions, 17 defective panels were generated in 10 hours.Z) t: , which was an amazing value.
第3図は3回のLSI程での開溝を作る最も代表的なそ
れぞれの開講の位置関係を示した縦断面図および平面図
(端部)である。FIG. 3 is a vertical cross-sectional view and a plan view (end) showing the most typical positional relationship of each opening to create an opening groove in three LSI cycles.
番号およびその工程は第2図と同様である。The numbers and steps are the same as in FIG.
第3図(A)は第1の開溝(13)、第1の素子(31
) 、第2の素子(11−) 、連結部(12)を自し
ている。FIG. 3(A) shows the first open groove (13) and the first element (31).
), a second element (11-), and a connecting portion (12).
図面より明らかなごとく、第1の開溝(13)は基板(
I)を少しえくっている。As is clear from the drawing, the first groove (13) is located on the substrate (
I) is slightly hollowed out.
さらに第2の開m (30)は、第1の素子(3])を
構成すべき半導体(3)の第1の電極(2)側にわたっ
て設りられ、半導体(3)をも除去し、その下の第1の
電極を残存させている。Furthermore, the second opening m (30) is provided across the first electrode (2) side of the semiconductor (3) that should constitute the first element (3), and also removes the semiconductor (3), The first electrode below it remains.
そのため、この第1の素子(31)の第1の電極(37
)と第2の素子(11)の第2の電極とが連結部(12
)にてこの第2の電極(38)より延びたCOによるコ
ネクタ(30)により、第1の電極(2)の上面(8)
で電気的に連結され、2つの素子が直列接続されている
。Therefore, the first electrode (37) of this first element (31)
) and the second electrode of the second element (11) are connected to the connecting portion (12
) at the top surface (8) of the first electrode (2) by means of a CO connector (30) extending from this second electrode (38).
The two elements are connected in series.
さらに図面において、PNまたはI’IN接合を少なく
とも1つ有する半導体(3)ここでは1つの5ixC1
((0< x< 1 ) P型−I型S1−微結晶化し
たN型Si (44)よりなる1つのPIN接合を存す
る半導体が設けられている。Further in the drawing, a semiconductor (3) with at least one PN or I'IN junction, here one 5ixC1
((0<x<1) A semiconductor having one PIN junction consisting of P-type-I-type S1-microcrystallized N-type Si (44) is provided.
この第3の開溝(20)か、約207のわたり深さに第
1の素子(31)側にシフ1−シている。This third open groove (20) is shifted to the first element (31) side to a depth of about 207 mm.
このため、第3の開溝(20)のイ」端部6,1、:I
ネクタ部(30)の一部をうがって設けられている。For this reason, the "A" end 6,1, :I of the third open groove (20)
It is provided by hollowing out a part of the connector part (30).
かくして第1および第2の素1’−(31) (Ii
)のそれぞれの第2の電極(4)を電気的に切断分l’
litし、且つこの電極間のリークをも4oΔ/l:m
(IcrnrljあたりIOAのオーダーの意)以下に
小さくすることができた。Thus, the first and second elements 1'-(31) (Ii
) of each of the second electrodes (4) by electrically cutting portion l'
lit, and the leakage between the electrodes is also 4oΔ/l:m
(meaning the order of IOA per Icrnrlj).
この値10A/cmを基準として製造!L留りを評価す
ると、従来が50%であるに比べて70〜75%をII
し、究めて高い生産性をiηることができた。Manufactured based on this value of 10A/cm! When evaluating L retention, II
As a result, we were able to achieve high productivity.
第3図(B)は平坦図を示し、ま人ンとのM+:i部(
図面で下側)においで第1 第2133の開溝(13)
、 (18)、 (20)か設りられてい乙。Figure 3 (B) shows the flat view, M+: i part (
(lower side in the drawing) No. 1 No. 2133 open groove (13)
, (18), (20) have been established.
この方向でのリークをより少なくずr〕7′こめ、?1
テ導体(3)が第1の電極(2)を覆)構造にして第1
、第2の電極間のショートを少なくさ−Uろごとが特徴
である。Would you like to reduce the leakage in this direction? 1
The first conductor (3) covers the first electrode (2).
It is characterized by a U loop that reduces short circuits between the second electrodes.
加えて素子の端部は第1の電極(2)、半導体、第2の
電極(4)を一度にLSによりスクライブ(50) し
た。In addition, at the end of the element, the first electrode (2), the semiconductor, and the second electrode (4) were scribed (50) at the same time by LS.
この図面において、第1、第2、第3の開溝+1は60
〜20 を自し、連結部の中450〜8074代表的
には12シを有−已しめることかできた。In this drawing, the first, second, and third open grooves +1 are 60
~20 mm, with 450 ~ 8074 typically 12 mm in the connecting portion.
以上のYAGレーザのスボノl−Jmをその出力0.4
(2(p’) 〜4W (7シ)を用いた場合であるか
、さらにそのスポット径を技術思想において小さくし、
さらにその焦点距離を長くても50mm以」−とするこ
とにより、この連結部に必要な面積をより小さくひいて
は光電変換装置としての有効面積(実効効率)をより同
士させることができるという進歩性を有している。The output of the YAG laser is 0.4
(2(p') ~ 4W (7shi) is used, or the spot diameter is further reduced based on the technical concept,
Furthermore, by setting the focal length to 50 mm or more at the longest, the area required for this connection can be reduced, and the effective area (effective efficiency) of the photoelectric conversion device can be further increased. have.
第4図は電卓用等の大きなパネルではなく小さな光電変
換装置6゛を同時に多量製造−Uんとした時の外部引出
し電極ij;を拡大して示したものである。FIG. 4 is an enlarged view of the externally drawn electrodes ij when a small photoelectric conversion device 6' is mass-produced at the same time instead of a large panel for a calculator or the like.
第4ヌ1(Δ)は第2図に対応しているが、外部引出し
電極部(5)は導電性ゴム電極(47)に接触するパノ
l” (49)を有し、このパッド(49)は第2の電
極(上側電極)(4)と連結している。The fourth nut 1 (Δ) corresponds to FIG. ) is connected to the second electrode (upper electrode) (4).
この時電極(47)の加圧か強゛1きてパ:/ l”
(49)がその下の半導体(3)を突き(友りで第10
′市]9メ(2)とショー併しても(49)と(2)よ
、が1・・11−Lないように開溝(13)か設りられ
てい・5゜また外側部は第1の電極、半導体、第2 [
2) i−、i:i 1.”Iλを同時に一力のLSに
てスクライブをした開7:l (!′I(1)で切1I
ji分1ilillされている。At this time, the pressure on the electrode (47) is very strong.
(49) pokes the semiconductor (3) below it (10th
' City] An open groove (13) is provided so that even when 9 meters (2) and the show are combined, (49) and (2) are not 1...11-L. 5 degrees and the outer part is The first electrode, the semiconductor, the second [
2) i-, i:i 1. ``Iλ was scribed at the same time with one force LS 7:l (!'I (1) cut 1I
It has been 1 liter for 1 minute.
さらに第4図(B)は下側の第1の電極(2)に連結し
た他のパノ+=’ (48)か第2の電極+4 :Ii
l !こより (30)にて連結して設のられている。Furthermore, FIG. 4(B) shows another pano +=' (48) or the second electrode +4 connected to the lower first electrode (2).
l! It is connected and installed at (30).
さらにパノl” (48)は導電性rツノ、、電極(4
G)と接触しており、外部に電気N6こ連結している。Furthermore, the pano l" (48) has conductive r horns, electrodes (4
G) and is electrically connected to the outside.
ここでも開溝(30) (20) (50)に、j
、リパノ1) 2
(48)は全く隣の光電変換装)1tとjt電気的分離
されており、この装置間のカラスリJ141iを後l−
稈に11、り分離切11iすることにより、1・つのパ
イルてζ゛iわせ用マスクを仝(用いることなしに、多
数の光′lt変換装置をつ(ることかできるという’l
&徴を白する。Again, in the open groove (30) (20) (50), j
, Ripano 1) 2 (48) is completely electrically isolated from the adjacent photoelectric conversion device) 1t, and after the Karasuri J141i between this device,
By making separate cuts 11 and 11i in the culm, it is possible to install a large number of light conversion devices in one pile without using a mask for ζ'i.
& whiten the signs.
例えは20cmX 60cmのパネルにて6cmA1.
5cmの光電変換装置(ηバ1.用)を作らんとすると
、一度に130個の電卓用太陽電池を作ることができる
ことがわかる。For example, a panel of 20cm x 60cm is 6cmA1.
If we try to make a 5cm photoelectric conversion device (for η bar 1), we can see that 130 solar cells for calculators can be made at one time.
つまり光電変換装置は有機樹脂モールF’ (22)で
電極部(5)、 (45)を除いて覆われており、この
後小電力用太陽電池を作る場合はガラス切りで切断すれ
ばよい。In other words, the photoelectric conversion device is covered with organic resin molding F' (22) except for the electrode parts (5) and (45), and if a small power solar cell is to be made after this, it can be cut with a glass cutter.
またさらにこのパネル例えば40cmX740cmまた
は(iocmx 20cmを3ケまたは4ヶ直列にアル
ミザノシ枠内に組み合わ一ロることによりパッケージさ
れ、120cm%40cm のNIEDO規格の大電
力用のパネルを設けることが可能である。Furthermore, it is possible to package this panel by combining three or four panels in series, for example, 40 cm x 740 cm or (iocm x 20 cm) in an aluminum frame, to provide a high power panel of 120 cm % 40 cm 2 according to the NIEDO standard. .
またこのN+:OO規格のパネルはシーフレ、クスによ
り弗素系保護膜を本発明の光電変換装置の反射面側(図
面では上側)にはりあわせて合わせ、風圧、雨等に対し
機械強度の増加を図ることも有効である。In addition, this N+:OO standard panel is made by laminating a fluorine-based protective film on the reflective surface side (upper side in the drawing) of the photoelectric conversion device of the present invention using Schiefle and glue to increase mechanical strength against wind pressure, rain, etc. It is also effective to aim for this.
本発明において、基板は透光性絶縁基板のうら特にガラ
スを用いている。In the present invention, the substrate is made of glass, especially the back side of the transparent insulating substrate.
しかしこの基板として可曲性有機樹脂または有機樹脂」
二に1箕化珪素または窒化工」をO,l・=−〇、弁の
厚−さに形成した複合基板を用いゑ、ことは右りノごあ
る。However, this substrate can be used as a flexible organic resin or an organic resin.
This is true because a composite substrate made of silicon nitride or silicon nitride is used to form a valve with a thickness of O, l·=-〇.
特にごの複合基(侵を前記し〆こ実施例に通用J−ろと
、酸化珪素または窒化珪素がこの11/+iの訂1・を
m傷して基板とCTFとの混合物を作ってしまうことを
防く、いわゆるフロ、キング9J)果をく1して勃に有
りJであった。In particular, silicon oxide or silicon nitride damages this 11/+i correction to create a mixture of the substrate and CTF. The so-called Flo, King 9J), which prevents this from happening, was in a state of erectile dysfunction.
さらに本発明を以−■に実施例を記してそのif’n
1l11をネ市完する。Further, the present invention will be described below with examples and if'n.
Completed 1l11.
実施例1
第2[訃の図面に従ってこの実施例を小′4゜RIJら
透光性基板(」)として化パi′強化カラスj1.′さ
1.1mm 、 JKさ60cm 、 llJ 20c
+nを用いた。Embodiment 1 This embodiment was prepared according to the drawings of 2nd [Mr. 'Length 1.1mm, JK height 60cm, llJ 20c
+n was used.
この土面に酸化珪素11Aを01の111Iさに塗(・
]シ、プロ)キング層とした。Apply silicon oxide 11A to 111I of 01 on this soil surface (・
], professional) King layer.
さらにその上にCTFをIT 01600 A +sn
O,ニジooAをフォト・プラスマC1,ID法により
作間した。Furthermore, add CTF on top of that IT 01600 A +sn
O, NijiooA was cropped using the photo plasma C1, ID method.
さらにこの後、第1の開溝をスボノlIM407’、出
力IWのYAGレ−づ−をマイクl」!ンビノ、−夕に
より制御して1〜5m/分(平均3m/分)の走査速度
にて作製し、た。Furthermore, after this, the first open groove is connected to Subono IM407', and the output IW YAG laser is connected to Microphone! The scanning speed was 1 to 5 m/min (average 3 m/min) and controlled by the Ambino and Yu.
素子領域(31) (II)は15mm1lJとした
。The element area (31) (II) was 15 mm 1 lJ.
ア
この後公知のpcvo法、フォー−CVD法またはフλ
1・・プラズマCVl)tノ、により第2図に示したP
(42)1 (43) N (44)接合を1つ有す
る非単結晶半導体を作製した。After this, the known pcvo method, four-CVD method or four-λ
1. P shown in FIG. 2 by plasma CVl)t
A non-single crystal semiconductor having one (42)1 (43) N (44) junction was fabricated.
その全厚さは約0.53Aであった。Its total thickness was about 0.53A.
かかる後、第1の開溝をテレビにてモニターし度にてL
Sにより第2の開a(18)をその開溝表面を酸化して
作製した。After this, the first open groove was monitored on the TV and the L
A second opening a (18) was prepared by oxidizing the surface of the opening groove with S.
さらにこの全体をCOであるITOをフォト・プラズマ
CVD法により平均膜厚1050Δに作製して、第2の
電極(45)コネクタ(30)を構成せしめた。Further, ITO, which is CO, was formed on the entire structure to have an average thickness of 1050Δ by photo-plasma CVD method, thereby forming the second electrode (45) and connector (30).
加えて珪素が0.5重量%添加されたアルミニュームを
同様に電子ビーム蒸着法により1000 Aの厚さに形
成してRMとした。In addition, aluminum to which 0.5% by weight of silicon was added was similarly formed to a thickness of 1000 A by electron beam evaporation to form an RM.
さらに第3の開溝(20)を同様に酸化雰囲気中にてL
Sにより第2の開溝(18) 、↓り興lのイ)ノこシ
′)深さに第1の素子(31)側にノットして形成さ−
U第2図(C)を得た。Furthermore, the third open groove (20) is similarly placed in an oxidizing atmosphere.
The second open groove (18) is formed by knotting on the first element (31) side at the depth of the second open groove (18).
Figure 2 (C) was obtained.
この時第3の開?+’ljの深さは図面シ、二車゛Jご
とく、その底部は第1の電極の表面にン」、(”’I’
、−Jていノコ。The third opening at this time? The depth of +'lj is as shown in the drawing, and its bottom is on the surface of the first electrode, as shown in the figure.
, -J Tenoko.
このため、C,0,RMおよび」′導イ本+=rは死金
に14:人されていた。For this reason, C, 0, RM and ''Guidebook+=r' were 14:00% dead money.
レーザー光は出力IWとし、他は第2の開溝の竹製と同
一・条件とした。The output of the laser beam was IW, and the other conditions were the same as those for the second open groove made of bamboo.
かくして第2図(C)を作製した。In this way, FIG. 2(C) was produced.
第2図(C)の工程の後、パa′、/しの端7HBをレ
ザ光出力1弱にて第1の7h極、コに導体、第2の重重
〇にのすべてをガラス端より4n+m内(則でに力形に
走査し、パネルの枠との電気的短絡を防」[し7た。After the process shown in Figure 2 (C), connect the ends 7HB of PA' and / to the first 7H poles with a laser light output of a little less than 1, the conductor to A, and the second conductor to all from the glass end. 4n+m (scan regularly in a force shape to prevent electrical short circuit with the panel frame).
このf&、バノシヘインヨンIIQ (2i > をI
ICν11 l大またはフメFCvD法により窒化珪集
lI俯を+oooXの厚さに250’Cの温度にて作製
した。This f&, Banoshiheinyo IIQ (2i > I
A silicon nitride aggregate was fabricated to a thickness of +oooX at a temperature of 250'C by ICv11L or Fume FCvD method.
すると20cm X 60cmのパネルに15mm中の
素子を110段作ることができた。As a result, it was possible to create 110 stages of 15 mm elements on a 20 cm x 60 cm panel.
パネルの実効効率として八Ml (100In W
/ cm’)にて6.8%、出カフ4.3Wを(4るこ
とができた。The effective efficiency of the panel is 8Ml (100InW
/cm'), I was able to achieve a power output of 6.8% and a cuff output of 4.3W (4).
有効面積は1102c+Hであり、パネル全体の91.
8%を有効に利用゛Jることかできた。The effective area is 1102c+H, and the total area of the panel is 91.
We were able to make effective use of 8%.
実施例2
基板ガラスとして厚さ1.1mm大きさ20cm W
60cmを用いた。さらに一つの電卓用光電変換装置を
5cmK1.5cmとして複数個同一基板上に作製した
。ここでは素子形状を9mmy13mm 5段連続アレ
ーとした。Example 2 As a substrate glass, thickness 1.1 mm and size 20 cm W
60 cm was used. Furthermore, a plurality of photoelectric conversion devices for calculators each having a size of 5 cm and a width of 1.5 cm were fabricated on the same substrate. Here, the element shape was a 5-stage continuous array of 9 mm x 13 mm.
第1の電極しまITO(400λ) +5nOt(20
OA) 、PIN接合を有する非単結晶半導体の第2の
電極はITO(300A)+金属(500A)として作
った。その他は実施例1と同様である。First electrode striped ITO (400λ) +5nOt (20
OA), the second electrode of a non-single crystal semiconductor with a PIN junction was made as ITO (300A) + metal (500A). The rest is the same as in Example 1.
連結部は10pとし、外部電極とは第4図(A)(B)
のW#造として設けた。The connecting part is 10p, and the external electrode is shown in Fig. 4 (A) (B).
It was set up as a W# structure.
すると160ケの電卓用装置を一度に作ることができた
。As a result, he was able to make 160 calculator devices at once.
4.5%の実効変換効率として螢光打丁200Iχでテ
ストをした。Tests were conducted with a fluorescent knife 200Ix with an effective conversion efficiency of 4.5%.
その結果83%の最終製造歩留りを得ることができた。As a result, a final manufacturing yield of 83% could be obtained.
これは従来方法においてしよ40〜50シロしか胃ら、
!′トず、かつ連結部の必要面積か人きく、3.2%ま
でしかその実効変換効率が得られなか−ツたことを考え
ると、きわめて有〃Jなものてあ−2た。In the conventional method, this cost only 40 to 50 kilos from the stomach.
! Considering that the effective conversion efficiency could only be obtained up to 3.2% due to the required area of the connecting portion, this was extremely significant.
その他は実施例1と同様である。The rest is the same as in Example 1.
実施例3
この実施例は実施例2であって、基板を1ケの厚さの透
光性有機樹脂であるボリイミI樹脂を用いた。Example 3 This example is Example 2, and the substrate was made of Boliimi I resin, which is a translucent organic resin and has a thickness of one layer.
さらにその上にブロッキング層として0.2274の酸
化珪素をプラズマ気相法によりシランと炭酸カスの反応
により250’Cの温度で作製して、この自機樹脂がL
Sにより損傷を受けないように3−るため0)ブロッキ
ング層とした。Furthermore, as a blocking layer, silicon oxide of 0.2274 was made at a temperature of 250'C by the reaction of silane and carbonate scum by plasma vapor phase method, and this self-produced resin was
In order to prevent damage from S, a blocking layer was used.
その他は実施例2と同様である。The rest is the same as in Example 2.
かかる方法においては、基板の価(;1か実施例2にお
いては30円かか−、ていたか、これを2円/′l看車
用素子にまですることができた。In this method, it was possible to reduce the cost of the substrate (which was 30 yen in Example 2) to 2 yen/'l for the vehicle element.
加えてシー1〜より各電卓用素子・を分離するのGこ裁
断または鋏を用いて行うことかできるため、きわめて加
工性に富み、安(il[iであった。In addition, since each calculator element can be separated from Sea 1 by cutting or using scissors, it is extremely easy to work with and is easy to use.
さらにこのシー1−より切断する場合、10〜15Wの
強いパルス光を用いたLSにより自動切断が可能となっ
)こ。Furthermore, when cutting from this sea 1-, automatic cutting is possible using LS using strong pulsed light of 10 to 15 W).
この実施例に、おいては、第2図(I))に示すごとく
、北側の保護用有機樹脂(22)を重合わせることによ
り、有機4R4脂シー1−の間に光電変換装置をはさむ
構造とすることができ、可曲性を有し、きわめて安価で
多量生産が可能になった。In this embodiment, as shown in FIG. 2(I)), the photoelectric conversion device is sandwiched between the organic 4R4 resin sheets 1- by overlapping the protective organic resin (22) on the north side. It has flexibility and can be mass-produced at an extremely low cost.
この実施例での歩留りは160ケ作ったうらの72%を
4.5%の実すJ変換効率を下限として得ることができ
た。The yield in this example was 72% of the 160 pieces produced, with a J conversion efficiency of 4.5% as the lower limit.
第2図〜第4図において、光入射は下側の透光性絶縁基
板よりとした。In FIGS. 2 to 4, light was incident from the lower translucent insulating substrate.
しかし本発明はその光入射側を下側に限定するものでは
ない。However, the present invention does not limit the light incident side to the lower side.
また本発明においては、基板側よりI”IN接合を積層
した。しかしその逆に基板側よりNIP接合を形成し、
このl)型半導体に50〜1500大のSnO詠c。In addition, in the present invention, I''IN junctions are stacked from the substrate side.However, conversely, NIP junctions are formed from the substrate side,
This l)-type semiconductor has a SnO coefficient of 50 to 1,500.
として設け、さらにそのL面にRMを300〜3000
Aの厚さに形成してもよい。RM of 300 to 3000 on the L side.
It may be formed to have a thickness of A.
以上のH’F細な説明においては、■・側より光!!4
44,1を行う場合の光電変換装置を基本とし7て記し
7ノコ。In the detailed explanation of H'F above, ■ Light from the side! ! 4
44, 7 is written based on the photoelectric conversion device when performing 1.
しかし絶縁基板が非透光性であって、1力、Yり光照射
がなされる積層構造の光?Ja変模装:1ζ:によ賞)
−Cも、本発明は有効である。かかる場合番よ第1の電
極は絶縁基板に密接してアル\−j、−ム求た’r:!
’、 tIJを主成分とする反射4j1′金属とその一
1而に50 = ] 500Aの透光性導電膜とを設り
て第1 に’) ’t:4 J)’y4とし7、さらに
非単結晶半導体上に透光性導電++Xを第2の電極とし
て形成すればよい。However, the insulating substrate is non-light-transmitting, and the light of a laminated structure where Y light is irradiated? Ja transformation: 1ζ:yo award)
-C is also effective in the present invention. In such a case, the first electrode is in close contact with the insulating substrate.
', a reflective 4j1' metal whose main component is tIJ, and a transparent conductive film of 500 A is provided first') 't: 4 J)'y4 and 7. A transparent conductive layer ++X may be formed as a second electrode on a non-single crystal semiconductor.
第1図は従来の光電変換装置のに& Llji面図−ζ
3)る。
第2図は本発明の光電変換装置の製造上程を小す縦断面
図である。
第3図は本発明の光電変換装置0) l+i(1lJi
1lii 121−CJ)る。
第4図は本発明の他の光電変換装:i!1の:41;分
1ツム人をした縦断面図である。
特許出願人
3ツノ2//
h?
ぢtめ
37 12 1+
(A) CB)
(A)
(Bン掌4(2)Figure 1 is a side view of a conventional photoelectric conversion device.
3). FIG. 2 is a longitudinal cross-sectional view showing the manufacturing process of the photoelectric conversion device of the present invention. FIG. 3 shows the photoelectric conversion device 0) l+i(1lJi
1lii 121-CJ). FIG. 4 shows another photoelectric conversion device of the present invention: i! 1:41: This is a vertical cross-sectional view of the Tsumu people. Patent applicant 3 horns 2 // h?ぢtme37 12 1+ (A) CB)
(A)
(Bunsho 4 (2)
Claims (1)
接して光照射により光起電力を発生させうる非単結晶半
導体と、該半導体上に密接して第2の電極とを有する光
電変換素子を複数個互いに電気的に直列接続せしめて前
記絶縁基板上に配設した光電変換装置の作製方法におい
て、前記絶縁基板上の第1の導電膜にレーザ光を照射し
て第1の開溝を形成し、前記導電膜を複数の所定の形状
に分割して第1の電極を形成する工程と、該第1の電極
および前記開溝」二に前記非単結晶半導体を形成する工
程と、該半導体にレーザ光を照射して第2の開溝を形成
する工程と、前記半導体および前記第2の開溝上に第2
の導電膜を形成する工程と、該工程の1&、該導電膜に
レーザ光を照射して第3の開講を前記第2の導電膜およ
び該導電11W下の半導体をも除去して少なくとも一部
に第1の導電膜を露呈するごとにより前記第2の電極を
形成する工程とを自することを特徴とする光電変換半導
体装15作製力方法2、特許請求の範囲第1項において
、第3の開〆Iηは第1の開溝に比べて20〜4094
のわたり深さを有して形成せしめたことを特徴とする光
電変換半導体装置作製方法。1. A first electrode of a conductive film on an insulating substrate, a non-single crystal semiconductor that can generate a photovoltaic force when irradiated with light closely on the electrode, and a second electrode closely on the semiconductor. In the method for manufacturing a photoelectric conversion device in which a plurality of photoelectric conversion elements having a plurality of photoelectric conversion elements are electrically connected to each other in series and disposed on the insulating substrate, a first conductive film on the insulating substrate is irradiated with a laser beam. forming a first groove and dividing the conductive film into a plurality of predetermined shapes to form a first electrode; and forming the non-single crystal semiconductor in the first electrode and the groove. a step of irradiating the semiconductor with a laser beam to form a second groove; and a step of forming a second groove on the semiconductor and the second groove.
a step of forming a conductive film, step 1& of the step, and a third step of irradiating the conductive film with a laser beam to remove at least a portion of the second conductive film and the semiconductor under the conductive film. 2. Method 2 for manufacturing a photoelectric conversion semiconductor device 15, which comprises the step of forming the second electrode each time the first conductive film is exposed. The opening Iη is 20 to 4094 compared to the first opening groove.
1. A method for manufacturing a photoelectric conversion semiconductor device, characterized in that the device is formed with a spanning depth.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58067969A JPS59193075A (en) | 1983-04-18 | 1983-04-18 | Manufacture of photoelectric conversion semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58067969A JPS59193075A (en) | 1983-04-18 | 1983-04-18 | Manufacture of photoelectric conversion semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59193075A true JPS59193075A (en) | 1984-11-01 |
Family
ID=13360310
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58067969A Pending JPS59193075A (en) | 1983-04-18 | 1983-04-18 | Manufacture of photoelectric conversion semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59193075A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61116884A (en) * | 1984-11-12 | 1986-06-04 | Semiconductor Energy Lab Co Ltd | Manufacture of photoelectric conversion semiconductor device |
EP1727211A1 (en) * | 2005-05-27 | 2006-11-29 | Sharp Kabushiki Kaisha | Method of fabricating a thin-film solar cell, and thin-film solar cell |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5712568A (en) * | 1980-06-02 | 1982-01-22 | Rca Corp | Method of producing solar battery |
JPS5753986A (en) * | 1980-07-25 | 1982-03-31 | Eastman Kodak Co | |
JPS57176778A (en) * | 1981-03-31 | 1982-10-30 | Rca Corp | Solar battery array |
-
1983
- 1983-04-18 JP JP58067969A patent/JPS59193075A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5712568A (en) * | 1980-06-02 | 1982-01-22 | Rca Corp | Method of producing solar battery |
JPS5753986A (en) * | 1980-07-25 | 1982-03-31 | Eastman Kodak Co | |
JPS57176778A (en) * | 1981-03-31 | 1982-10-30 | Rca Corp | Solar battery array |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61116884A (en) * | 1984-11-12 | 1986-06-04 | Semiconductor Energy Lab Co Ltd | Manufacture of photoelectric conversion semiconductor device |
EP1727211A1 (en) * | 2005-05-27 | 2006-11-29 | Sharp Kabushiki Kaisha | Method of fabricating a thin-film solar cell, and thin-film solar cell |
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