JPH10135239A - Manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method, capable of ensuring a sufficient height of a gate electrode having approximately a T-shaped profile and fine workability of the gate electrode. SOLUTION: Resist films 2a, 2b, 3, 4 having specified temp. differences are coated on a semiconductor substrate 1, then irradiated three times with an electron beam at different exposure rates and developed to form openings 5, 6, 7 different in aperture size, and a metal material 8 is deposited and lifted off to form a T-shaped gate electrode 9 having an intermediate part 9C between the head 9a and leg 9b. A protective insulating film is formed thereon.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a gate electrode having a substantially T-shaped cross section.
(MEtal Semiconductor Field Effect Transistor), HEMT (High Electron Mobility Transistor) and MMIC (Monolithic Microwave I
There is a method of manufacturing a semiconductor device having a Schottky gate used for an integrated circuit).

[0002]

In a semiconductor device used for amplifying a signal in a microwave band, a T-type gate capable of achieving both a shortened gate length and a low gate resistance which is advantageous for high-frequency operation. It is common to employ electrodes. After the formation of the T-type gate electrode, a protective insulating film is formed on the surface thereof.
If the height to the top of the mold gate electrode is insufficient, the protective insulating film is filled between them, and if there is a gap between them in such a state. , The parasitic capacitance increases.

In order to prevent the increase of the parasitic capacitance, if the length of the leg is increased in order to secure a sufficient height to the head of the gate electrode, a portion related to the determination of the gate length of the gate electrode, that is, the leg is a semiconductor. The fine workability of the width dimension of the portion in contact with the substrate is reduced. In addition, since the leg of the gate electrode is formed in a shape in which the joint with the semiconductor substrate is shorter than the joint with the head, disconnection between the head and the leg is likely to occur. There is.

As a prior art for solving such a problem, for example, Japanese Patent Application Laid-Open No. 5-109778 discloses a resist layer in which a tapered opening having a surface portion wider than a bottom portion is formed by a single electron beam exposure. A technique is disclosed in which the legs are formed in such a manner that the cross-sectional shape of the legs formed by metal vapor deposition in the openings is rectangular, that is, both sides of the legs are substantially perpendicular to the semiconductor substrate. ing.
However, such a technique has a problem in reproducibility of the bottom dimension at the opening of the resist layer, that is, the gate length.

Japanese Patent Application Laid-Open No. 6-302617 discloses an intermediate portion having a width smaller than the width of the head and wider than the width of the leg at the junction between the head and the leg of the T-type gate electrode. A technique for forming a part is disclosed. By forming such an intermediate portion, even when the height of the T-type gate electrode is sufficiently ensured, the strength of the bonding portion can be ensured. However, in this method, since the developing step for determining the width of the intermediate portion and the leg is performed at a time, the thickness of the resist is increased so as not to increase the parasitic capacitance, and the leg of the gate electrode is formed. If the length is increased, it is inevitable that the fine workability of the portion related to the determination of the gate length is reduced.

[0006] The present invention is to solve the above problems,
An object of the present invention is to provide a method of manufacturing a semiconductor device capable of sufficiently securing the height of a gate electrode having a T-shaped cross section and also ensuring the fine workability of the gate electrode.

[0007]

According to a method of manufacturing a semiconductor device according to the present invention, in a first step, a first lower resist film having a predetermined sensitivity is formed on a semiconductor substrate.
After the second lower resist film, the intermediate resist film, and the upper resist film are collectively formed by sequentially applying them, exposure and development are sequentially performed under predetermined conditions in the second, third, and fourth steps, respectively. Accordingly, an upper opening having an overhang shape, a second lower opening having an opening size smaller than the upper opening, and a first lower layer having an opening size smaller than the second lower opening and reaching the semiconductor substrate surface Openings are respectively formed. Then, after depositing the electrode metal material in the fifth step, the resist film of each layer is dissolved and removed in the sixth step, so that the joint between the head and the leg in the substantially T-shaped cross section is formed. A gate electrode having a shape having an intermediate portion is formed. Further, in a seventh step, a protective insulating film is formed on the gate electrode and the semiconductor substrate.

[0008] Therefore, after the resist films of the respective layers are collectively formed in the first step, each opening can be formed by repeating the simple steps of exposure and development. The gate electrode of the semiconductor device can be finely processed by separately performing the step of determining the opening dimensions of the second and first lower-layer openings, which are the cross-sectional width dimensions of the intermediate part and the leg part of the gate electrode. In addition, the height of the gate electrode can be sufficiently secured,
When the protective insulating film is formed, the parasitic capacitance generated between the head of the gate electrode and the semiconductor substrate can be reduced.

According to a second aspect of the present invention, in the first step, a lower resist film, an intermediate resist film, and an upper resist film each having a predetermined sensitivity are sequentially applied on the semiconductor substrate. In this way, after the formation in a lump, the upper and lower openings having an overhang shape are made smaller by sequentially exposing and developing under predetermined conditions in the second, third and fourth steps, respectively. A concave portion having an opening size and a lower layer opening portion having an opening size smaller than the concave portion and reaching the semiconductor substrate surface are respectively formed.
Then, after depositing the electrode metal material in the fifth step, the resist film of each layer is dissolved and removed in the sixth step, so that the joint between the head and the leg in the substantially T-shaped cross section is formed. A gate electrode having a shape having an intermediate portion is formed. Further, in a seventh step, a protective insulating film is formed on the gate electrode and the semiconductor substrate. Therefore, the resist film can be reduced by one layer, and the first step can be further simplified.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
This will be described with reference to FIGS. 1 to 7 are schematic sectional views showing a process of manufacturing a semiconductor device having a T-type gate electrode. In FIG. 1, a high-resolution electron beam (EB) resist film is sequentially formed in layers on a semiconductor substrate (hereinafter simply referred to as a substrate) 1 on which an operation layer is formed as follows. I have.

First, a first lower resist film 2a having a relatively low sensitivity is formed with a thickness of, for example, 250 nm, and a second lower resist film 2a having a higher sensitivity than the first lower resist film 2a is formed on the first lower resist film 2a. The lower resist film 2b is formed to a thickness of, for example, 150
nm. Next, an intermediate resist film 3 having a higher sensitivity than the second lower resist film 2b is formed to a thickness of, for example, 300 nm.
The upper resist film 4 having a lower sensitivity than the intermediate resist film 3 is formed with a thickness of, for example, 250 nm (first step).

In this case, for example, the first lower resist film 2a
And, as the upper resist film 4, polymethyl methacrylate acting as a positive EB resist is used, and as the second lower resist film 2b and the intermediate resist film 3, a polyalkyl methacrylate-based resist having higher sensitivity than the above polymethyl methacrylate is used. .

Next, as shown in FIG. 2, exposure is performed by the first electron beam irradiation, and an opening (upper opening) 5 is formed in the upper resist film 4 and the intermediate resist film 3 by subsequent development. Form. For example, at this time, the acceleration voltage of the electron beam is set to 25 KV, the exposure amount is set to about ²⁰ μC / cm ^2, and development is performed with a mixed solution of methyl isobutyl ketone and isopropanol (second step). In this case, since the second lower resist film 2b uses an EB resist having sufficiently lower sensitivity than the intermediate resist film 3, the opening 5 can be formed with high reproducibility.

When such a second step is performed, the shape of the opening 5 depends on the sensitivity difference between the upper resist film 4 and the intermediate resist film 3, and the opening dimension (for example, 0 mm) of the upper resist film 4 portion. 0.5 to 0.8 μm) is slightly smaller than the opening size of the intermediate layer resist film 3, so that the upper resist film 4 is formed so as to overhang the intermediate layer resist film 3. You.

Subsequently, as shown in FIG. 3, by developing after exposure by the second electron beam irradiation,
Opening (second lower opening) 6 in second lower resist film 2b
Is formed so that the opening dimension is, for example, 0.3 to 0.4 μm. The exposure amount at this time is, for example, 10 μC / c
m ² and development with a mixed solution of methyl isobutyl ketone and isopropanol (third step).

Further, as shown in FIG. 4, after exposure by the third electron beam irradiation, an opening (first lower layer opening) 7 which reaches the surface of the substrate 1 by development is made into a first lower layer resist. Formed on the film 2a (fourth step). The exposure amount at this time is, for example, 200 μC / cm ² or ² nC
/ Cm, and developed with a mixed solution of methyl isobutyl ketone and isopropanol to obtain a size of 0.1
An opening size that can realize a gate length of 5 μm or less is obtained. In this case, it is considered that a finer gate length can be realized by increasing the acceleration voltage of the electron beam.

After the opening 7 is formed in the first lower resist film 2a as described above, the substrate 1 is etched using the first lower resist film 2a as a mask, if necessary for the structure of the semiconductor device.

Thereafter, as shown in FIG. 5, the surface of the substrate 1 facing the opening 7 and the resist films 2a, 2b, 3, 4 of each layer are formed.
A metal material 8 for an electrode is deposited thereon (fifth step).
Subsequently, by immersing the semiconductor device in the solution, unnecessary portions of the metal material 8 are removed (lift-off) together with the remaining resist films 2a, 2b, 3 and 4, as shown in FIG. Thereby, between the head 9a and the leg 9b, a substantially T-shaped gate electrode 9 having an intermediate portion 9c whose sectional width is smaller than the head 9a and larger than the leg 9b is formed. (Sixth step).

At this time, as described above, since the upper resist film 4 has a shape overhanging the intermediate resist film 3 in the opening 5, the gate electrode 9 is formed.
And unnecessary portions of the metal material 8 can be surely separated.

After the formation of the gate electrode 9, as shown in FIG. 7, a protective insulating film 10 is formed on the gate electrode 9 and the substrate 1 (seventh step). In FIG. 7, the first and second lower resist films 2a, 2a are previously formed at the time of applying the resist film in FIG. 1 so that a gap 11 is formed between the head 9a and the substrate 1.
The film thickness b is set with reference to the designed film thickness of the insulating film. By providing such a gap 11 between the head 9a and the substrate 1, the protective insulating film 1 having a large dielectric constant between the two.
Parasitic capacitance of the gate electrode 9 is reduced as compared with the case where it is satisfied by zero.

As described above, according to the present embodiment, after each of the resist films 2a, 2b, 3, and 4 having a predetermined sensitivity difference is applied and formed on the substrate 1, the resist films differ from each other. An electron beam is irradiated three times at an exposure amount, development is performed on each of them, openings 5, 6 and 7 having different opening dimensions are formed, and a metal material 8 is vapor-deposited and then lifted off, so that a head 9a and a leg 9a are formed. 9b, a T-type gate electrode 9 having an intermediate portion 9c was formed, and a protective insulating film 10 was formed thereon.

Therefore, in the second electron beam irradiation, the size of the opening 6, that is, the intermediate portion 9 c of the gate electrode 9 is formed.
Is determined, the opening dimension of the opening 7, that is, the width dimension (gate length dimension) of the leg 9b of the gate electrode 9 can be determined in the third electron beam irradiation.
Can be finely processed, and by forming the intermediate portion 9c, the head 9a and the leg 9b can be formed when the metal material 8 is deposited.
Disconnection can be prevented.

Further, the head 9a of the gate electrode 9 can be designed to be high, and even if the protective insulating film 10 is formed, the increase in the parasitic capacitance can be suppressed. In this case, the thickness of the first lower resist film 2a can be made smaller than the height of the head 9a, so that its fine workability can be sufficiently ensured, and the gate length which is important for high-frequency characteristics can be secured. Can be finely designed.

Further, according to this embodiment, in the first electron beam irradiation, an overhang shape is formed in the opening 5 due to a difference in sensitivity between the upper resist film 4 and the intermediate resist film 3, whereby the gate is formed. Since the electrode 9 and the unnecessary portion of the metal material 8 can be reliably separated, the unnecessary portion after the deposition of the metal material 8 can be easily removed.

(Second Embodiment) FIGS. 8 to 14 are schematic sectional views showing a process of manufacturing a semiconductor device according to a second embodiment of the present invention. The same parts as those in the first embodiment are denoted by the same reference numerals. In FIG. 8, a high-resolution EB resist film is sequentially formed on the substrate 1 in the form of a layer in the same manner as in the first embodiment.
The lower resist films 2a and 2b are replaced with a lower resist film 12 (first step). This lower resist film 1
2 is formed using, for example, the same polymethyl methacrylate as the upper resist film 3 with a thickness of 400 nm.

Next, as shown in FIG. 9, an opening 5 is formed in the same manner as in the second step in the first embodiment (second step). At this time, since the lower resist film 12 has sufficiently lower sensitivity than the intermediate resist film 3, the opening 5 has good reproducibility.
Can be formed.

Subsequently, as shown in FIG. 10, a concave portion 13 having a depth up to the middle of the lower resist film 12 is formed by performing exposure by the second electron beam irradiation and developing the resultant (see FIG. 10). Step 3). For example, the exposure amount at this time is about 100 μC / cm ^2, and development is performed with a mixed solution of methyl isobutyl ketone and isopropanol.

Further, by performing exposure after performing exposure by the third electron beam irradiation and then developing, as shown in FIG. 11, an opening having a smaller opening size than the concave portion 13 and reaching the substrate 1 (FIG. 11). (Lower opening) 14 to lower resist film 1
2 (fourth step). For example, at this time, the exposure amount is set to about 200 μC / cm ² or ² nC / cm, and development is performed with a mixed solution of methyl isobutyl ketone and isopropanol to obtain an opening 14 capable of realizing a gate length of 0.15 μm or less.

The subsequent steps are performed in the same manner as in the first embodiment, and as shown in FIGS.
After vapor deposition 5 (fifth step), unnecessary portions of the metal material 15 are removed (lifted off) together with the remaining resists 3, 4 and 12 to form a gate electrode 16 having a substantially T-shaped cross section. It is formed (sixth step).

After the formation of the gate electrode 16, a protective insulating film 17 is formed on the gate electrode 16 and the substrate 1 (seventh step). Also in this case, the gap between the head 16a and the substrate 1 can be obtained by setting the thickness of the lower resist film 12 in advance in applying the resist film in FIG. 8 with reference to the design value of the insulating film. 18 can occur.

As described above, according to the second embodiment, the number of resist films is smaller than that of the first embodiment, so that the cross-sectional shape is substantially T-shaped, and the intermediate portion is formed between the head 16a and the leg 16b. The gate electrode 16 having the portion 16c can be formed, and the first step can be further simplified.

The present invention is not limited to the embodiment described above and shown in the drawings, and the following modifications or extensions are possible. The first electron beam irradiation is performed under the condition that the intermediate resist film 3 and the upper resist film 4 are replaced by a single upper resist film having higher sensitivity than the second lower resist film 2b, and the upper resist film can be exposed. By performing development after irradiation, an opening having a shape in which the opening size on the surface of the upper resist film is smaller than the opening size inside the upper resist film is defined as the upper opening, and the opening 5 is used instead of the opening 5. It may be formed. By appropriately changing the material of the resist, the exposure may be performed using light such as ultraviolet rays, an ion beam, X-rays, or the like. The thickness of each resist film formed in each embodiment and the size of the opening due to exposure may be appropriately changed according to the design specifications of the gate electrode and the gate length. Further, the material of each resist film may be appropriately changed as long as the magnitude relation of the sensitivity difference between the layers is maintained.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device according to a first embodiment of the present invention (part 1).

FIG. 2 is a diagram corresponding to FIG. 1 (part 2);

FIG. 3 is a diagram corresponding to FIG. 1 (part 3);

FIG. 4 is a diagram corresponding to FIG. 1 (part 4);

FIG. 5 is a diagram corresponding to FIG. 1 (part 5)

FIG. 6 is a diagram corresponding to FIG. 1 (part 6);

FIG. 7 is a diagram corresponding to FIG. 1 (part 7);

FIG. 8 is a view (part 1) corresponding to FIG. 1 in a second embodiment of the present invention;

FIG. 9 is a diagram corresponding to FIG. 8 (part 2);

FIG. 10 is a diagram corresponding to FIG. 8 (part 3);

FIG. 11 is a diagram corresponding to FIG. 8 (part 4);

FIG. 12 is a diagram corresponding to FIG. 8 (part 5);

FIG. 13 is a diagram corresponding to FIG. 8 (part 6);

FIG. 14 is a diagram corresponding to FIG. 8 (part 7);

[Explanation of symbols]

1 is a semiconductor substrate, 2a is a first lower-layer resist film, 2b is a second lower-layer resist film, 3 is an intermediate-layer resist film, 4 is an upper-layer resist film, and 5, 6, and 7 are openings (upper-layer openings, second lower-layer films). 8 is a metal material (metal material for an electrode), 9 is a gate electrode, 9a is a head, 9b is a leg, 9c is an intermediate portion, 10 is a protective insulating film, and 11 is a protective insulating film. A gap, 12 is a lower resist film, 13 is a recess, 14 is an opening (lower opening), 15 is a metal material (metal material for an electrode),
16 is a gate electrode, 16a is a head, 16b is a leg, 16
c indicates an intermediate portion, 17 indicates a protective insulating film, and 18 indicates a void.

Claims (2)

[Claims] 1. A method of manufacturing a semiconductor device having a gate electrode having a substantially T-shaped cross section, comprising: forming a first lower resist film on a semiconductor substrate; and a second lower layer having higher sensitivity than the first lower resist film. A first step of sequentially applying and forming a resist film, an intermediate resist film having a higher sensitivity than the second lower resist film, and an upper resist film having a lower sensitivity than the intermediate resist film; A second step of forming an upper opening having an overhang shape by performing development after exposing the intermediate resist film under conditions that allow exposure, and forming the upper opening under conditions that can expose the second lower resist film. A third step of forming a second lower-layer opening having an opening dimension smaller than the upper-layer opening by performing development after exposing an area in the section; Forming a first lower opening having an opening size smaller than that of the second lower opening and reaching the semiconductor substrate surface by performing development after exposing the first lower resist film in the region. A fifth step of depositing a metal material for an electrode on a surface of the semiconductor substrate surface facing the first lower layer opening and on each layer resist film; and dissolving and removing each layer resist film, T
A sixth step of forming a gate electrode having a middle portion having a cross-sectional width smaller than that of the head and larger than that of the leg at a joint between the head and the leg in the cross-sectional shape of the mold. And a seventh step of forming a protective insulating film that covers the gate electrode and the surface of the semiconductor substrate. 2. A method of manufacturing a semiconductor device having a gate electrode having a substantially T-shaped cross section, comprising: forming a lower resist film, an intermediate resist film having a higher sensitivity than the lower resist film on a semiconductor substrate; A first step of sequentially applying and forming an upper resist film having lower sensitivity than the layer resist film, and developing the overhang shape by exposing the upper resist film and the intermediate resist film under conditions capable of exposing the overhang shape. A second step of forming an upper-layer opening having, and performing development after exposing the lower-layer resist film under a condition that a predetermined film thickness remains, thereby forming a concave portion having an opening dimension smaller than the upper-layer opening. A third step of forming, and performing development after exposing a region in the concave portion of the lower resist film to have an opening dimension smaller than the concave portion and extending to the surface of the semiconductor substrate. Fifth depositing a fourth step of forming a lower opening, the electrode metal material on said lower surface facing the opening and each resist film on the semiconductor substrate surface to
By dissolving and removing the resist film of each layer, T
A sixth step of forming a gate electrode having a shape having an intermediate portion having a cross-sectional width smaller than the head and larger than the leg at a joint between the head and the leg in the cross-sectional shape of the mold; And a seventh step of forming a protective insulating film that covers the gate electrode and the surface of the semiconductor substrate.