JPH05152294A - Formation of fine pattern and manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a pattern which is finer than a fine pattern formed on an upper layer by using an upper layer resist which is sensitive to ultraviolet ray and a lower layer resist which is not sensitive thereto. CONSTITUTION:At first, a lower layer resist 2 which is not sensitive to ultraviolet ray is applied to a surface of a substrate 1 and an upper layer resist 3 which enables image inversion and is sensitive to untraviolet ray is applied thereto. An opening 4 of a trapezoid cross section is acquired in the upper layer resist 3 by carrying out image inversion processing. Then, after a metallic film 5 is formed all over the upper layer resist 3 and a metallic film pattern 6 is formed in an exposed surface of the lower layer resist 2, the upper layer resist 3 and the metallic film 5 are fused and removed and the metallic film pattern 6 is made to remain on the lower layer resist 2. Then, the lower layer resist 2 is etched using O2 reactive ion etching method and a pattern 2a of the lower layer resist is formed. The metallic film pattern 6 is removed and a lower resist pattern 2a having a size Lb which is smaller than a size La of the opening 4 of the upper layer resist is acquired.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a fine pattern related to manufacturing a semiconductor device, a method for forming an electrode using such a forming method, and a method for manufacturing a semiconductor device.

[0002]

2. Description of the Related Art In the process of manufacturing semiconductor devices such as individual semiconductor elements and integrated circuits, it is often necessary to form a fine pattern of resist in order to form electrodes and wirings having a desired shape and dimension. A pattern having a dimension of 1 μm or more can be formed relatively easily, but it is quite difficult to form a fine pattern of 0.5 μm or less.

A conventional fine pattern forming method will be described with reference to FIG. 6 by taking a manufacturing process of a junction field effect transistor (JFET) as an example. In the figure, 1 is a semiconductor substrate made of GaAs, 8 is a source electrode formed on the surface of the substrate, 9 is a drain electrode formed on the surface of the substrate at a certain distance from the source electrode 8, and 11 is a substrate. The gate electrode is formed on the surface of, and is provided in the recess 12 formed between the source and drain electrodes. The above structure is the JFE after the electrode formation process is completed.
It is clear from (e) of FIG. 6 showing the main part of T.

The gate electrode 11 has a fine width, for example, about 1.0 μm to 0.5 μm, and an opening having the same size, that is, a fine pattern, must be formed in the resist for forming the gate electrode 11. In the conventional method, in order to manufacture a JFET having such a fine pattern, first, as shown in FIG.
As shown in FIG. 6A, a resist layer 7 is applied on a substrate 1 having a source electrode 8 and a drain electrode 9 formed on its surface, and an optical exposure method or an electron beam exposure method is used to form FIG.
The fine pattern 13 as described above is formed. In this case, the fine pattern 13 is an opening having a width as narrow as the above. Next, the substrate surface is etched through this opening to form an inverted trapezoidal recess 12, a metal layer is vapor-deposited from above the resist layer 7, and the organic solvent is used to vapor-deposit the resist layer 7 and the vapor-deposited layer. By removing the metal layer (lift-off process), the form shown in FIG. 6C is obtained.

In the above fine pattern forming method, when the electron beam exposure method is used, the throughput (the amount of processing per unit time) is low, so that it is not suitable for mass production, and when the optical exposure method is used, Although the throughput is high, it is extremely difficult to form a fine pattern having a size of 0.5 μm or less due to the limit due to the wavelength of ultraviolet light used. Also, if there is a stepped portion on the surface like when forming a mesa on the substrate,
Due to the fact that the thickness of the resist layer formed below and above the step varies and the uniform thickness cannot be obtained over the entire surface, variations occur in the pattern dimensions to be formed. In some cases, the pattern cannot be formed (the opening is formed in the thin portion, but the opening cannot be formed in the thick portion).

Further, the semiconductor device manufacturing method that relies on the above-described fine pattern forming method has a low yield and requires an overlapping operation between electrodes, so that integration and high performance cannot be realized. It contained a problem.

[0007]

The problem to be solved by the present invention is that it is difficult to form a fine pattern having a size of 0.5 μm or less in the above conventional method, and there is a step on the substrate surface. Variation in pattern size and inability to form a fine pattern, low yield in a semiconductor device manufacturing method using a conventional fine pattern forming method, disadvantages requiring overlay, difficulty in integration, and high performance. It is difficult.

[0008]

According to the present invention, a resist layer which is not exposed to ultraviolet rays and a resist layer which is exposed to ultraviolet rays are formed in this order on the surface of a substrate in that order, and the upper layer resist is exposed to ultraviolet rays to obtain a desired layer. Pattern is formed larger than the fine pattern, and a metal film is formed on the residual portion of the upper layer resist and the surface of the lower layer resist exposed in the pattern, and the residual portion of the upper layer resist and the metal film on it are removed. To form a metal pattern on the lower layer resist, etch the lower layer resist using this metal film pattern as a mask, and then remove the metal film pattern to form a lower layer resist pattern smaller than the pattern in the upper layer resist on the substrate. Form on the surface.

Further, the lower layer resist is etched by using the metal film pattern formed as described above as a mask, another resist layer is formed on the entire surface of the substrate, and the other resist layer up to the metal film pattern is removed. By etching and removing the metal film pattern and the underlying resist pattern thereunder, a small-sized blank (meaning a hole) pattern is formed.

[0010]

Since the metal film pattern is formed on the surface of the lower layer resist by utilizing the large pattern formed on the upper layer resist, the lower layer resist is removed from the substrate by etching after removing the upper layer resist and the metal film on it. Etching progresses in the depth direction and in the lateral direction from the periphery of the metal film. Especially, if O ₂ reactive ion etching (O ₂ RIE) is used as an etching method, fine control of gas concentration, voltage and time is performed. Since the etching amount can be precisely controlled by this, a lower resist pattern smaller than the metal film pattern having the same size as the upper resist pattern by a desired amount can be formed.

[0011]

EXAMPLE 1 An example of a fine pattern forming method of the present invention will be described with reference to FIG. In this example, a resist island-shaped fine pattern is formed on the surface of a semiconductor substrate. First, as shown in FIG. 1A, a lower resist 2 which is not exposed to ultraviolet rays is applied to the surface of a substrate 1 made of a semiconductor such as silicon (Si) or gallium arsenide (GaAs), and an image is inverted (on the surface). An upper layer resist 3 capable of image reversal and sensitive to ultraviolet rays is applied. PMGI (polydimethyldimethylglutarimide) or the like is used as the resist material which is not exposed to the ultraviolet rays. As the upper layer resist, a material which is sensitive to ultraviolet rays having a wavelength of 300 nm or more, such as i-line and g-line is used.

Next, by using an appropriate mask, a region other than the pattern to be formed on the surface of the upper resist 3 is exposed to ultraviolet rays and processed by an image reversal method or the like.
That is, for example, by inverting the image of a positive resist, a negative image is obtained. Develop this with normal techniques,
An opening 4 is obtained in the upper layer resist 3. The opening 4 has a trapezoidal cross section due to the image reversal process, and the dimension of the upper side thereof is La ((b) in FIG. 1). As a result, the lower layer resist 2 is exposed in the opening 4, but the lower layer resist is not etched when the upper layer resist 3 is developed, that is, the film thickness is not reduced.

Next, as shown in FIG. 1C, the substrate 1
A metal such as aluminum (Al) or titanium (Ti) is vapor-deposited on the entire surface of the upper layer resist 3, and a metal film 5 is formed on the entire remaining upper layer resist 3 and a metal film pattern 6 is formed on the exposed surface of the lower layer resist 2 in the opening 4. Form. Next, the remaining upper layer resist 3 and the remaining metal film 5 covering the upper portion thereof are completely dissolved and removed (lifted off) with an organic solvent such as acetone that does not act on the lower layer resist 2, and then, as shown in FIG. As shown in, the metal film pattern 6 is left on the lower layer resist 2.

Then, as shown in FIG. 1 (e), O ₂ R
Using IE (O ₂ reactive ion etching method), the lower layer resist 2 is etched using the metal film pattern 6 as a mask to form a lower layer resist pattern 2a. next,
As shown in FIG. 1F, the metal film pattern 6 is removed with hydrochloric acid or the like to obtain a lower layer resist pattern 2a having Lb smaller than the dimension La of the upper layer resist opening 4, and hence the metal film pattern 6.

According to the method of this embodiment, the pattern dimension Lb formed in the lower layer can be made smaller than the pattern dimension La formed in the upper layer of the two upper and lower resists 3, 2 laminated on the substrate 1. Difference in size (La-Lb)
Can be precisely controlled by properly selecting and adjusting O ₂ RIE conditions, that is, gas concentration, accelerating voltage and time, and Lb is 0.5 μm or less, 0.2
A pattern having a dimension of μm can be stably formed.

Further, even if a substrate having a step formed on the surface from the beginning is used, it can be flattened by the lower layer resist 2 of the two layer resist, and the upper layer resist 3 having a uniform thickness is formed. Therefore, the initial pattern dimension La can be stably formed. Since the image inversion method is used to form the opening 4 of the upper layer resist 3, the opening 4
The cross section of can be formed into a trapezoid (overhang type) suitable for lift-off processing, and without generating fluff during lift-off,
The metal film pattern 6 having a clear contour can be stably formed, and accordingly, the pattern 2a having an accurate desired shape and dimension can be obtained.

Embodiment 2 The formation of an inversion pattern of the fine pattern obtained by the method of Embodiment 1 may also be required in the manufacturing process of a semiconductor device. This embodiment relates to such an inversion technique and is described below with reference to FIG. In FIG. 2, the same reference numerals as those in FIG. 1 indicate the same or equivalent components. This also applies to each of the drawings starting from FIG.

First, a substrate having the shape shown in FIG. 1E is prepared by the method of the first embodiment, and then, as shown in FIG.
A resist 7 (for example, PMMA (polymethylmethacrylate) that is not developed with an alkali developing solution is applied to the entire surface (including the metal film pattern 6 and the pattern 2a) to completely resist the metal film pattern 6 and the pattern 2a. 7 is embedded in the metal film pattern 6 by the O ₂ RIE, as shown in FIG.
Remove until exposed. Subsequently, as shown in FIG. 2C, the metal film pattern 6 is removed with hydrochloric acid or the like, and the lower resist pattern 2a is removed with an alkali developing solution to obtain an inverted pattern 2b having a dimension Lb. The reverse pattern is a blank pattern, that is, an opening.

As described above, according to the method of this embodiment, a pattern finer than the pattern dimension La initially formed on the upper layer resist 3 can be inverted, and the reverse pattern of the pattern 2a obtained by the method of the embodiment 1 can be obtained. 2b can be easily formed. Therefore, not only can it be used for integration of a semiconductor device, but also a fine pattern can be stably formed on a substrate having a step.

Example 3 A method of manufacturing a semiconductor device using the fine pattern forming method described in Examples 1 and 2 will be described below. 3A to 3E are views for explaining the manufacturing process,
1 is a substrate of semiconductor such as GaAs, 2a is a lower layer resist pattern, 6 is a metal film pattern, 7 is a resist, 8 is a source electrode, 9 is a drain electrode, 10 is a metal for source / drain electrodes, 11 is a gate electrode, 12 is recess, 14
Is an opening.

First, a substrate of FIG. 1E formed by the method of Example 1 as shown in FIG. 3A is prepared, and a non-alloying metal (not alloyed with the substrate), such as titanium (Ti), is formed on the entire surface. ) / Platinum (Pt) / Gold (Au), etc. are deposited in this order and laminated to form a source electrode 8 and a drain electrode 9 that are in contact with the surface of the substrate 1 and source / drain electrodes on the metal film pattern 6. The metal layer 10 is formed so that the state shown in FIG.

Next, as shown in FIG. 3C, a resist 7 is applied and formed on the entire surface of the substrate to cover the entire surfaces of the source and drain electrodes 8 and 9 and almost all side surfaces of the pattern 2a.
The resist 7 is made of a material that does not dissolve in the PMGI developer and has a thickness of, for example, about 6000 Å.

Next, the metal film pattern 6 and the lower layer resist pattern 2a are removed by hydrochloric acid, a developing solution, etc., and the opening 14 having the dimension Lb of the lower layer resist pattern 2a is formed.
Is opened in the resist 7 to obtain the shape shown in FIG.

Subsequently, as shown in FIG. 3E, the surface of the substrate 1 is etched through the opening 14 using tartaric acid, phosphoric acid or the like to form the recess 12. The width of the recess 12 is larger than Lb due to side etching.
Next, a metal for the gate electrode, such as T, is formed on the entire surface of the substrate 1.
The gate electrode 11 having the gate length Lb is formed by depositing i, Al, Au, etc. and lifting off.

According to this manufacturing method, the gate length can be made fine, the distance between the source and the drain can be shortened, and the gate electrode can be formed by the self-alignment method with respect to the source and drain electrodes. Therefore, high performance and easy integration of the semiconductor device are facilitated.

Example 4 A second example of a method of manufacturing a semiconductor device using the fine pattern forming method shown in Examples 1 and 2 will be described with reference to FIG. First, a substrate similar to that shown in FIG. 1E obtained by the method of Example 1 is prepared (FIG. 4A). Then Example 3
A semi-finished product of FIG. 4B similar to that of FIG. Further, a resist or an insulating film (for example, SiO ₂ ) 15 formed by the ECR-CVD (electron cyclotron resonance CVD) method is formed on the substrate and the source / drain electrodes to a thickness of about 2000 A °, and then, as shown in FIG.
Obtain the shape of (c). This resist or insulating film 15 is
The gap extends between the source / drain electrodes 8 and 9 and the pattern 2a and fills the gap.

Next, the metal film pattern 6 and the lower resist pattern 2a are removed by hydrochloric acid and a developing solution in the same manner as in the third embodiment to form an opening 14 having a size Lb (FIG. 4).
(D)). Subsequently, when the film 15 is a resist, a different type of resist that is not mixed with the resist is selected, and an appropriate resist 7 is applied on this resist or the insulating film 15, and T
An upper mold pattern is formed, and a pattern 16 having a T-shaped cross section as shown in FIG. 4E is formed by exposure and etching.
The pattern 16 is a blank pattern (opening).

Next, the surface of the substrate 1 is etched through the pattern 16 to form the recess 12. The width of the recess 12 is larger than Lb because of the side etching. Then, a metal for a gate electrode is vapor-deposited on the entire surface, and the gate electrode 11 is formed by using lift-off to obtain FIG. 4F. The film 15 is removed at the time of the lift-off in the case of a resist, and remains after the lift-off in the case of an insulating film.
You can leave it as it is.

Example 5 A method, which is a simplified version of the method for manufacturing a semiconductor device shown in Example 4, will be described with reference to FIGS. With this method, the steps up to FIGS. 5A and 5B are the same as the steps of FIGS. 4A and 4B of the fourth embodiment. However, the film thickness of the lower resist pattern 2a is set to about 2000 A °. Next, on this substrate, Si is formed by ECR-CVD.
An insulating film such as O is formed or a film of resist 15 is applied, and so-called cueing treatment is performed up to the upper surface of the source / drain electrode metal 10 to obtain the state of FIG.

For the cueing, if the film 15 is a resist, the entire surface thereof may be subjected to O ₂ RIE treatment and the resist may be removed until the top surface of the source / drain electrode metal 10 is exposed. If the film 15 is an insulating film, planarization and cueing can be easily performed during the ECR-CVD process.

Then, as in the case of the methods of Examples 3 and 4, the source / drain electrode metal 10, the metal film pattern 6, and the lower resist pattern 2a are removed to form a T-shaped relief pattern, that is, an opening 17. 5 (d) having Next, the surface of the substrate 1 is etched through the opening 17 to form the recess 12, the metal for the gate electrode is vapor-deposited, and the film 15 and the metal film on the film 15 are removed by lift-off to remove the T-shaped gate. The electrode 11 is formed, and the structure of FIG.

If the film 15 is an insulating film, it cannot be lifted off. Therefore, after the metal for the gate electrode is vapor-deposited, the metal other than the part to be the T-type gate is removed by ion milling to obtain the desired T. The mold gate electrode 11 can be formed.

[0033]

As described above, according to the method for forming a fine pattern according to the present invention, the optical exposure is performed by using the two-layer resist including the upper layer resist which is exposed to ultraviolet rays and the lower layer resist which is not exposed to ultraviolet rays. There is an effect that a finer pattern than the fine pattern formed on the upper layer resist by the method can be formed easily, with high accuracy, efficiently, and at low cost.

Further, according to the method of manufacturing a semiconductor device using this method of forming a fine pattern, in addition to the fact that the fine pattern can be easily formed with high precision, for example, in the case of a field effect transistor, its gate electrode and Since the source and drain electrodes can be manufactured in a self-aligned manner, not only the performance of the semiconductor device can be improved, but also integration can be facilitated.

[Brief description of drawings]

FIG. 1 is a diagram showing a form of a substrate in each step for explaining an embodiment of a fine pattern forming method of the present invention.

FIG. 2 is a diagram showing the form of the substrate in each step for explaining another embodiment of the fine pattern forming method of the present invention.

FIG. 3 is a diagram showing a product formation state in each step for explaining an embodiment of the semiconductor device manufacturing method of the present invention.

FIG. 4 is a diagram showing a product formation state in each step for explaining another embodiment of the semiconductor device manufacturing method of the present invention.

FIG. 5 is a diagram showing a product formation state in each step for explaining another embodiment of the semiconductor device manufacturing method of the present invention.

FIG. 6 is a diagram illustrating a process sequence of a method of manufacturing a semiconductor device by a conventional fine pattern forming method.

[Explanation of symbols]

 1 semiconductor substrate 2 lower layer resist 3 upper layer resist 4 opening formed in upper layer resist (first pattern) 5 metal film 6 metal film pattern (first pattern) 2a lower layer resist pattern (second pattern) 7 resist 2b reverse pattern 8 source Electrode 9 Drain electrode 11 Gate electrode 12 Recess 13 Opening 14 Opening (opening pattern) 15 Resist or insulating film 16, 17 T-type opening

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI Technical indication location H01L 21/338 29/812 7739-4M H01L 29/80 F

Claims (8)

[Claims] 1. A step of providing, on a substrate, a lower layer resist which is not exposed to ultraviolet rays in contact with the surface of the substrate and an upper layer resist which is exposed to ultraviolet rays and is superposed on the lower layer resist; a predetermined pattern is formed on the upper layer resist. A step of forming a first pattern that exposes the lower resist surface by ultraviolet light exposure and development treatment through a mask that is provided; a metal film is entirely formed on the first pattern portion and the surface of the remaining upper resist layer. And a step of removing the remaining upper layer resist and the metal film deposited thereon by a lift-off process to form a first pattern of the metal film on the surface of the lower layer resist; Etching the lower resist by a desired amount by O ₂ RIE using the first pattern made of the metal film as a mask; removing the pattern of the metal film Exposing a lower layer resist having a second pattern having a smaller size than the first pattern, thereby forming a fine pattern. 2. The method for forming a fine pattern according to claim 1, wherein an image reversal method suitable for a subsequent lift-off process is used in the step of forming the first pattern of the upper layer resist. 3. A step of providing, on a substrate, a lower layer resist which is not exposed to ultraviolet rays in contact with the surface of the substrate and an upper layer resist which is exposed to ultraviolet rays and is superposed on the lower layer resist; a predetermined pattern is formed on the upper layer resist. A step of forming a first pattern that exposes the lower resist surface by ultraviolet light exposure and development treatment through a mask that is provided; a metal film is entirely formed on the first pattern portion and the surface of the remaining upper resist layer. And a step of removing the remaining upper layer resist and the metal film deposited thereon by a lift-off process to form a first pattern of the metal film on the surface of the lower layer resist; A step of etching a desired amount of the lower layer resist by O ₂ RIE using the first pattern made of a metal film as a mask; Is a step of applying a different kind of resist to a thickness such that the first pattern of the metal film is completely buried; and a step of removing the different kind of resist by O ₂ RIE to the depth of the first pattern of the metal film. A step of removing the first pattern and the lower layer resist of the metal film to form an empty pattern having a smaller dimension than the first pattern in the layer of the different type resist; 4. A step of providing, on a substrate, a lower layer resist which is not exposed to ultraviolet rays in contact with the surface of the substrate and an upper layer resist which is exposed to ultraviolet rays and is superposed on the lower layer resist; a predetermined pattern is formed on the upper layer resist. A step of forming a first pattern that exposes the lower resist surface by ultraviolet light exposure and development treatment through a mask that is provided; a metal film is entirely formed on the first pattern portion and the surface of the remaining upper resist layer. And a step of removing the remaining upper layer resist and the metal film deposited thereon by a lift-off process to form a first pattern of the metal film on the surface of the lower layer resist; A step of etching a desired amount of the lower resist by O ₂ RIE using the first pattern made of a metal film as a mask; A step of forming a source electrode and a drain electrode by depositing a metal for a back electrode; a step of applying a resist different from the lower layer resist on the entire surface of the substrate;
A step of removing the first pattern of the metal film and the lower layer resist by a solvent or an etching agent that does not act on the different type resist to form an empty pattern having a size smaller than the first pattern in the different type resist layer; A step of depositing a gate metal on the entire surface of the substrate by using the different type resist as a mask; and removing the gate metal deposition layer and the different type resist other than the blank pattern portion by lift-off to self-align with the source electrode and the drain electrode. A step of forming a gate electrode; and a method of manufacturing a semiconductor device comprising: 5. A step of providing, on a substrate, a lower layer resist which is not exposed to ultraviolet rays in contact with the surface of the substrate and an upper layer resist which is exposed to ultraviolet rays and is superposed on the lower layer resist; a predetermined pattern is formed on the upper layer resist. A step of forming a first pattern that exposes the lower resist surface by ultraviolet light exposure and development treatment through a mask that is provided; a metal film is entirely formed on the first pattern portion and the surface of the remaining upper resist layer. And a step of removing the remaining upper layer resist and the metal film deposited thereon by a lift-off process to form a first pattern of the metal film on the surface of the lower layer resist; A step of etching a desired amount of the lower resist by O ₂ RIE using the first pattern made of a metal film as a mask; A step of forming a source electrode and a drain electrode by depositing a metal for a back electrode; a step of applying a resist different from the lower layer resist on the entire surface of the substrate;
A step of removing the first pattern of the metal film and the lower layer resist by a solvent or an etching agent that does not act on the different type resist to form an empty pattern having a size smaller than the first pattern in the different type resist layer; A step of applying another resist which does not mix with the different type resist on the entire surface of the substrate; a pattern corresponding to the upper side of the T-type gate electrode is exposed and developed at a position aligned with the cut pattern of the other resist layer. Forming by processing;
A method of manufacturing a semiconductor device, comprising: a step of depositing a metal for a gate electrode on the entire surface of a substrate; and a step of removing the another resist and the metal for a gate electrode thereon by lift-off to form a T-type gate. 6. A step of providing, on a substrate, a lower layer resist which is not exposed to ultraviolet rays in contact with the surface of the substrate and an upper layer resist which is exposed to ultraviolet rays and is superposed on the lower layer resist; a predetermined pattern is formed on the upper layer resist. A step of forming a first pattern that exposes the lower resist surface by ultraviolet light exposure and development treatment through a mask that is provided; a metal film is entirely formed on the first pattern portion and the surface of the remaining upper resist layer. And a step of removing the remaining upper layer resist and the metal film deposited thereon by a lift-off process to form a first pattern of the metal film on the surface of the lower layer resist; A step of etching a desired amount of the lower resist by O ₂ RIE using the first pattern made of a metal film as a mask; A step of forming a source electrode and a drain electrode by depositing a metal for a back electrode; a step of forming an insulating film on the entire surface of the substrate by an electron cyclotron resonance CVD method; a first pattern of the metal film and a lower layer resist. A step of removing and forming a punching pattern having a size smaller than the first pattern in the insulating film; forming a pattern corresponding to the upper side of the T-type gate electrode at a position aligned with the punching pattern of the insulating film. And a step of depositing a metal for a gate electrode on the entire surface of the substrate; a step of removing the metal for a gate electrode on the insulating film by lift-off to form a T-type gate. 7. A step of providing, on a substrate, a lower layer resist which is not exposed to ultraviolet rays in contact with the surface of the substrate and an upper layer resist which is exposed to ultraviolet rays and is superposed on the lower layer resist; a predetermined pattern is formed on the upper layer resist. A step of forming a first pattern that exposes the lower resist surface by ultraviolet light exposure and development treatment through a mask that is provided; a metal film is entirely formed on the first pattern portion and the surface of the remaining upper resist layer. And a step of removing the remaining upper layer resist and the metal film deposited thereon by a lift-off process to form a first pattern of the metal film on the surface of the lower layer resist; A step of etching a desired amount of the lower resist by O ₂ RIE using the first pattern made of a metal film as a mask; A step of forming a source electrode and a drain electrode by depositing a metal for a back electrode;
A step of applying a resist different from the lower layer resist to a thickness that covers the non-alloy ohmic electrode metal deposition layer on the first pattern made of the metal film; Removing the metal deposition layer on the first pattern until it is exposed; removing the first pattern made of the metal film and the lower layer resist to form a T-shaped blank pattern in the different resist layer. A step of depositing a metal for a gate electrode on the entire surface of the substrate; a step of removing the different resist and the metal for a gate electrode thereon by a lift-off process to leave the metal for a gate electrode in the T-cut pattern. And a T-type gate electrode forming method. 8. A step of providing a lower layer resist which is not exposed to ultraviolet rays on the substrate in contact with the surface of the substrate, and an upper layer resist which is exposed to ultraviolet rays and is superposed on the lower layer resist; a predetermined pattern is formed on the upper layer resist. A step of forming a first pattern that exposes the lower resist surface by ultraviolet light exposure and development treatment through a mask that is provided; a metal film is entirely formed on the first pattern portion and the surface of the remaining upper resist layer. And a step of removing the remaining upper layer resist and the metal film deposited thereon by a lift-off process to form a first pattern of the metal film on the surface of the lower layer resist; A step of etching a desired amount of the lower resist by O ₂ RIE using the first pattern made of a metal film as a mask; A step of forming a source electrode and a drain electrode by depositing a metal for a back electrode; and a deposition layer of a metal for a non-alloy ohmic electrode on the first pattern made of the metal film is buried by an electron cyclotron resonance CVD method. Forming an insulating film over the entire surface of the substrate to a thickness;
Removing the surface of the insulating film up to the metal deposition layer on the first pattern made of the metal film; removing the first pattern made of the metal film and the lower resist to form a T-type film in the insulating film. A step of forming a punching pattern; a step of depositing a metal for a gate electrode on the entire surface of the substrate; a metal on the insulating film is removed by a lift-off process to leave the metal for a gate electrode in the T-shaped punching pattern. And a step of forming a T-type gate electrode.