JPH09127707A - Formation of resist pattern - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method capable of decreasing photolithographic stages. SOLUTION: A positive type resist 26 is applied on laminated films of a semiconductor layer 24 and a channel protective film 25 and is subjected to first exposure of small exposure energy by using a first photomask 27. Next, the resist is subjected to second exposure of large exposure energy using a second photomask 28. The integral formation of the two patterns varying in size is possible. The parts of the resist patterns where width is large are removed by a plasma treatment, by which the use of the two patterns as the mask for etching is possible. The photolithographic stages are, therefore, decreased and the productivity is enhanced.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a method for forming a resist pattern. The present invention can be used in the field of manufacturing semiconductor devices such as thin film transistors and liquid crystal display devices.

[0002]

2. Description of the Related Art Generally, various semiconductor manufacturing techniques such as etching technique and ion implantation technique use a resist pattern formed by photolithography technique.
It is assumed. The range of this photolithography technique is generally from resist coating to exposure and development. Such a resist pattern forming technique is used, for example, when manufacturing a thin film transistor (TFT) as shown in FIGS.

A conventional method of forming a resist pattern used for manufacturing a TFT will be described below with reference to the drawings.

The process shown in FIGS. 9A and 9B is performed by T
It shows a step of forming a resist pattern used for patterning the blocking layer that protects the channel of the FT. In the figure, 1 is a glass substrate on which a gate electrode 2 is patterned. A gate insulating film 3 made of, for example, silicon nitride is deposited on the gate electrode 2 and the glass substrate 1. Further, on the gate insulating film 3, a semiconductor layer 4 made of, for example, amorphous silicon, and an insulating film 5 serving as the blocking layer described above are sequentially deposited. Then, as shown in FIG.
After applying a positive resist 6 on the insulating film 5, a photomask 7 corresponding to the blocking layer is arranged and exposure is performed. At this time, the portion hidden by the photomask 7 becomes the unexposed portion 6A, and the exposed portion becomes the exposed portion 6B. Then, by developing the positive resist 6, a resist pattern 6P as shown in FIG. 9B can be formed.

Thereafter, as shown in FIG. 10A, a blocking layer 5A is formed by anisotropic dry etching of the insulating film 5 using the resist pattern 6P as a mask.
After that, as shown in FIG. 10B, the resist pattern 6P is peeled off.

Next, after performing pretreatment on the substrate, as shown in FIG.
As shown in (A), the positive resist 8 is applied again,
A photomask 9 having a width wider than that of the above-described photomask 7 is arranged and exposure is performed. At this time, the portion hidden by the photomask 9 becomes the unexposed portion 8A, and the exposed portion becomes the exposed portion 8B. After that, as shown in FIG. 11B, the positive resist 8 is developed to form a resist pattern 8P corresponding to the unexposed portion 8A, and the resist pattern 8P is used as a mask to form a different pattern on the semiconductor layer 4. Perform anisotropic dry etching. As a result, as shown in FIG. 12A, it is possible to process the semiconductor layer 4A having a predetermined width which constitutes the TFT, and obtain a structure having the blocking layer 5A at the center of the upper surface of the semiconductor layer 4A. FIG.
(B) shows an ohmic film 10 having an N-type impurity introduced therein and a source / drain electrode 1 for such a structure.
1 and 1 are formed. When patterning the ohmic film 10 and the source / drain electrodes 11, the blocking layer 5A has a function of protecting the semiconductor layer 4A (channel region) from an etchant.

[0007]

However, in the fabrication of the conventional TFT described above, at least two photolithography steps have been performed in order to form the semiconductor layer 4A and the blocking layer 5A. Such TFT
In the manufacturing method, as described above, steps such as film formation of various films, pretreatment of resist coating, resist patterning, etching, resist peeling, heat treatment such as soft baking of resist, and various cleaning steps are repeated. By doing so, the final device structure (staggered type, inverted staggered type, coplanar type, inverted coplanar type, etc.) is obtained. In such a series of steps, the smaller the number of patterning steps, the shorter the TFT process can be realized, which leads to improvement in production and yield. In the above-mentioned conventional process, one material film can be processed by one resist pattern, and the number of patterns is one. For this reason, it has been difficult to reduce the number of resist pattern forming steps by the photolithography technique more than necessary.

An object of the present invention is to provide a method for forming a resist pattern which enables reduction of the photolithography process involved in manufacturing a semiconductor device.

[0009]

According to a first aspect of the present invention, in a method of forming a resist pattern, a step of forming a resist on a substrate, and a step of exposing only an upper portion of an area excluding the first area of the resist. 1 exposure step and the first
A second exposure step which is performed before or after the exposure step and exposes an area other than the first area and a second area adjacent to the first area; and the first exposure step and the second exposure step. And a developing step of forming an island-shaped first resist pattern on the base and a second resist pattern narrower than the first resist pattern on the first resist pattern, and the first resist pattern. And an etching step of etching the second resist pattern to form a third resist pattern which is at least a part of the second resist pattern.

According to the first aspect of the present invention, after the resist is formed on the substrate, the first exposure step and the second exposure step are performed, and the second resist pattern narrower than the first resist pattern is formed on the first resist pattern. To form these first
When these are etched without a mask, the second resist pattern has a portion overlapping with the first resist pattern. Therefore, the first resist pattern portion not overlapping with the second resist pattern is removed. However, it is possible to leave the third resist pattern formed of at least a part of the second resist pattern, and to use a pattern having a size different from that of the first resist pattern as the second mask. Thus, resist patterns having different widths can be simultaneously formed in one development step, and the throughput of resist pattern formation can be improved.

In the first exposure step of exposing only the upper part of the resist except the first area, the resist is exposed to light having an energy smaller than the exposure energy of the second exposure step or the exposure time is set to the second exposure step. The exposure time may be shortened, a resist having low photosensitivity may be provided, or the resist film may be thickened so that only the upper part is sufficiently exposed. Further, the resist may have a two-layer structure in which the upper layer is a highly sensitive resist and the lower layer is a less sensitive resist than the upper layer. In this case, the low-photosensitive resist may be provided with a dye that adjusts the light transmittance.

According to a second aspect of the present invention, the resist is a positive type resist, and the etching step is a plasma etching step.

According to a third aspect of the present invention, the base comprises a semiconductor layer and an insulating layer of a thin film transistor, and a first patterning step of patterning the semiconductor layer and the insulating layer using the second resist pattern as a mask, and the first patterning step. And a second patterning step of patterning the insulating layer using the three resist patterns as a mask.

According to a fourth aspect of the invention, at least the step of injecting impurities into the semiconductor layer and the step of forming an impurity layer on the semiconductor layer using the third resist pattern or the patterned insulating layer as a mask. It is characterized by having one step.

In the invention described in claim 3, the semiconductor layer can be patterned in an island shape, and the insulating layer can be patterned in a width different from that of the island-shaped semiconductor layer. In the invention described in claim 4, in the invention described in claim 4, Impurity regions can be formed on or in the semiconductor layer using the resist pattern or the patterned insulating layer as a mask.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a method for forming a resist pattern according to the present invention will be described below with reference to the drawings. (Embodiment 1) FIGS. 1 to 3 are process sectional views showing Embodiment 1 of the present invention. The present embodiment is an example in which the present invention is applied to manufacture of a thin film transistor having an inverted stagger type structure, and the present embodiment can be used particularly in manufacture of a liquid crystal display element.

First, in this embodiment, as shown in FIG. 1A, a gate electrode 22 made of, for example, aluminum is patterned on a glass substrate 21. After that, a gate insulating film 23 made of silicon nitride is deposited on the gate electrode 22 and the glass substrate 21. Next, the gate insulating film 2
3, a semiconductor layer 24 made of amorphous silicon,
A channel protection film 25 made of silicon dioxide is sequentially deposited. Then, as shown in FIG.
A positive type resist 26 is spin-coated on top of the above so as to have a relatively large thickness (for example, a film thickness of 3.0 μm). As the positive resist 26, for example, a phenol resin as an alkali-soluble polymer compound and an o
-Use a mixture of naphthoquinone diazides.

Next, as shown in FIG. 1A, a first photomask 27 is arranged and a first exposure is performed. At this time, the glass substrate 21 side is first above the gate electrode 22.
It is set so that the light-shielding portion of the photomask 27 is positioned. The width dimension of the light shielding portion of the first photomask 27 is set to the width dimension of the blocking layer to be formed on the semiconductor layer 24. The exposure amount of the first exposure is
Lower than normal exposure energy (eg about 50 mJ / c
m ² ) It is set. Note that these exposure conditions can be appropriately changed according to the characteristics of the positive resist. First
As a result of the exposure, as shown in FIG. 1A, in the positive resist 26, the portion hidden (shadowed) by the first photomask 27 becomes an unexposed portion 26a, and the portion irradiated with light is It becomes the photosensitive section 26b. The photosensitive portion 26b is formed only in the upper half portion of the positive resist 26 in the thickness direction due to the above conditions.

Subsequently, as shown in FIG. 1B, the first photomask 27 is replaced with a second photomask 28, and a second exposure is performed. The second photomask 28 corresponds to the pattern of the semiconductor layer of the thin film transistor to be formed, and has a light shielding portion pattern wider than the first photomask 27. Then, the exposure amount of the second exposure is
Greater than the exposure energy of the first exposure (eg 100
mJ / cm ² ) is set. The exposure time of the second exposure may be set longer than the exposure time of the first exposure. As a result of this second exposure, as shown in FIG. 1B, the photosensitive portion 26 that is exposed over the entire thickness direction to the positive resist 26 in the portion not hidden by the second photomask 28.
c is formed. During this second exposure, the photosensitive portion 26b formed immediately after the first exposure, which is located immediately below the second photomask 28, naturally holds that state.

Next, the positive resist 26 is developed.
By this development, the positive type resist 26 is formed as shown in FIG.
As shown in FIG. 5, the first pattern 26A having a narrow width in which the unexposed portion 26a remains, and the unexposed portion 26a and the exposed portion 26
A resist pattern 26 integrally formed with a wide second pattern 26B in which an unexposed portion immediately below b remains.
P can be created.

Using the resist pattern 26P as a mask, the channel protection film 25 and the semiconductor layer 2 which are the bases are formed.
4 is continuously anisotropically etched. In addition, as the anisotropic etching, the channel protective film (SiO ₂ ) 25
Is used as an etching gas, for example, CF ₄ −
Dry etching using H ₂ system gas is performed, and for etching the semiconductor layer 24, for example, CF is used as an etching gas.
Dry etching is performed using a _4- O ₂ system gas. In addition,
In the etching of the semiconductor layer 24, by using the above-mentioned gas system, the etching selection ratio with the gate insulating film (SiN) 23 which is the base of the semiconductor layer 24 can be obtained. In addition, these etchings can be continuously performed under in-site conditions by using a multi-chamber process device. Note that FIG. 2A shows a state where the semiconductor layer 24 is being etched.

After the channel protective film 25 and the semiconductor layer 24 are thus etched, the resist pattern 26P is subjected to oxygen plasma treatment. When the oxygen plasma treatment is performed, as shown in FIG.
6P retreats downward (indicated by an arrow in the figure) from the state indicated by the broken line, and when the second pattern 26B disappears, the third point
The pattern 26C is formed. This third pattern 26C
Has the pattern shape and pattern dimensions of the first pattern 26A transferred, and the second pattern is substantially removed by removing the second pattern from the resist pattern 26P.
Only left. Although a thin oxide film is formed on the exposed portion (side wall portion) of the semiconductor layer 24 by this oxygen plasma treatment, it does not affect the characteristics of the thin film transistor to be formed. By the way, when such an oxygen plasma treatment is performed, charge-up may occur due to the influence of charged particles in the plasma, and for example, inconvenience such as breakdown voltage deterioration of the gate insulating film may occur. It is possible to prevent the occurrence of inconvenience by taking If the resist ashing has a film thickness of about this embodiment, charge-up does not occur and the breakdown voltage of the gate insulating film does not deteriorate. Furthermore, by using a plasma generator having a high uniformity of plasma density, it is possible to further avoid the occurrence of charge-up.

Next, as shown in FIG. 3A, the channel protection film 25 is etched by using the third pattern 26C as a mask to pattern the channel protection layer 25A. For this etching, a gas system such as C ₂ F ₆ , C ₃ F ₈ or C ₄ F ₈ is used in order to obtain a selection ratio between the underlying amorphous silicon and the gate insulating film (SiN) 23. Perform dry etching.

After that, the third pattern 26C is peeled off.
Here, after forming the resist pattern 26, the resist peeling process is performed for the first time after the semiconductor layer 24 and the channel protective layer 25A are patterned. Next, as shown in FIG. 3B, the ohmic film 29 and the source / drain electrodes 3 are formed.
After the formation process of 0, the manufacturing of the inverted stagger type thin film transistor is completed.

By forming the resist pattern as described above, in this embodiment, the patterning of the semiconductor layer 24 and the patterning of the channel protective layer 25A are performed in one step.
The resist pattern formed by one photolithography process was used. Therefore, steps associated with photolithography, such as a pretreatment step, a resist coating step, a soft bake (prebake) step, a photomask alignment step, an exposure step, a development step, a rinse cleaning step, a hard bake (post bake) step, etc. The number of steps can be significantly reduced.

(Embodiment 2) FIGS. 4 to 6 are process sectional views showing Embodiment 2 of the present invention. The present embodiment also applies the present invention to the manufacture of an inverted staggered thin film transistor, but the present embodiment is characterized in that the positive resist is formed in two layers. In the description of the present embodiment, the same parts as those in the first embodiment described above are designated by the same reference numerals and the description thereof will be omitted.

In this embodiment, the gate electrode 22, the gate insulating film 23, and the semiconductor layer 2 are formed on the glass substrate 21.
4. Until the formation of the channel protective film 25, the process is the same as in the above-described first embodiment. Next, on the channel protective film 25,
A positive resist 31 having low photosensitivity is applied. afterwards,
On top of that, a positive resist 32 having high photosensitivity is applied so as not to mix with the positive resist 31. In the present embodiment, the same material is used as the material for the upper and lower layers of resist, and an appropriate amount of dye is mixed only in the lower layer of resist in order to adjust the light transmittance to a low level. Therefore, the photosensitivity of the lower positive resist 31 is lower than that of the upper positive resist 32.

Next, using the same first photomask 27 as in the first embodiment, a first exposure is performed with a predetermined exposure amount. As a result, as shown in FIG. 4A, the portion of the positive resist 32 that is hidden by the first photomask 27 (the portion that is shaded) becomes the unexposed portion 32 a, and the portion that is not hidden by the first photomask 27. The (non-shadowed portion) is exposed and becomes the photosensitive portion 32b. At this time, the lower positive resist 31 is not exposed.

Subsequently, the first photomask 27 is replaced with the second photomask 28, and second exposure is performed. The second exposure is performed by setting the exposure energy larger than that of the first exposure. As a result, as shown in FIG. 4B, the exposed portions become the photosensitive portions 32c and 31b. The unexposed portion of the lower positive-working resist 31 is not exposed.
1a.

Next, by performing development, as shown in FIG.
A resist pattern 33 as shown in is formed. The resist pattern 33 includes a first pattern 33A in which the unexposed portion 32a of the positive resist 32 in the upper layer remains, and a second pattern 33B in which the unexposed portion 31a of the positive resist 31 in the lower layer remains. Are integrally formed.

Then, using the resist pattern 33 as a mask, the channel protection film 25 and the semiconductor layer 24 are anisotropically etched as in the first embodiment. As a result, the semiconductor layer of the thin film transistor to be manufactured can be patterned. Further, as shown in FIG. 5B, by subjecting the resist pattern 33 to oxygen plasma treatment in the same manner as in the first embodiment, a third pattern 33C having the same planar shape and the same size as the first pattern 33A can be formed. .

Then, as shown in FIG.
The channel protection film 25 is etched using the pattern 33C as a mask. As a result, it is possible to form the pattern of the channel protection layer 25A that protects the channel region of the semiconductor layer 24. Then, the third pattern 33C is peeled off, the ohmic film 29 and the source / drain electrodes 30 are formed as in the first embodiment, and the manufacturing of the thin film transistor as shown in FIG. 6B is completed.

Although the first and second embodiments have been described above, the present invention is not limited to these, and various changes accompanying the gist of the configuration can be made. For example, in Embodiments 1 and 2 described above, the present invention is applied to manufacture of an inverted stagger type thin film transistor, but FIG.
As shown in FIG. 7A, the exposed portion of the semiconductor layer 24 is doped with impurity ions 34 containing phosphorus (P) using the third pattern or the channel protection layer 25A as a mask, and FIG.
As shown in FIG. 3, the impurity regions 24a may be formed at both ends of the channel region 24b of the semiconductor layer 24, or the resist pattern in which the first pattern and the second pattern are integrally formed is formed in the LDD structure of the MOS transistor. It is also possible to apply to formation. In this case, the thin portion of the second pattern has a function of adjusting the concentration of ions introduced into the base semiconductor layer during ion implantation.

In the first embodiment, the first exposure time is set shorter than the first exposure time, and the exposure energy is set to be different, but only the exposure energy or only the exposure time is set as a parameter. You can do it.

Furthermore, in the second embodiment, the sensitivity of the resist is set low by mixing the dye in the lower layer positive type resist 31, but the upper and lower layer resists are preliminarily high sensitivity type and low sensitivity type. It is of course possible to prepare the above types and to not mix the dye in the resist in the lower layer.

Furthermore, in the above-described first and second embodiments, oxygen plasma treatment is performed as a method of removing the second pattern, but other plasma treatment, wet treatment, or the like can be performed.

In the first and second embodiments, after the first exposure using the first photomask 27 as a mask, the second exposure is performed using the second photomask 28 wider than the first photomask as a mask. However, not limited to this, FIG.
As shown in (A), the second exposure is performed by using the photomask 35 that matches the patterning of the semiconductor layer 24 as a mask, and the unexposed portion 36 a and the exposed portion 3 are formed on the positive resist 36.
After forming 6b, the first exposure is performed using the photomask 37 narrower than the photomask 35 as a mask to expose the upper portion of the unexposed portion 36a in the region where the photomask 35 and the photomask 37 do not overlap. The photosensitive portion 36c may be formed and the remaining non-photosensitive portion 36d may be provided.

The third pattern may be made wider or narrower than the first pattern by etching depending on the setting of the channel region of the semiconductor layer. Therefore, since the width of the channel region, that is, the so-called channel length can be set as appropriate, the present invention can be applied to a thin film transistor having an offset structure.

[0039]

As is apparent from the above description, according to the present invention, it is possible to realize a plurality of pattern processes in one photolithography process. Also,
According to the present invention, there is an effect that it is easy to set the implantation amount to be different depending on the region by one-time ion implantation. Therefore, according to the present invention, the effect of improving the productivity of various semiconductor devices and liquid crystal display devices can be obtained.

[Brief description of the drawings]

1A and 1B are process cross-sectional views of a first embodiment of the present invention.

2A and 2B are process sectional views of Embodiment 1 of the present invention.

3A and 3B are process sectional views of Embodiment 1 of the present invention.

4A and 4B are process sectional views of Embodiment 2 of the present invention.

5A and 5B are process sectional views of Embodiment 2 of the present invention.

6A and 6B are process sectional views of Embodiment 2 of the present invention.

7A and 7B are cross-sectional views of the ion implantation process.

8A and 8B are sectional views of the exposure process.

9A and 9B are process cross-sectional views of a conventional example.

10A and 10B are process cross-sectional views of a conventional example.

11A and 11B are process cross-sectional views of a conventional example.

12A and 12B are process cross-sectional views of a conventional example.

[Explanation of symbols]

 24 semiconductor layer 25 channel protective film 25A channel protective layer 26 positive resist 26a unexposed part 26b exposed part 26A first pattern 26B second pattern 26C third pattern 26P resist pattern 27 first photomask 28 second photomask

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical display location H01L 21/336

Claims (4)

[Claims] 1. A process of forming a resist on a substrate, a first exposure process of exposing only an upper portion of a region of the resist excluding a first region, and one of before and after the first exposure process, After performing a second exposure step of exposing a region other than the first region and a second region adjacent to the first region, the first exposure process and the second exposure process, island-shaped patterns are formed on the substrate. A first resist pattern, a developing step of forming a second resist pattern having a width narrower than the first resist pattern on the first resist pattern, and etching the first resist pattern and the second resist pattern,
A method of forming a resist pattern, comprising an etching step of forming a third resist pattern which is composed of at least a part of the second resist pattern. 2. The resist is a positive type resist,
The method of forming a resist pattern according to claim 1, wherein the etching step is a step of plasma etching. 3. The substrate comprises a semiconductor layer and an insulating layer of a thin film transistor, a first patterning step of patterning the semiconductor layer and the insulating layer with the second resist pattern as a mask, and a third pattern of the resist with the third resist pattern as a mask. The resist pattern forming method according to claim 1, further comprising a second patterning step of patterning the insulating layer. 4. The method comprises at least one of a step of implanting an impurity into the semiconductor layer and a step of forming an impurity layer on the semiconductor layer by using the third resist pattern or the patterned insulating layer as a mask. The method of forming a resist pattern according to claim 3, wherein