KR100300862B1 - Method for fabricating tft - Google Patents
Method for fabricating tft Download PDFInfo
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- KR100300862B1 KR100300862B1 KR1019940017024A KR19940017024A KR100300862B1 KR 100300862 B1 KR100300862 B1 KR 100300862B1 KR 1019940017024 A KR1019940017024 A KR 1019940017024A KR 19940017024 A KR19940017024 A KR 19940017024A KR 100300862 B1 KR100300862 B1 KR 100300862B1
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- gate
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- polysilicon
- layer
- polysilicon film
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- 238000000034 method Methods 0.000 title claims abstract description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 58
- 229920005591 polysilicon Polymers 0.000 claims abstract description 58
- 239000010409 thin film Substances 0.000 claims abstract description 28
- 125000006850 spacer group Chemical group 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000000151 deposition Methods 0.000 claims abstract description 3
- 239000010408 film Substances 0.000 claims description 71
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 238000000059 patterning Methods 0.000 claims description 5
- 238000005468 ion implantation Methods 0.000 abstract description 5
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 4
- 230000004888 barrier function Effects 0.000 abstract description 2
- 239000012535 impurity Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
제1(a)도 내지 제1(c)도는 본 발명의 일실시예에 따른 박막트랜지스터 제조 공정도.1 (a) to 1 (c) is a process chart for manufacturing a thin film transistor according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 절연막 2 : 게이트용 폴리실리콘막1 insulating film 2 polysilicon film for gate
3 : 두꺼운 산화막 4 : 감광막3: thick oxide film 4: photosensitive film
5 : 불순물이 주입된 폴리실리콘막 스페이서 6 : 게이트 산화막5 polysilicon film spacer implanted with impurities 6 gate oxide film
7 : 채널용 폴리실리콘막7: polysilicon film for channel
본 발명은 바텀(bottom) 게이트형 박막트랜지스터 및 그 제조방법에 관한 것이다.The present invention relates to a bottom gate type thin film transistor and a method of manufacturing the same.
잘 알려진 바와 같이, SRAM 셀의 로드 소자 등으로 박막트랜지스터가 사용되고 있으며, 바텀 게이트형 박막트랜지스터 제조 방법은 박막트랜지스터의 게이트 폴리실리콘막 증착 및 패터닝을 실시한 이후 게이트 산화막을 형성하고 채널 폴리실리콘막을 증착한 다음에 박막트랜지스터의 특성이 오프 전류를 감소시키기 위하여 소오스/드레인의 오프셋(offset)이 적용된 이온주입을 실시하고 있다.As is well known, a thin film transistor is used as a load element of an SRAM cell, and in the bottom gate type thin film transistor manufacturing method, after a gate polysilicon film deposition and patterning of a thin film transistor is performed, a gate oxide film is formed and a channel polysilicon film is deposited. Next, in order to reduce the off current due to the characteristics of the thin film transistor, ion implantation to which an offset of a source / drain is applied is performed.
그러나, 이러한 방법으로는 박막트랜지스터의 오프 전류(off current) 감소에 따른 특성 향상에 제한이 있는 실정이며, 공정시 채널 폴리실리콘막을 패터닝할 때 하부층인 게이트 산화막이 얇은 관계로 게이트 산화막 하부층인 게이트 폴리실리콘막의 손상을 유발하며, 채널 폴리실리콘막 식각시 잔유물에 의한 채널 폴리실리콘막과의 브리지(bridge)가 발생되는 문제점이 있었다.However, such a method has a limitation in improving characteristics due to a decrease in off current of the thin film transistor, and in the process of patterning the channel polysilicon film, the gate oxide film, which is a lower layer, is thin when the channel polysilicon film is patterned. It causes damage to the silicon film, and there is a problem in that a bridge (bridge) with the channel polysilicon film due to the residue during the channel polysilicon film etching.
본 발명은 상술한 바와 같은 종래기술의 문제점을 해결하기 위하여 안출된 것으로서, 오프 전류를 감소시켜 박막트랜지스터의 특성을 향상시킬 수 있는 박막트랜지스터 및 그 제조방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the problems of the prior art as described above, it is an object of the present invention to provide a thin film transistor and a method for manufacturing the thin film transistor which can improve the characteristics of the thin film transistor by reducing the off current.
또한 본 발명은 채널 폴리실리콘막 식각시의 문제점을 해결할 수 있는 박막트랜지스터 및 그 제조방법을 제공하는데 다른 목적을 갖는다.In addition, the present invention has another object to provide a thin film transistor and a method for manufacturing the same that can solve the problem of etching a channel polysilicon film.
상기 목적을 달성하기 위한 본 발명의 박막트랜지스터는, 기판 상에 형성된 게이트용 폴리실리콘막; 상기 게이트용 폴리실리콘막 상에 형성되며, 상기 게이트용 폴리실리콘막의 소정부위를 노출시키는 오픈부를 갖는 절연막패턴; 상기 오픈내의 상기 절연막패턴 측벽과 상기 게이트용 폴리실리실리콘막 가장자리에 형성된 도핑된 폴리실리콘막 스페이서; 상기 오픈부 내의 상기 도핑된 폴리실리콘막 스페이서와 상기 게이트용 폴리실리콘막 표면상에서부터 상기 오픈부 밖의 상기 절연막패턴 표면으로 확장되어 형성된 게이트산화막; 및 상기 게이트산화막과 오버랩되어 형성된 채널용 폴리실리콘막을 포함하여 이루어진다.The thin film transistor of the present invention for achieving the above object is a gate polysilicon film formed on a substrate; An insulating film pattern formed on the gate polysilicon film and having an open portion exposing a predetermined portion of the gate polysilicon film; A doped polysilicon layer spacer formed at an edge of the insulating film pattern sidewall in the opening and an edge of the polysilicon layer for gate; A gate oxide film extending from the doped polysilicon film spacer in the open portion and the gate polysilicon film surface to the surface of the insulating film pattern outside the open portion; And a polysilicon film for channel formed to overlap with the gate oxide film.
또한 본 발명의 박막트랜지스터 제조방법은 기판 상에 게이트용 폴리실리콘막을 형성하는 제1단계; 상기 게이트용 폴리실리콘막 상에 상기 게이트용 폴리실리콘막의 소정부위를 노출시키는 절연막패턴을 형성하는 제2단계; 상기 절연막패턴 측벽과 상기 노출된 게이트용 폴리실리콘막의 가장자리에 도핑된 폴리실리콘막 스페이서를 형성하는 제3단계; 상기 제3단계가 완료된 결과물 전면에 박막트랜지스터의 게이트 산화막을 형성하는 제4단계; 상기 게이트 산화막상에 채널용 폴리실리콘막을 형성하는 제5단계; 및 상기 채널용 폴리실리콘막과 상기 게이트 산화막을 식각하여 패터닝하는 제6단계를 포함하여 이루어진다.In addition, the method of manufacturing a thin film transistor of the present invention comprises a first step of forming a polysilicon film for a gate on a substrate; Forming an insulating layer pattern on the gate polysilicon film to expose a predetermined portion of the gate polysilicon film; Forming a doped polysilicon layer spacer on sidewalls of the insulating layer pattern and the edge of the exposed polysilicon layer for gate; A fourth step of forming a gate oxide layer of a thin film transistor on the entire surface of the resultant of the third step; A fifth step of forming a polysilicon film for a channel on the gate oxide film; And a sixth step of etching and patterning the channel polysilicon layer and the gate oxide layer.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.
첨부된 도면 제1(a)도 내지 제1(c)도는 본 발명의 일실시예에 따른 박막트랜지스터 제조 공정도이다.1 (a) to 1 (c) of the accompanying drawings are a process chart of manufacturing a thin film transistor according to an embodiment of the present invention.
먼저, 제1(a)도를 참조하면, 절연막(1)이 기 형성된 기판 상에 박막트랜지스터의 게이트용 폴리실리콘막(2) 및 두꺼운 산화막(3)을 차례로 형성한 후 박막트랜지스터의 게이트 마스크 작업으로 감광막(4) 패턴을 형성하고, 상기 감광막(4) 패턴을 식각 장벽으로 하여 산화막(3)을 식각한다. 이에 의해 박막트랜지스터의 게이트 부위가 오픈된 산화막패턴이 형성된다.First, referring to FIG. 1A, a gate polysilicon film 2 and a thick oxide film 3 of a thin film transistor are sequentially formed on a substrate on which an insulating film 1 is formed, and then a gate mask operation of the thin film transistor is performed. The photosensitive film 4 pattern is formed, and the oxide film 3 is etched using the photosensitive film 4 pattern as an etching barrier. As a result, an oxide layer pattern in which the gate portion of the thin film transistor is opened is formed.
이어서, 제1(b)도를 참조하면, 상기 감광막(4)을 제거하고 불순물이 주입된 폴리실리콘막을 증착한 후 다시 전면식각(blanket etch)하여 상기 산화막(3)의 오픈부위 측벽에 불순물이 주입된 폴리실리콘막 스페이서(5)를 형성한 다음에 전체구조 상부에 박막트랜지스터의 게이트용 산화막(6)을 형성한다.Subsequently, referring to FIG. 1 (b), the photoresist film 4 is removed, a polysilicon film into which impurities are injected is deposited, and the surface is etched again, followed by blanket etch to remove impurities from the open sidewall of the oxide film 3. After the implanted polysilicon film spacer 5 is formed, the gate oxide film 6 for the thin film transistor is formed on the entire structure.
계속해서, 제1(c)도에 도시된 바와 같이 게이트용 산화막(6)상에 채널용 폴리실리콘막(7)을 형성한 후 패터닝하고, 박막트랜지스터 관련 이온주입을 실시한다.Subsequently, as shown in FIG. 1 (c), the channel polysilicon film 7 is formed on the gate oxide film 6, and then patterned, and ion implantation associated with the thin film transistor is performed.
도면에서, 불순물이 주입된 폴리실리콘막 스페이서(5)는 박막트랜지스터의 게이트 폴리실리콘막(2)에 0볼트를 인가할시 오프셋의 역할을 하며, 박막트랜지스터의 게이트 폴리실리콘막(2)에 3.3볼트를 인가할시 박막트랜지스터의 채널로 작용한다. 때문에, 오프셋 영역 형성을 위한 별도의 마스크 작업 및 이온주입 공정은 필요 없다.In the drawing, the impurity-injected polysilicon film spacer 5 serves as an offset when 0 volts is applied to the gate polysilicon film 2 of the thin film transistor, and 3.3 is applied to the gate polysilicon film 2 of the thin film transistor. When a bolt is applied, it acts as a channel of the thin film transistor. Therefore, a separate mask operation and ion implantation process for forming the offset region is not necessary.
이상, 상기 설명과 같이 이루어지는 본 발명은 오프셋 영역 형성을 위한 별도의 마스크 작업 및 이온주입 공정은 생략 할 수 있어, 웨이퍼 대 웨이퍼의 오프셋 길이 균일도를 향상시키며, 또한 박막트랜지스터 특성에 관련된 오프 전류의 감소를 가져온다.As described above, according to the present invention, a separate mask operation and ion implantation process for forming an offset region can be omitted, thereby improving wafer-to-wafer offset length uniformity and reducing off current related to thin film transistor characteristics. Bring it.
또한, 채널 폴리실리콘막을 패터닝을 위한 식각시 하부층이 두꺼운 산화막(3)이기 때문에 게이트 폴리실리콘막(2)의 손상을 유발하는 것을 방지하며, 스트링거에 의한 채널 폴리실리콘막과 게이트 폴리실리콘막 사이의 브리지를 방지하는 효과가 있다.In addition, when the channel polysilicon film is etched for patterning, the lower layer is a thick oxide film 3, thereby preventing damage to the gate polysilicon film 2, and between the channel polysilicon film and the gate polysilicon film by a stringer. It has the effect of preventing bridges.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940017024A KR100300862B1 (en) | 1994-07-14 | 1994-07-14 | Method for fabricating tft |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940017024A KR100300862B1 (en) | 1994-07-14 | 1994-07-14 | Method for fabricating tft |
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| Publication Number | Publication Date |
|---|---|
| KR960006078A KR960006078A (en) | 1996-02-23 |
| KR100300862B1 true KR100300862B1 (en) | 2001-12-15 |
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| KR1019940017024A KR100300862B1 (en) | 1994-07-14 | 1994-07-14 | Method for fabricating tft |
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| KR100903455B1 (en) * | 2007-08-27 | 2009-06-18 | 주식회사 동부하이텍 | Manufacturing Method of Semiconductor Device |
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1994
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