KR0171976B1 - Method of producing thin film transistor - Google Patents
Method of producing thin film transistor Download PDFInfo
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- KR0171976B1 KR0171976B1 KR1019950006370A KR19950006370A KR0171976B1 KR 0171976 B1 KR0171976 B1 KR 0171976B1 KR 1019950006370 A KR1019950006370 A KR 1019950006370A KR 19950006370 A KR19950006370 A KR 19950006370A KR 0171976 B1 KR0171976 B1 KR 0171976B1
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- South Korea
- Prior art keywords
- source
- drain
- nitride film
- photoresist
- polysilicon
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- 238000000034 method Methods 0.000 title claims abstract description 16
- 239000010409 thin film Substances 0.000 title claims abstract description 16
- 239000010408 film Substances 0.000 claims abstract description 33
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 33
- 229920005591 polysilicon Polymers 0.000 claims abstract description 33
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 31
- 150000004767 nitrides Chemical class 0.000 claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 claims abstract description 18
- 239000004065 semiconductor Substances 0.000 claims abstract description 10
- 230000004888 barrier function Effects 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 8
- 238000000151 deposition Methods 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 7
- 230000007261 regionalization Effects 0.000 claims description 5
- 230000007547 defect Effects 0.000 abstract description 6
- 229920002994 synthetic fiber Polymers 0.000 abstract description 5
- 230000008021 deposition Effects 0.000 abstract description 2
- 239000000356 contaminant Substances 0.000 abstract 1
- 238000011109 contamination Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Weting (AREA)
Abstract
1. 청구 범위에 기재된 발명이 속한 기술 분야1. The technical field to which the invention described in the claims belongs
고집적 반도체 소자 제조 방법.Highly integrated semiconductor device manufacturing method.
2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention
종래에는 소오스/드레인용 폴리실리콘의 패턴 형성을 위해, 포토레지스트 패턴을 형성한 후 이를 식각 배리어로 이용하여 상기 소오스/드레인용 폴리실리콘의 식각을 실시하였는데, 포토마스크 공정 및 포토레지스트 제거 공정을 거치면서 소오스/드레인용 폴리실리콘에 합성물질의 결함, 오염물질 등이 형성되어 소자 불량의 원인을 초래하는 문제점을 해결하고자 함.Conventionally, in order to form a pattern of the source / drain polysilicon, a photoresist pattern was formed and then the source / drain polysilicon was etched using the photoresist pattern, and the photomask process and the photoresist removal process were performed. However, defects of synthetic materials and contaminants are formed in the source / drain polysilicon to solve the problem of device defects.
3. 발명의 해결방법의 요지3. Summary of Solution to Invention
소오스/드레인용 폴리실리콘을 증착하고, 하부층의 손실없이 쉽게 제거할 수 있도록 500Å 내지 1000Å 정도의 얇은 두께로 질화막을 증착한 다음, 포토레지스트를 도포하고 소오스/드레인용 폴리실리콘의 패턴 형성을 위한 소정의 포토레지스트 패턴을 형성하고, 이를 식각 배리어로 이용하여 상기 질화막과 소오스/드레인용 폴리실리콘을 차례로 식각함으로써 합성물질의 결함을 억제하고자함.Deposition of source / drain polysilicon, a nitride film with a thickness of about 500 kV to 1000 kV so as to be easily removed without loss of the underlying layer, and then a photoresist is applied and a predetermined pattern for forming the polysilicon for source / drain is formed. Forming a photoresist pattern, and using this as an etching barrier to etch the nitride film and the source / drain polysilicon in order to suppress the defect of the synthetic material.
4. 발명의 중요한 용도4. Important uses of the invention
고집적 반도체 소자, 특히 박막 트랜지스터의 제조에 이용됨.Used in the manufacture of highly integrated semiconductor devices, in particular thin film transistors.
Description
제1도는 종래의 박막 트랜지스터 제조시 발생하는 문제점을 설명하기 위한 공정도.1 is a process chart for explaining a problem occurring in the manufacturing of a conventional thin film transistor.
제2a도 내지 제2d도는 본 발명의 박막 트랜지스터 제조 방법에 따른 제조 공정도.2a to 2d is a manufacturing process chart according to the manufacturing method of the thin film transistor of the present invention.
제3a도 내지 제3c도는 본 발명의 다른 실시예에 따른 제조 공정도.3a to 3c is a manufacturing process diagram according to another embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11,21,31 : 반도체 기판 12,22,32 : 산화막11,21,31: semiconductor substrate 12,22,32: oxide film
13,23,35 : 소오스/드레인용 폴리실리콘 16 : 측벽 스페이서13,23,35: Polysilicon 16 for source / drain: Sidewall spacer
17 : 합성물질의 결함부분 24,36 : 질화막17: defective part of the synthetic material 24,36: nitride film
25,37 : 토레지스트 14,26,34 : 게이트 산화막25,37: toresist 14,26,34: gate oxide film
15,27,33 : 게이트 전극15,27,33: gate electrode
본 발명은 고집적 반도체 소자 제조 방법에 관한 것으로서, 특히 박막 트랜지스터(Thin Film Transistor) 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a highly integrated semiconductor device, and more particularly, to a method for manufacturing a thin film transistor.
종래의 박막 트랜지스터의 제조에 있어서는, 소오스/드레인용 폴리실리콘의 패턴 형성을 위해 단순히 포토레지스트 패턴을 형성한후, 이를 식각 배리어로 이용하여 상기 소오스/드레인용 폴리실리콘의 식각을 실시하였는데, 포토마스크 공정 및 포토레지스트 제거 공정을 거치면서 제1도에 도시한 바와같은 박막 트랜지스터의 구조에서 소오스/드레인용 폴리실리콘(13)상에 합성물질의 결함 부분(17)들이 형성되어 소자 불량의 원인을 초래하는 문제점이 발생하였으며, 이러한 현상은 도핑되지 않은 폴리실리콘의 경우에 더욱 심각한 문제가 되었다.In manufacturing a conventional thin film transistor, a photoresist pattern was simply formed to form a pattern of the source / drain polysilicon, and then the source / drain polysilicon was etched using the photoresist pattern as an etch barrier. Through the process and the photoresist removal process, defect portions 17 of the synthetic material are formed on the source / drain polysilicon 13 in the structure of the thin film transistor as shown in FIG. The problem occurred, which is a more serious problem in the case of undoped polysilicon.
따라서, 이러한 문제점을 해결하기 위하여 안출된 본 발명은, 소오스/드레인용 폴리실리콘을 증착하고, 질화막을 얇은 두께로 증착한 다음 포토레지스트를 도포하여 소오스/드레인용 폴리실리콘의 패턴 형성을 위한 포토래지스트 패턴을 형성하고, 이를 식각 배리어로 상기 질화막과 소오스/드레인용 폴리실리콘을 차례로 식각함으로써 합성물질의 결함을 억제할 수 있는 박막 트랜지스터 제조 방법을 제공하는 것을 목적으로 한다.Therefore, the present invention devised to solve this problem, the deposition of the source / drain polysilicon, the nitride film is deposited to a thin thickness and then a photoresist is applied to the photoresist for pattern formation of the source / drain polysilicon An object of the present invention is to provide a method of manufacturing a thin film transistor which can suppress a defect of a synthetic material by forming a gist pattern and sequentially etching the nitride film and the source / drain polysilicon using an etch barrier.
본 발명에 따른 박막 트랜지스터의 제조 방법은, 반도체 기판상에 절연층이 형성된 구조에 소오스/드레인용 폴리실리콘을 증착하고, 그 위에 질화막을 소정의 두께로 증착한 다음, 포토레지스트를 도포하는 단계와, 상기 소오스/드레인용 폴리실리콘의 패턴 형성을 위한 소정의 포토레지스트 패턴을 형성하는 단계와, 상기 포토레지스트패턴을 식각 배리어로 이용하여 상기 질화막과 소오스/드레인용 폴리실리콘을 차례로 식각하는 단계와, 잔류 포토레지스트와 질화막을 제거하는 단계 및, 게이트 산화막을 증착하고 게이트 전극 및 소오스/드레인 영역을 형성하는 단계를 포함하는 것을 특징으로 한다.The method for manufacturing a thin film transistor according to the present invention includes depositing polysilicon for source / drain on a structure in which an insulating layer is formed on a semiconductor substrate, depositing a nitride film on a predetermined thickness thereon, and then applying a photoresist; Forming a predetermined photoresist pattern for pattern formation of the source / drain polysilicon, sequentially etching the nitride film and the source / drain polysilicon using the photoresist pattern as an etch barrier; Removing the residual photoresist and nitride film; and depositing a gate oxide film and forming a gate electrode and a source / drain region.
본 발명의 다른 실시예에 따른 박막 트랜지스터 제조 방법은, 반도체 기판상에 게이트 전극과 게이트 산화막 및 소오스/드레인용 폴리실리콘층이 형성된 구조에 질화막을 소정의 두께로 증착하는 단계와, 상기 소오스/드레인용 폴리실리콘층의 패턴 형성을 위한 소정의 포토레지스트 패턴을 형성하는 단계와, 상기 포토레지스트 패턴을 식각 배리어로 이용하여 상기 질화막과 소오스/드레인용 폴리실리콘층을 차례로 식각하는 단계 및, 잔류 포토레지스트를 제거하는 단계를 포함하는 것을 특징으로 한다.According to another aspect of the present invention, there is provided a method of manufacturing a thin film transistor, the method comprising: depositing a nitride film to a predetermined thickness on a structure in which a gate electrode, a gate oxide film, and a source / drain polysilicon layer are formed on a semiconductor substrate; Forming a predetermined photoresist pattern for pattern formation of the cited polysilicon layer, sequentially etching the nitride film and the source / drain polysilicon layer using the photoresist pattern as an etching barrier, and remaining photoresist It characterized in that it comprises a step of removing.
이제 본발명의 한 실시예에 대하여 첨부 도면을 참조하여 보다 상세하게 설명하게 된다. 드레인 오프셋(Drain Offset) 구조의 오버 게이트형(Over gate) 박막 트랜지스터를 제조하는 경우, 먼저 제2a도에 도시한 바와 같이 반도체 기판(21)상에 산화막 (22)을 형성하고, 그 위에 소오스/드레인용 폴리실리콘(23)을 증착한 다음, 그 위에 다시 질화막(24)을 500Å 내지 1000Å의 두께로 증착한다. 다음에 소오스/드레인용 폴리실리콘(23)의 패턴 형성을 위한 포토레지스트 패턴(25)을 형성한다. 다음에 제2b도에 도시한 바와같이 상기 포토레지스트 패턴(25)을 식각 배리어로 이용하여 상기 질화막(24)과 소오스/드레인용 폴리실리콘(23)을 차례로 식각한다. 다음에는 제 2c도에 도시한 바와같이, 잔류 포토페지스트(25)와 상기 질화막(24)을 제거하고, 전체 구조 상부에 게이트 산화막(26)을 증착한 후, 통상적인 공정, 즉n+형의 이온으로 도핑된 게이트 전국 형성, 드레인 오프셋 구조의 소오스/드레인 영역을 형성하는 공정을 수행하여 제2d도에 도시한 바와같은 오프셋 구조의 박막 트랜지스터를 제조한다.An embodiment of the present invention will now be described in more detail with reference to the accompanying drawings. When manufacturing an over gate thin film transistor having a drain offset structure, an oxide film 22 is first formed on the semiconductor substrate 21 as shown in FIG. 2A, and the source / After the polysilicon 23 for drain is deposited, the nitride film 24 is again deposited thereon at a thickness of 500 kV to 1000 kV. Next, a photoresist pattern 25 for forming a pattern of the source / drain polysilicon 23 is formed. Next, as shown in FIG. 2B, the nitride film 24 and the source / drain polysilicon 23 are sequentially etched using the photoresist pattern 25 as an etching barrier. Next, as shown in FIG. 2C, the residual photoresist 25 and the nitride film 24 are removed, and the gate oxide film 26 is deposited on the entire structure, and then the conventional process, i. A thin film transistor having an offset structure as shown in FIG. 2D is manufactured by performing a process of forming a nationwide gate-doped gate doped region and a source / drain region having a drain offset structure.
본 발명의 다른 실시예는 반전형 게이트(Inverted Gate) 구조의 박막 트랜지스터를 제조하는 경우, 제 3a도에 도시한 바와같이 반도체 기판(31)상에 산화막(32),n+형의 이온으로 도핑된 게이트 전극(33), 게이트 산화막(34),소오스/드레인용 폴리실리콘(35)을 차례로 형성하고, 소오스/드레인 영역이 형성된 소오스/드레인용 폴리실리콘(35) 상부에 질화막(36)을 500Å 내지 1000Å의 두께로 증착한 후 소오스/드레인용 폴리실리콘(35)의 패턴 형성을 위한 포토레지스트패턴(37)을 형성하고, 상기 포토레지스트 패턴(37)을 식각 배리어로 이용하여 상기 질화막(36)과 소오스/드레인용 폴리실리콘(35)을 차례로 식각한다. 다음에 제3b도에 도시한 바와같이 상기 포토레지스트(37)을 제거하는 공정을 수행한다. 이때, 제3c도에 도시한 바와같이 상기 질화막(36)을 제거할 수도 있다.According to another embodiment of the present invention, when a thin film transistor having an inverted gate structure is fabricated, as shown in FIG. 3A, an oxide film 32 and an n + type ion are doped on a semiconductor substrate 31. The gate electrode 33, the gate oxide film 34, and the source / drain polysilicon 35 are sequentially formed, and the nitride film 36 is formed on the source / drain polysilicon 35 on which the source / drain regions are formed. After depositing at a thickness of 1000 Å, a photoresist pattern 37 for forming a pattern of the source / drain polysilicon 35 is formed. The photoresist pattern 37 is used as an etch barrier to form the photoresist pattern 37. The source / drain polysilicon 35 is sequentially etched. Next, as shown in FIG. 3B, the photoresist 37 is removed. At this time, the nitride film 36 may be removed as shown in FIG. 3C.
전술한 바와같은 본 발명을 이용하므로써, 박막 트랜지스터 제조시, 공정상의 결함이나 오염을 줄여 제조 수율을 향상시킬 수 있다는 장점이 있다.By using the present invention as described above, when manufacturing a thin film transistor, there is an advantage that the manufacturing yield can be improved by reducing process defects and contamination.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950006370A KR0171976B1 (en) | 1995-03-24 | 1995-03-24 | Method of producing thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950006370A KR0171976B1 (en) | 1995-03-24 | 1995-03-24 | Method of producing thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR960036099A KR960036099A (en) | 1996-10-28 |
| KR0171976B1 true KR0171976B1 (en) | 1999-02-01 |
Family
ID=19410518
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950006370A KR0171976B1 (en) | 1995-03-24 | 1995-03-24 | Method of producing thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0171976B1 (en) |
-
1995
- 1995-03-24 KR KR1019950006370A patent/KR0171976B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR960036099A (en) | 1996-10-28 |
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