KR100856544B1 - Method for manufacturing tin film transistor aray - Google Patents

Abstract

A thin film transistor array manufacturing method of a liquid crystal display device using four masks is disclosed. A gate electrode is formed on the substrate. A gate insulating film is formed on the substrate including the gate electrode. An active layer, an ohmic contact layer, and a conductive layer are sequentially stacked on the gate insulating layer to form a stacked structure. The stacked structure includes a central portion overlapping the gate electrode, wiring portions on both sides of the central portion, and peripheral portions adjacent to the wiring portions and opposite to the central portion, respectively. A first photoresist pattern is formed on the laminate to expose the peripheral portions. The first photoresist pattern is formed such that the thickness on the central portion is thinner than the thickness on the wiring portions. The conductive layer of the peripheral parts is etched using the first photoresist pattern as a mask to form an electrode pattern, and the ohmic contact layers of the peripheral parts are exposed. The first photoresist pattern is etched to form a second photoresist pattern exposing the electrode pattern of the central portion. Dry etching is performed using the second photoresist layer pattern as a mask to etch the ohmic contact layer and the active layer of the peripheral portions, and at the same time, the electrode pattern and the ohmic contact layer of the central portion are etched.

Gate wiring, data wiring, self etching

Description

Thin Film Transistor Array Manufacturing Method {METHOD FOR MANUFACTURING TIN FILM TRANSISTOR ARAY}

1 is a cross-sectional view illustrating a thin film transistor process of a liquid crystal display using the conventional four masks of FIG. 1.

2A and 2B illustrate a method of manufacturing a thin film transistor according to an exemplary embodiment of the present invention.

3A to 3C are other diagrams for describing a method of manufacturing a thin film transistor according to an exemplary embodiment of the present invention.

4A and 4B are still another views for explaining fabrication of a thin film transistor according to an embodiment of the present invention.

       Explanation of symbols on the main parts of the drawings

       100, 200: substrate 110, 210: gate electrode

       120, 220: gate insulating film 130, 230: active layer

       140, 240: ohmic contact layer 150: metal layer

       250: conductive layer 260: first photosensitive film pattern

       265: second photosensitive film pattern

The present invention relates to a method for manufacturing a thin film transistor array, and more particularly, to a method for manufacturing a thin film transistor and a thin film transistor array of a liquid crystal display device manufactured by a four mask process.

In the liquid crystal display (LCD), the manufacturing process of the thin film transistor and the thin film transistor array is one of very important process, which greatly affects the yield as well as the performance of the device.

The manufacture of a conventional liquid crystal display is performed through a 5 mask process or a 4 mask process.

For example, in order to manufacture a liquid crystal display, a process of forming a gate on a glass substrate using a gate mask, forming an active layer using an active mask, forming a source / drain using a source / drain mask, and A process of forming a channel portion, a process of forming a protective layer using a passivation mask, and a process of forming a pixel electrode using a pixel mask were performed.

As an alternative to this conventional five mask process, a four mask process has been proposed and used. The four mask process currently used is to reduce the active mask and the source / drain mask to one source / drain mask in the above-described five mask process.

1 is a cross-sectional view illustrating a thin film transistor process of a liquid crystal display using the conventional four masks of FIG. 1. As shown in FIG. 1, in the conventional method of manufacturing a thin film transistor using four masks, a gate 110 and a gate insulating film 120 are formed on a glass substrate 100, and an amorphous layer is formed on the gate insulating film 120. The active layer 130 made of silicon, the ohmic contact layer 140 for ohmic contact, and the metal layer 150 for source / drain formation are sequentially stacked, and then the metal layer 150 is first formed in such a manner that the source and the drain are not separated. Wet etch first.

Subsequently, the ohmic contact layer 140 and the active layer 130 in portions other than the active layer 130 are etched through a separate process. Then, the channel portion is opened by ashing the photoresist pattern (not shown), and then the metal layer 150 is removed by wet etching of the portion and the ohmic contact layer 140 is removed by dry etching. In addition, the conventional four mask process wet strips the photoresist pattern used as an etching mask.

In the conventional four-mask process, the ohmic contact layer 140 and the active layer 130 must be etched through a separate etching process after wet etching the metal layer 150 as described above. This not only requires two separate equipments, but also limits the accuracy of the pattern size due to the isotropy of wet etching. Furthermore, the conventional method performs hot water rinsing to suppress the occurrence of Al corrosion, which is used as the metal layer 150, which in itself increases the cost, but by moving from vacuum equipment to the hot water. Various problems arise, including mass production problems.

The present invention has been made in view of the above-described problems of the prior art, and an object thereof is to provide a method of manufacturing a thin film transistor and a thin film transistor array of a liquid crystal display device having a simple process and improved quality.

In order to achieve the above object, the present invention provides a method of manufacturing a thin film transistor of a liquid crystal display device, comprising the steps of: (a) forming a gate electrode on a substrate; (b) forming a stacked structure including a gate insulating film, an active layer, an ohmic contact layer, and a conductive layer on the substrate including the gate electrode, wherein the conductive layer is a top layer; (c) patterning the conductive layer into an electrode pattern in which source and drain electrodes are not separated; And (d) patterning a channel region to separate the electrode pattern into a source electrode and a drain electrode, and simultaneously removing the gate insulating layer of a pattern region not covered by the electrode pattern of the electrode pattern. Provided is a method for manufacturing a transistor.

       In addition, the object of the present invention, in the method for manufacturing a thin film transistor of the liquid crystal display device, the step of sequentially forming a gate electrode, a gate insulating film, an active layer, an ohmic contact layer and a conductive layer on the substrate; Forming a first photoresist pattern on which the region corresponding to the channel region is formed relatively thinly on the conductive layer; Etching the conductive layer using the first photoresist pattern as an etching mask to form an electrode pattern from which the conductive layer in the pattern region is removed; Removing a portion of the first photoresist pattern to form a second photoresist pattern that opens a channel region; Removing the ohmic contact layer and the active layer of the pattern region while removing Mo, which is an upper layer of the electrode pattern, to expose the gate insulating layer on the pattern region; Exposing the ohmic contact layer of the channel region by removing Al, which is the upper layer of the channel region, and Mo, which is a lower layer; And removing the ohmic contact layer of the channel region to expose the active layer of the channel region.

       Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Example

      2A and 2B illustrate a method of manufacturing a thin film transistor according to an exemplary embodiment of the present invention.

       2B is a cross-sectional view taken along the AA ′ direction of FIG. 2A. In the method of manufacturing the thin film transistor of the present invention, as shown in FIGS. 2A and 2B, the gate electrode 210 is formed on the substrate 200. The substrate 200 may be, for example, an insulating substrate made of soda lime glass. The gate electrode 210 may be formed of a double layer of upper and lower layers such as Mo / Al or Mo / ALNd, for example. The gate electrode 210 may be formed by depositing and patterning the material layer on the substrate 200 by sputtering as in the conventional manner.

      3A to 3C are other diagrams for describing a method of manufacturing a thin film transistor according to an exemplary embodiment of the present invention.

      3A through 3C, a gate insulating layer 220 is formed on the entire surface of the substrate 200 on which the gate electrode 210 is formed. An active layer 230, an ohmic contact layer 240, and a conductive layer 250 are sequentially formed on the gate insulating layer 220 to form a stacked structure. The stacked structure may include a central portion overlapping the gate electrode 210, wiring portions on both sides of the central portion, and peripheral portions adjacent to the wiring portions and opposite to the central portion, respectively.

The gate insulating film 220 may be formed of, for example, a silicon nitride film such as SiNx.

The active layer 230 is for forming a channel of the thin film transistor, and may form, for example, an intrinsic amorphous silicon having a thickness of 1,000 kPa to 3,000 kPa using PECVD. Preferably, the active layer 220 may form amorphous silicon to a thickness of about 2,000 kPa. An electric field is applied to the active layer 230 through the gate insulating film 220 according to the control signal applied to the gate electrode 210, and the active layer 230 on the gate electrode 210 forms a channel according to the control signal. The thin film transistor performs an on / off operation.

The ohmic contact layer 240 is for forming an ohmic contact between the source / drain region of the active layer 230 and the conductive layer 250. For example, the doped amorphous silicon (n + a-Si) is 200 to 1,000 Å. It can be formed in the thickness of. Preferably it can be formed to a thickness of about 500 kPa.

The conductive layer 250 is for forming a source / drain electrode and may be formed of, for example, a multi layer formed of Mo / Al / Mo. The conductive layer 250 may be formed to have an upper Mo film of 500 mV to 1,500 mV as an upper layer, an Al film of 3,000 to 6,000 mV as an upper layer, and a lower Mo film of 200 mV to 1,000 mV as a lower layer by sputtering.

Subsequently, as illustrated in FIG. 3B, the first photoresist layer pattern 260 is formed on the conductive layer 250, and the conductive layer 250 is patterned as the electrode pattern 255 using the etching mask as an etching mask. The first photoresist pattern 260 is formed such that the thickness on the central portion 300 is thinner than the thickness on the wiring portions. The method of forming the first photoresist pattern 260 having such a shape may be variously implemented. For example, there may be a method using a slit or lattice-type exposure mask or an exposure mask in which a portion corresponding to a thin portion of the first photoresist pattern 260 is semitransparent. In addition, it is possible to use any other method as long as the irradiation dose of light can be different for each part.

What is important here is that only the conductive layer 250 is patterned in this step to expose the underlying ohmic contact layer 240. In addition, the electrode pattern 255 has a form in which the source electrode and the drain electrode are not separated. That is, as can be seen in the drawing, the electrode pattern 255 of the central portion 300 is not etched in this step.

Next, the first photoresist pattern 260 is ashed to form a second photoresist pattern 265 to expose the electrode pattern 255 of the central portion 300 as shown in FIG. 3C. .

4A and 4B are still another views for explaining fabrication of a thin film transistor according to an embodiment of the present invention.

In particular, FIG. 4B is a cross-sectional view taken along the direction BB ′ of FIG. 4A, and the second photoresist pattern is omitted in FIG. 4A.

Referring to FIG. 4B, the electrode pattern 255 and the ohmic contact layer 240 of the central portion 300 are etched using the second photoresist pattern 265 as an etch mask, and the peripheral portions 310 of the peripheral portion 310 are etched. The ohmic contact layer 240 and the active layer 230 are etched. In other words, the electrode pattern 255 is separated into a source electrode and a drain electrode, and the ohmic contact layer 240 of the central portion 300 is removed to expose the active layer 230 of the central portion 300, and at the same time, the electrode pattern 255 is removed. The ohmic contact layer 240 and the active layer 230 of the peripheral portion 310, which are not covered by the 255, are removed.

Preferably dry etching is applied and performed in-situ and simultaneous removal.

Specifically, first, the upper Mo (top-Mo) film, which is the upper layer of the electrode pattern 255, uses Cl ₂ / SF ₆ as an etchant, and the peripheral portion not covered by the electrode pattern 255 by this etchant. Most of the ohmic contact layer 240 and the active layer 230 of 310 may be removed. Accordingly, the ohmic contact layer 240 of the central portion 300 is not removed, the ohmic contact layer 240 and the active layer 230 of the peripheral portion 310 are removed, and the lower gate insulating layer 220 is exposed. .

At this time, the etchant Cl ₂ / SF ₆ is supplied into the reaction chamber at 7000/1000 (scccm) and the pressure in the chamber can be maintained at 30m Torr.

The Al film, which is the upper layer of the electrode pattern 255, and the lower Mo (bottom-Mo) film, which is the lower layer, may be removed using Cl ₂ / BCl ₃ as an etchant. Since the etchant has an etch selectivity with respect to the gate insulating film 220, the gate insulating film 220 of the peripheral portion 310 is not substantially etched and remains exposed. In addition, the electrode pattern 255 of the central portion 300 is removed, and the ohmic contact layer 240 under the electrode pattern 255 is exposed.

At this time, the etchant Cl ₂ / BCl ₃ is supplied into the reaction chamber at 2000/2000 (scccm) and the pressure in the chamber may be maintained at 30m Torr.

Finally, the doped amorphous silicon, which is the ohmic contact layer 240 of the central portion 300, may be removed using Cl ₂ / SF ₆ . The active layer 230 of the central portion 300 is exposed by removing the ohmic contact layer 240 of the central portion 300. The etching of the doped amorphous silicon may be performed under the same conditions as removing the upper Mo layer, which is an upper layer of the electrode pattern 255.

As described above, the ohmic contact layer 240 and the active layer 230 of the peripheral part 310, which are not covered by the electrode pattern 255, may be removed while the electrode pattern 255 of the central part 300 is removed.

In addition to being a four mask process, this simultaneous removal has several advantages over the conventional four mask process. Simultaneous removal of the present invention is implemented in-situ self etching performed by dry etching. In addition, by applying dry etching having both anisotropy, accurate control of the pattern size is possible. This is desirable for manufacturing processes that require precise pattern size control, for example full HD TVs or quad HD TVs.

Meanwhile, in the above, the upper Mo (top-Mo) film as the upper layer of the electrode pattern 255, the Al film as the upper layer and the lower Mo (bottom-Mo) layer as the lower layer and the ohmic contact layer 240 of the central portion 300 ) Removal is described under different etchant and conditions.

However, according to another embodiment of the present invention, as an etchant, Cl ₂ / BCl ₃ is supplied at 2000/2000 (scccm) and the internal pressure is maintained at 10 m Torr, thereby forming an upper Mo (top-Mo) film and a middle film. The Al film and the lower Mo (bottom-Mo) film and the ohmic contact layer 240 of the central portion 300 may be simultaneously removed.

Even when the etchant is used, the ohmic contact layer 240 and the active layer 230 of the peripheral portion 310 which are not covered by the electrode pattern are removed while the electrode pattern 255 of the central portion 300 is removed. in-situ) at the same time.

Subsequently, post anti-corrosion treatment is preferably performed to prevent Al corrosion. Post-processing uses O ₂ / CHF ₃ plasma. This may also be carried out in situ following the dry etching process of the previous step in the present invention. Conventional manufacturing methods have to extract from vacuum equipment and pass through the atmosphere by performing hot water rinsing to prevent Al corrosion. On the other hand, the present invention does not cause such a problem.

Next, the second photoresist pattern is removed using an O ₂ plasma. This photoresist strip using oxygen plasma does not cause the problem of corrosion of Al together with post-corrosion treatment in the preceding vacuum equipment.

In addition to the four mask process, the present invention can shorten the process and obtain high quality compared to the conventional four mask process. The present invention enables accurate control of the pattern size by performing in-situ self etching performed by dry etching. Dry treatment of the aftertreatment method essentially prevents aluminum corrosion problems that may occur during the process or subsequent photoresist stripping. This shortening of the process and easy control of the pattern size can result in a significant improvement in yield.

Claims (19)

(a) forming a gate electrode on the substrate; (b) forming a gate insulating film on the substrate including the gate electrode; (c) stacking an active layer, an ohmic contact layer, and a conductive layer on the gate insulating layer in order to form a stacked structure, wherein the stacked structure includes a central portion overlapping the gate electrode, wiring portions on both sides of the central portion, and the wiring portions. Having peripheral portions each adjacent and located opposite the central portion; (d) forming a first photoresist film pattern exposing the periphery parts on the stacked structure, wherein the first photoresist pattern is formed such that the thickness on the central part is thinner than the thickness on the wiring parts; (e) etching the conductive layers of the peripheral parts using the first photoresist pattern as a mask to form an electrode pattern, and exposing the ohmic contact layers of the peripheral parts; (f) etching the first photoresist pattern to form a second photoresist pattern exposing the electrode pattern of the central portion; and (g) etching the ohmic contact layer and the active layer of the peripheral parts by performing dry etching using the second photoresist pattern as a mask, and simultaneously etching the electrode pattern and the ohmic contact layer of the center part. The method of claim 1, In the step (f), the etching of the first photosensitive film pattern is performed using a thin film transistor manufacturing method. The method of claim 1, In the step (e), etching the conductive layers of the peripheral portion is a thin film transistor manufacturing method using a dry etching. The method of claim 1, The conductive layer may be formed to include a lower layer, a middle layer, and an upper layer, which are sequentially stacked, and the electrode pattern may include the lower layer, the middle layer, and the upper layer. Step (g) may include (g-1) etching the upper layer of the central portion and simultaneously etching the ohmic contact layer and the active layer of the peripheral portion; (g-2) etching the middle and lower layers of the central portion; And (g-3) etching the ohmic contact layer in the center portion. The method of claim 4, wherein The step (g-1), the step (g-2) and the step (g-3) are performed in-situ. The method of claim 4, wherein The upper layer is an upper Mo layer, the step (g-1) is a thin film transistor manufacturing method performed using Cl ₂ / SF ₆ as an etching gas. The method of claim 4, wherein The middle layer is an Al film, the lower layer is a lower Mo film, the step (g-2) is a thin film transistor manufacturing method using the Cl ₂ / BCl ₃ as an etching gas. The method of claim 1, In the step (g), the ohmic contact layer and the active layer of the peripheral part and the electrode pattern and the ohmic contact layer of the central part are simultaneously etched using the same etching gas. The method of claim 8, The conductive layer may be formed to include a lower layer which is a lower Mo film, an upper layer which is an Al film, and an upper layer which is an upper Mo film, and the electrode pattern may include the lower layer, the middle layer, and the upper layer, which are sequentially stacked. The etching of the ohmic contact layer and the active layer of the peripheral portion, and the electrode pattern and the ohmic contact layer of the central portion is performed using Cl ₂ / BCl ₃ characterized in that the thin film transistor manufacturing method. (a) forming a gate electrode on the substrate; (b) forming a gate insulating film on the substrate including the gate electrode; (c) forming a stacked structure by sequentially stacking an active layer, an ohmic contact layer, and a conductive layer on the gate insulating film, wherein the conductive layer includes a lower Mo film, an Al film, and an upper Mo film, which are sequentially stacked, and the lamination The structure includes a central portion overlapping the gate electrode, wiring portions on both sides of the central portion, and peripheral portions adjacent to the wiring portions and opposite to the central portion, respectively; (d) forming a first photoresist film pattern exposing the periphery on the laminate structure, wherein the first photoresist pattern is formed such that the thickness on the central portion is thinner than the thickness on the wiring portion; (e) etching the conductive layer of the peripheral part using the first photoresist pattern as a mask to form an electrode pattern, and exposing the ohmic contact layer of the peripheral part; (f) etching the first photoresist pattern to form a second photoresist pattern exposing the electrode pattern of the central portion; (g) etching the upper Mo film in the center portion using a dry etching method using the second photoresist pattern as a mask and simultaneously etching the ohmic contact layer and the active layer in the peripheral portion; (h) etching the Al film and the lower Mo film of the central portion by dry etching using the second photoresist pattern as a mask; And (i) etching the ohmic contact layer in the center portion by using a dry etching method using the second photoresist pattern as a mask. The method of claim 10, The step (g) is a thin film transistor manufacturing method using Cl ₂ / SF ₆ as an etching gas. The method of claim 10, The step (h) is a thin film transistor manufacturing method using Cl ₂ / BCl ₃ as an etching gas. The method of claim 10, After the step (i), (j) a post anti-corrosion treatment using a plasma (O ₂ / CHF ₃ ) further comprises a thin film transistor manufacturing method. The method of claim 13, After the step (j), using the O ₂ plasma to remove the second photosensitive film pattern manufacturing method of a thin film transistor. The method of claim 13, The step (g), the step (h), the step (i), and the step (j) are performed in-situ. The method of claim 10, The step (g), the step (h) and the step (i) are performed in-situ thin film transistor manufacturing method. The method of claim 1, After the step (g), (h) a post anti-corrosion treatment using a plasma (O ₂ / CHF ₃ ) further comprising a thin film transistor manufacturing method. The method of claim 17, Step (g) and step (h) is a thin film transistor manufacturing method performed in-situ. The method of claim 4, wherein The lower layer is a lower Mo layer, the step (g-3) is a thin film transistor manufacturing method performed using Cl ₂ / SF ₆ as an etching gas.

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