KR20060098018A - Method of fabricating for tft substrate - Google Patents

Abstract

A method of manufacturing a TFT substrate is provided in which a data line and a semiconductor pattern positioned below it can have a uniform profile. The method for manufacturing a TFT substrate includes forming an etching mask including a first thickness region and a second thickness region thicker than the first thickness on both sides of the first and second thickness regions on a substrate on which a semiconductor layer and a conductor layer are stacked; Etching the conductor layer and the semiconductor layer using a mask to form a conductor pattern and an undercut semiconductor pattern thereunder; removing the first thickness region of the etch mask and partially removing the outer portion of the second thickness region; And etching the conductor layer pattern using the partially removed etching mask to separate the two conductor patterns spaced apart from each other.

LCD, semiconductor pattern, isotropic etching, dry etching

Description

Method of fabricating TFT substrate {Method of fabricating for TFT substrate}

1 is a layout view of a TFT substrate for a liquid crystal display device formed by a method of manufacturing a TFT substrate according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along line II-II ′ of the TFT substrate of FIG. 1.

3 is a cross-sectional view taken along line III-III ′ of the TFT substrate of FIG. 1.

4 through 12 are cross-sectional views sequentially illustrating a method of manufacturing the TFT substrate of FIG. 1.

(Explanation of symbols for the main parts of the drawing)

10: substrate 22: gate line

24: gate line end 26: gate electrode

28 sustain electrode line 30 gate insulating film

42, 48: semiconductor pattern 55, 56, 58: contact layer pattern

62, 64, 65, 66, 68: data wiring 70: protective film

72, 74, 76, 78: contact hole 82: wire electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a TFT substrate, and more particularly, to a method for manufacturing a TFT substrate, in which a data line and a semiconductor layer positioned below it can have a uniform profile.

The liquid crystal display device includes a color filter substrate including a color filter and a TFT substrate including a thin film transistor array. The color filter substrate and the TFT substrate face each other and are bonded to each other by a seal line interposed between the two substrates, and a liquid crystal layer is formed in a constant gap formed therebetween. As described above, the liquid crystal display device is composed of two substrates (color filter substrate and TFT substrate) on which electrodes are formed and a liquid crystal layer interposed therebetween. The liquid crystal molecules of the liquid crystal layer are rearranged by applying a voltage to the electrode. It is a device configured to display a predetermined image by adjusting the amount of light transmitted. Since the liquid crystal display is a non-light emitting device, a backlight unit for supplying light is located at the rear of the thin film transistor. Light transmitted from the backlight is adjusted according to the arrangement of liquid crystals.

The TFT substrate used in the liquid crystal display device includes a gate electrode, a gate insulating film formed on the gate electrode, a semiconductor layer formed on the gate insulating film, and a data wiring formed on the semiconductor pattern, that is, a source electrode / drain electrode, separated from the gate electrode. Include.

According to the three-mask or four-mask process by the TFT substrate manufacturing method according to the prior art, the source electrode / drain electrode is mainly patterned by wet etching, while the semiconductor layer is patterned by dry etching using plasma. .

Accordingly, when patterning the source electrode / drain electrode, etching occurs on the side surface of the source electrode / drain electrode, resulting in a structure in which the semiconductor layer protrudes laterally relative to the source electrode / drain electrode.

As such, when the semiconductor layer has a protruding structure, the distance is relatively close to the wiring formed around the semiconductor layer. When a signal is applied to the source electrode / drain electrode when driving the TFT substrate, parasitic capacitance is generated between the semiconductor layer and the peripheral wiring. There is a possibility that cross-talk occurs or vertical taint occurs in the liquid crystal display, thereby deteriorating display characteristics of the liquid crystal display.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method for manufacturing a TFT substrate, in which a data line and a semiconductor pattern positioned below it may have a uniform profile.

Technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a method of manufacturing a TFT substrate, wherein a first thickness region and a first thickness region are formed on both sides of a substrate on which a semiconductor layer and a conductor layer are stacked. Forming an etch mask comprising a thicker second thickness region, etching the conductor layer and the semiconductor layer using the etch mask to form a conductor pattern and an undercut semiconductor pattern under the etching pattern; Removing the first thickness region of the etching mask and partially removing the outer portion of the second thickness region, and etching the conductor layer pattern using the partially removed etching mask to form two conductor patterns spaced apart from each other. Separating.

Specific details of other embodiments are included in the detailed description and the drawings.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention, and the general knowledge in the art to which the present invention pertains. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

Hereinafter, a method of manufacturing a TFT substrate according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

First, referring to FIGS. 1 to 3, a unit pixel structure of a TFT substrate for a liquid crystal display device, which is completed by using a method of manufacturing a TFT substrate, will be described in detail with reference to FIGS. 1 to 3.

1 is a layout view of a TFT substrate for a liquid crystal display device formed by a method of manufacturing a TFT substrate according to an embodiment of the present invention. 2 is a cross sectional view taken along the line II-II 'of the TFT substrate shown in FIG. 1, and FIG. 3 is a cross sectional view taken along the line III-III' of the TFT substrate shown in FIG.

First, gate wirings 22, 24, and 26 are formed on the insulating substrate 10. The gate lines 22, 24, and 26 include a gate line 22, a gate line end 24, and a gate electrode 26.

In addition, the storage electrode line 28 is formed on the substrate 10 in parallel with the gate line 22. The storage electrode lines 28 and the gate lines 22, 24, and 26 may be formed of a single layer made of Al (Al alloy), or a double layer in which Al (Al alloy) and Mo (Mo alloy) are laminated. The storage electrode line 28 overlaps the conductive capacitor conductor 68 for the storage capacitor connected to the pixel electrode 82 to be described later to form a storage capacitor which improves charge storage capability of the pixel. The pixel electrode 82 and the gate line to be described later will be described. If the holding capacity generated by the overlap of (22) is sufficient, it may not be formed. The same voltage as that of the common electrode of the upper substrate is usually applied to the storage electrode line 28.

A gate insulating film 30 made of silicon nitride (SiNx) or the like is formed on the gate wirings 22, 24, 26, and the storage electrode line 28 to form the gate wirings 22, 24, 26, 28, and the storage electrode line 28. Covering.

Semiconductor patterns 42 and 48 made of a semiconductor such as hydrogenated amorphous silicon are formed on the gate insulating layer 30, and n-type impurities such as phosphorus (P) are highly concentrated on the semiconductor patterns 42 and 48. An ohmic contact layer pattern or an intermediate layer pattern 55, 56, 58 made of amorphous silicon or the like doped with is formed.

The data lines 62, 64, 65, 66, and 68 are formed on the ohmic contact layer patterns 55, 56, and 58. The data wirings 62, 64, 65, 66, and 68 are made of a single layer made of Al (Al alloy), or a triple layer in which Mo (Mo alloy), Al (Al alloy) and Mo (Mo alloy) are laminated. Can be. The data line is a thin film that is a branch of the data line 62 formed in the vertical direction, the data line end 68 connected to one end of the data line 62 to receive an image signal from the outside, and the data line 62. And a data line portion 62, 68, 65 made of the source electrode 65 of the transistor, and separated from the data line portions 62, 68, 65, and the channel portion C of the gate electrode 26 or the thin film transistor. In addition, the drain electrode 66 of the thin film transistor positioned on the opposite side of the source electrode 65 and the conductor pattern 64 for the storage capacitor located on the storage electrode line 28 are also included. When the storage electrode line 28 is not formed, the conductor pattern 64 for the storage capacitor is also not formed.

The contact layer patterns 55, 56, and 58 serve to lower the contact resistance between the semiconductor patterns 42 and 48 below and the data lines 62, 64, 65, 66, and 68 above them. It has exactly the same form as (62, 64, 65, 66, 68). That is, the data line part intermediate layer pattern 55 is the same as the data line parts 62, 68, and 65, the drain electrode intermediate layer pattern 56 is the same as the drain electrode 66, and the storage capacitor intermediate layer pattern 58 is It is the same as the conductor pattern 64 for holding capacitors.

The semiconductor patterns 42 and 48 have the same shape as the data wires 62, 64, 65, 66 and 68 and the ohmic contact layer patterns 55, 56 and 58 except for the channel portion C of the thin film transistor. Doing Specifically, the semiconductor capacitor 48 for the storage capacitor, the conductor pattern 64 for the storage capacitor, and the contact layer pattern 58 for the storage capacitor have the same shape, but the semiconductor pattern 42 for the thin film transistor has data wiring and contact. Slightly different from the rest of the layer pattern. That is, in the channel portion C of the thin film transistor, the data line portions 62, 68, and 65, in particular, the source electrode 65 and the drain electrode 66 are separated, and the contact layer pattern for the data line intermediate layer 55 and the drain electrode. Although 56 is also separated, the semiconductor pattern 42 for thin film transistors is not disconnected here and is connected to generate a channel of the thin film transistor.

On the data lines 62, 64, 65, 66 and 68, an a-Si: C: O film or a-Si: O: F film (low dielectric constant CVD) deposited by silicon nitride or plasma enhanced chemical vapor deposition (PECVD) method Film) or an organic insulating film is formed. The protective film 70 has contact holes 76, 78, and 72 that expose the drain electrode 66, the data line end 64, and the conductive pattern 68 for the storage capacitor, and together with the gate insulating film 30. It has a contact hole 74 that exposes the gate line end 24.

On the passivation layer 70, a pixel electrode 82 that receives an image signal from a thin film transistor and generates an electric field together with the electrode of the upper plate is formed. The pixel electrode 82 is made of a transparent conductive material such as ITO or IZP, and is physically and electrically connected to the drain electrode 66 through the contact hole 76 to receive an image signal. The pixel electrode 82 also overlaps with the neighboring gate line 22 and the data line 62 to increase the aperture ratio, but may not overlap. In addition, the pixel electrode 82 is also connected to the conductive capacitor pattern 64 through the contact hole 72 to transmit an image signal to the conductor pattern 64. On the other hand, an auxiliary gate line end 86 and an auxiliary data line end 88 are formed on the gate line end 24 and the data line end 68 through the contact holes 74 and 78, respectively. They are not essential to serve to protect the ends and to protect adhesion between the ends 24 and 68 and external circuit devices, and their application is optional.

Hereinafter, a method of manufacturing a TFT substrate for a liquid crystal display device, particularly a thin film transistor, having a structure of FIGS. 1 and 3 using four masks will be described in detail with reference to FIGS. 1 to 3 and 4 to 12. Let's explain.

First, as shown in FIG. 4, a multilayer metal film for gate wiring (not shown) is laminated on the substrate 10, and then patterned to form a gate electrode 26. Here, the gate electrode 26 may be formed of a single layer composed of Al (Al alloy), or a double layer in which Al (Al alloy) and Mo (Mo alloy) are laminated.

Next, as shown in FIG. 5, the gate insulating film 30, the semiconductor layer 40, and the intermediate layer 50 made of silicon nitride are respectively 1,500 kV to 5,000 kV, 500 kV to 2,000 kV, 300 kV using chemical vapor deposition. To 600 μm thickness, and then to form a conductor layer 60 to be used as data wiring, and then to the photosensitive film 110 is applied to a thickness of 1㎛ 2㎛. Here, the conductor layer 60 to be used as the data wiring may be formed of a single layer made of Al (Al alloy), or a triple layer in which Mo (Mo alloy), Al (Al alloy) and Mo (Mo alloy) are laminated. .

Thereafter, the photosensitive film 110 is irradiated with light through a mask and then developed to form the photosensitive film patterns 112 and 114, as shown in FIG. In this case, among the photoresist patterns 112 and 114, the channel portion C of the thin film transistor, that is, the first portion 114 positioned between the source electrode 65 and the drain electrode 66, is the data wiring portion A, that is, the source. The thickness is made smaller than that of the second part 112 located at the part where the data line, such as the electrode 65 and the drain electrode 66, is to be formed, and all of the photosensitive film of the other part B is removed. At this time, the ratio of the thickness of the photoresist film 114 remaining in the channel portion C and the thickness of the photoresist film 112 remaining in the data wiring portion A should be different depending on the process conditions in the etching process to be described later. It is preferable to make the thickness of the 1st part 114 into 1/2 or less of the thickness of the 2nd part 112, for example, it is good that it is 4,000 kPa or less.

As such, there may be various methods of varying the thickness of the photoresist layer according to the position. In order to control the light transmittance in the A region, a slit or lattice-shaped pattern is mainly formed or a translucent film is used.

In this case, the line width of the pattern located between the slits, or the interval between the patterns, that is, the width of the slits, is preferably smaller than the resolution of the exposure apparatus used for exposure. A thin film having a thickness or a thin film may be used.

When the light is irradiated to the photosensitive film through such a mask, the polymers are completely decomposed at the part directly exposed to the light, and the polymers are not completely decomposed because the amount of light is small at the part where the slit pattern or the translucent film is formed. In the part covered by the light film, the polymer is hardly decomposed. Subsequently, when the photoresist film is developed, only a portion where the polymer molecules are not decomposed is left, and a thin photoresist film may be left at a portion where the light is not irradiated at a portion less irradiated with light. In this case, if the exposure time is extended, all molecules are decomposed, so it should not be so.

The thin photoresist pattern 114 is developed by using a photoresist film made of a reflowable material and exposed with a conventional mask that is divided into a part that can completely transmit light and a part that can not completely transmit light. It may be formed by reflowing a portion of the photosensitive film to a portion where the photosensitive film does not remain.

Subsequently, etching is performed on the photoresist pattern 114 and the underlying layers, that is, the conductor layer 60, the intermediate layer 50, and the semiconductor layer 40. In this case, the data line and the lower layer of the data line remain in the data wiring portion A, and only the semiconductor layer should remain in the channel portion C, and the upper three layers 60, 50, 40 must be removed to expose the gate insulating film 30.

First, as illustrated in FIG. 7, the conductor layer 60 of the portion exposed by the photosensitive film patterns 112 and 114, that is, the other portion B is removed to expose the lower intermediate layer 50. In this process, a wet etching method may be used. In this case, the conductive layer 60 may be etched and the photoresist patterns 112 and 114 may be hardly etched.

In this way, as shown in FIG. 7, only the conductor layer of the channel portion C and the data wiring portion B, that is, the conductor pattern 67 for the source / drain remains, and the conductor layer 60 of the other portion B is All are removed to reveal the underlying intermediate layer 50. At this time, the remaining conductor pattern 67 is connected to the source electrode 65 and the drain electrode 66 without being separated.

Subsequently, as shown in FIG. 8, the intermediate layer 50 of the portion exposed by the photosensitive film patterns 112 and 114, that is, the other portion B, and the semiconductor layer 40 below the florin (F ₂ ) series are formed. By using the etching gas of the isotropic dry etching (isotropic dry etching) at the same time (intermediate layer and semiconductor layer has almost no etching selectivity) is removed. At this time, the intermediate layer 50 and the semiconductor layer 40 may be removed by isotropic dry etching by flowing a florin-based etching gas without using plasma for isotropic dry etching and merely maintaining the process chamber in a vacuum state. have.

In this case, as shown in FIG. 8, the intermediate layer 50 and the semiconductor layer 40 of the other portion B are removed to expose the gate insulating layer 30 below. In this step, the intermediate layer pattern 57 and the semiconductor pattern 42 are completed under the conductor pattern 67.

Here, XeF ₂ , BrF ₂ , ClF _2, etc. may be used as the florin-based etching gas. The fluorine-based etching gas has a high etch selectivity of about 50: 1 or more with respect to aluminum, photoresist, silicon nitride, silicon oxide, and the like. Specifically, it has an etching selectivity of about 60: 1 or more relative to silicon: aluminum and an etching selectivity of about 100: 1 or more relative to silicon: (photosensitive film or silicon nitride).

Due to the high conventional SF ₆ and HCl in the mixture or, SF ₆ and Cl ₂ etch selectivity only on the silicon nitride case of etching the intermediate layer 50 and the semiconductor layer 40 by using a plasma of a mixed gas of the non-conductors ( 67), but when dry etching using the Florin-based etching gas of the present invention, the etching damage to the conductor pattern 67, because it has a high etching selectivity also to the conductor pattern 67 Can be prevented.

In addition, since the florin-based etching gas has a high etching selectivity with respect to silicon nitride, even if the intermediate layer 50 and the semiconductor layer 40 are overetched, the gate insulating layer 30 disposed below is damaged. Do not give.

In addition, when the intermediate layer 50 and the semiconductor layer 40 are etched using plasma of a mixed gas of SF ₆ and HCl or a mixed gas of SF ₆ and Cl _2, the etching rate is about 0.2 to 0.3 μm / min. In the case of using the florin-based etching gas of the present invention, the etching rate may be increased to about 1 to 3 μm / min. Therefore, since the intermediate layer 50 and the semiconductor layer 40 can be etched effectively within a short time, the manufacturing time can be reduced by shortening the process time.

In addition, since the photoresist patterns 112 and 114 are hardly etched by the florin-based etching gas, process margins due to the etching of the photoresist pattern 114 in the C region during the formation of the photoresist patterns 112 and 114 of FIG. 6. There is no need to secure a margin.

Next, as shown in FIG. 9, the photoresist patterns 112 and 114 are etched back to remove the photoresist pattern 114 of the channel portion C. At this time, since the photoresist pattern 112 of the data wiring portion A is also etched, the thickness becomes thin and etching occurs on the side surface. 9 shows a profile before the photoresist pattern 112 of the data line portion A is etched.

Subsequently, ashing removes photoresist residue remaining on the surface of the source / drain conductor pattern 67 of the channel portion C.

Next, as shown in FIG. 10, the source / drain conductor pattern 67 of the channel part C and the source / drain interlayer pattern 57 below are etched and removed. In this case, the source / drain conductor pattern 67 may be wet etched, and the intermediate layer pattern 57 may be dry etched. This eliminates the laterally protruding portion of the conductor pattern 67 in FIG. 9, and separates the source wiring 65 and the drain electrode 66 into contact layers below the data wirings 65 and 66. Patterns 55 and 56 are completed.

As shown in FIG. 10, the laterally protruding portion of the conductor pattern 67 is removed, whereby the conductor pattern 67, the contact layer patterns 55 and 56 and the semiconductor pattern 42 thereunder. The sides of the are aligned to have a uniform profile. In FIG. 8, an undercut of the intermediate layer 50 and the semiconductor layer 40 is previously formed in the lower portion of the conductor pattern 67 through isotropic dry etching, so that the semiconductor pattern is lower than that of the conductor patterns 55 and 56. This is because (42) was prevented from protruding laterally.

Then, the photosensitive film second portion 112 remaining in the data wiring portion A is removed. However, the removal of the second portion 112 may be performed after removing the conductor pattern 67 for the channel portion C source / drain and before removing the intermediate layer pattern 57 thereunder.

Next, as shown in FIG. 11, a silicon nitride, an a-Si: C: O film, or an a-Si: O: F film is grown by chemical vapor deposition (CVD) or an organic insulating film is applied to form a protective film 70. do.

Next, as shown in FIG. 12, the protective layer 70 is photo-etched to form contact holes 76 exposing the drain electrodes 66, respectively.

Finally, as shown in FIG. 3, an ITO layer or an IZO layer having a thickness of 400 kHz to 500 kHz is deposited and photo-etched to form a pixel electrode 82 connected to the drain electrode 66.

On the other hand, as a gas used in the pre-heating process before laminating ITO or IZO, it is preferable to use nitrogen, which is a metal oxide film on the upper portion of the metal film 66 exposed through the contact hole 76. This is to prevent the formation.

As described above, the manufacturing method of the TFT substrate of the present invention can be applied to the manufacturing method of a TFT substrate using four masks, but the same can be applied to the manufacturing method of a TFT substrate using three masks.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

As described above, according to the method for manufacturing a TFT substrate according to the present invention, when patterning the semiconductor layer, dry etching without using plasma is used to form an undercut in the lateral direction of the semiconductor layer in advance, and the data is located thereon. It can be aligned with wiring.

Claims (8)

Forming an etching mask including a first thickness region and a second thickness region thicker than the first thickness on both sides of the first thickness region on the substrate on which the semiconductor layer and the conductor layer are stacked; Etching the conductor layer and the semiconductor layer using the etching mask to form a conductor pattern and an undercut semiconductor pattern under the conductor pattern; Removing the first thickness region of the etching mask and partially removing an outer portion of the second thickness region; And Etching the conductor layer pattern by using the partially removed etching mask to separate the two conductive patterns spaced apart from each other. The method of claim 1, wherein the forming of the conductor pattern and the undercut semiconductor pattern under the conductive pattern is performed. Wet etching the conductor layer using the etching mask to form the conductor pattern; And And isotropic dry etching the semiconductor layer using the etching mask to form the undercut semiconductor pattern under the conductor pattern. The method of claim 2, The isotropic dry etching is a method of manufacturing a TFT substrate is a dry etching using no plasma. The method of claim 2, The isotropic dry etching is a method of manufacturing a TFT substrate using dry etching of florin-based etching house. The method of claim 4, wherein The florin-based etching gas is XeF ₂ , BrF ₂ or ClF ₂ manufacturing method of a TFT substrate. The method of claim 2, And wherein the isotropic etching gas has an etch selectivity of the semiconductor layer: the gate insulating film, the semiconductor layer: the conductor layer, and the semiconductor layer: the photoresist pattern. According to claim 1, Partially removing the etch mask is such that an outer profile of the partially removed etch mask substantially coincides with an outer profile of the semiconductor pattern. According to claim 1, Sequentially forming a gate pattern and a gate insulating film between the substrate and the semiconductor layer; Wherein the semiconductor pattern is an active region of a TFT substrate, and the two separated conductor patterns are a source electrode and a drain electrode, respectively.

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