KR101026797B1 - Thin film transistor array panel and manufacturing method thereof - Google Patents

Thin film transistor array panel and manufacturing method thereof Download PDF

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Publication number
KR101026797B1
KR101026797B1 KR1020030055419A KR20030055419A KR101026797B1 KR 101026797 B1 KR101026797 B1 KR 101026797B1 KR 1020030055419 A KR1020030055419 A KR 1020030055419A KR 20030055419 A KR20030055419 A KR 20030055419A KR 101026797 B1 KR101026797 B1 KR 101026797B1
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South Korea
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formed
layer
gate insulating
drain electrode
electrode
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KR1020030055419A
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Korean (ko)
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KR20050017900A (en
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김장수
류혜경
유영훈
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삼성전자주식회사
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Priority to KR1020030055419A priority Critical patent/KR101026797B1/en
Priority claimed from US10/915,958 external-priority patent/US7190000B2/en
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Abstract

An insulating substrate, a gate line and sustain electrode wiring formed on the insulating substrate, a gate insulating film formed on the gate line and the sustain electrode wiring, a semiconductor layer formed on the gate insulating film, a drain electrode and a data line formed on the semiconductor layer, A protective film formed on the data line, an organic film formed on the protective film, and a pixel electrode formed on the organic film and electrically connected to the drain electrode, wherein a part of the drain electrode and a part of the organic electrode wiring overlap each other. A thin film transistor array panel in which the thickness of the gate insulating film provided in the portion is thinner than the thickness of the gate insulating film in the other portion.
Retention Capacitance, Opening Ratio

Description

Thin film transistor array panel and manufacturing method therefor {THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF}

1 is a layout view of a thin film transistor array panel for a liquid crystal display according to a first exemplary embodiment of the present invention.

2A and 2B are cross-sectional views of the thin film transistor array panel of FIG. 1 taken along lines IIa-IIa 'and IIb-IIb', respectively.

3, 5, 7, and 9 are layout views at an intermediate stage in the method of manufacturing the thin film transistor array panel according to the exemplary embodiment shown in FIGS. 1 to 2B.

4A and 4B are cross-sectional views taken along lines IVa-IVa 'and IVb-IVb' of FIG. 3, respectively.

6A and 6B are cross-sectional views at the next stage of FIGS. 4A and 4B,

8A and 8B are cross-sectional views at the next stage of FIGS. 6A and 6B,

10A and 10B are cross-sectional views at the next stage of FIGS. 8A and 8B,

11A and 11B are cross-sectional views illustrating a step of forming a contact hole using a photomask,

12 is a layout view of a thin film transistor array panel for a liquid crystal display according to a second exemplary embodiment of the present invention.                 

13A and 13B are cross-sectional views of the thin film transistor array panel of FIG. 12 taken along lines XIIIa-XIIIa 'and XIIIb-XIIIb', respectively.

14, 16, 18, and 20 are layout views at an intermediate stage in the method of manufacturing the thin film transistor array panel according to the exemplary embodiment illustrated in FIGS. 12 to 13B.

15A and 15B are cross-sectional views taken along the lines XVa-XVa 'and XVb-XVb' of FIG. 14, respectively, and FIGS. 17A and 17B are cross-sectional views at the next steps of FIGS. 15A and 15B,

19A and 19B are cross-sectional views at the next stage of FIGS. 17A and 17B,

21A and 21B are cross-sectional views at the next stage of FIGS. 19A and 19B,

22A and 22B are cross-sectional views illustrating a step of forming a contact hole using a photomask,

23 is a layout view of a thin film transistor array panel according to a third exemplary embodiment of the present invention.

24 is a layout view of a liquid crystal display according to a fourth exemplary embodiment of the present invention.

25A is a cross-sectional view taken along line XXVa-XXVa 'of FIG. 24,

FIG. 25B is a cross-sectional view taken along line XXVb-XXVb 'of FIG. 24.

<Description of the symbols for the main parts of the drawings>

110: substrate 121, 129: gate line

124: gate electrode 140; Gate insulating film

151, 154: semiconductors 161, 163, 165: ohmic contact members

171, 179: data line 173: source electrode                 

175: drain electrode 180p: protective film

180q: organic film 181, 182, 184, 186, 187, 188: contact hole

190: pixel electrode 81, 82: contact auxiliary member

The present invention relates to a thin film transistor array panel and a method of manufacturing the same.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two display panels on which a field generating electrode is formed and a liquid crystal layer interposed therebetween. It is a display device which controls the transmittance | permeability of the light which passes through a liquid crystal layer by rearranging.

Among the liquid crystal display devices, a field generating electrode is provided in each of two display panels. Among them, a liquid crystal display device having a structure in which a plurality of pixel electrodes are arranged in a matrix form on one display panel and one common electrode covering the entire display panel on the other display panel is mainstream. The display of an image in this liquid crystal display device is performed by applying a separate voltage to each pixel electrode. To this end, a thin film transistor, which is a three-terminal element for switching a voltage applied to a pixel electrode, is connected to each pixel electrode, and a gate line for transmitting a signal for controlling the thin film transistor and a data line for transmitting a voltage to be applied to the pixel electrode are provided. Install on the display panel.

In addition, a storage capacitance Cst is formed so that the charge transferred by the first signal transferred to the pixel is maintained until the second signal is applied. Such storage capacitance can be achieved by using adjacent gate lines or by using a common structure in which separate storage electrode wirings are formed.

The common structure in which the separate sustain electrode wirings are formed uses a sustain capacitance formed between the drain electrode and the sustain electrode wiring in contact with the pixel electrode, and as the overlapping area between the sustain electrode wiring and the drain electrode increases, the sustain capacitance increases. do. However, when the overlap area is increased, a problem arises in that the opening ratio is relatively decreased.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a thin film transistor array panel and a method of manufacturing the same, which increase an aperture ratio without reducing a holding capacitance.

The thin film transistor array panel according to the present invention includes an insulating substrate, a gate line and a sustain electrode wiring formed on the insulating substrate, a gate insulating film formed on the gate line and the sustain electrode wiring, a semiconductor layer formed on the gate insulating film, and A drain electrode and a data line formed on the semiconductor layer, a passivation film formed on the data line, an organic film formed on the passivation film, and a pixel electrode formed on the organic film and electrically connected to the drain electrode. It is preferable that the thickness of the gate insulating film provided in the part which overlaps a part of the said drain electrode and a part of the said organic electrode wiring is thinner than the thickness of the gate insulating film of another part.

The storage electrode wiring may include a storage electrode line formed in parallel with the gate line, and a storage electrode connected to the storage electrode line and having a width wider than that of the storage electrode line, wherein the drain electrode is connected to the pixel electrode. It is preferable that the width is extended and this portion overlaps with the sustain electrode.

The pixel electrode may be connected to the drain electrode through a contact hole penetrating through the passivation layer and the organic layer, and the sidewall of the contact hole may have a stepped profile.

In addition, the protective film is made of an inorganic insulating material, it is preferred to further include a color filter formed between the protective film and the organic film.

In addition, the color filter is preferably removed from the contact hole on the drain electrode.

In the color filter, red, green, and blue color filters are formed long along the pixel columns separated by the data lines, and red, green, and blue colors appear repeatedly.

In addition, the method of manufacturing a thin film transistor array panel according to the present invention includes forming a gate line and a storage electrode wiring on a substrate, forming a gate insulating film and a semiconductor layer on the gate line and the storage electrode wiring, and a data line on the semiconductor layer. And forming a drain electrode, depositing a passivation layer and an organic layer on the data line and the drain electrode, and photolithography the passivation layer and the organic layer to form a contact hole exposing a portion of the drain electrode. And forming a pixel electrode connected to a part of the drain electrode, and in the forming of the gate insulating film and the semiconductor layer, the holding of the gate insulating film and the semiconductor layer by photo etching using a photomask having a slit region. Electrode wiring and part of the drain electrode To form the gate insulating film in the overlapping portion thinner than other portion is preferable. In addition, in the photomask having the slit region, a blocking region and an opening region are formed in addition to the slit region, and a semiconductor layer is formed at a portion corresponding to the blocking region, and a semiconductor layer is etched at a portion corresponding to the slit region. In the portion corresponding to the region, it is preferable that the semiconductor layer is etched and a portion of the gate insulating layer beneath it is etched.

In addition, the thin film transistor array panel according to the present invention includes an insulating substrate, a gate line and sustain electrode wiring formed on the insulating substrate, a gate insulating film formed on the gate line and the sustain electrode wiring, and a semiconductor layer formed on the gate insulating film. And a drain electrode and a data line formed on the semiconductor layer, a passivation layer formed on the data line, an organic layer formed on the passivation layer, and a pixel formed on the organic layer and electrically connected to the drain electrode. It is preferable that a part of the drain electrode is formed with a contact hole so that the gate insulating film is exposed, and the thickness of the gate insulating film of the portion where the contact hole is formed is thinner than the thickness of the gate insulating film of the other portion.

The contact hole is preferably formed in a portion where the drain electrode and the sustain electrode wiring overlap.

The storage electrode wiring may include a storage electrode line formed in parallel with the gate line, and a storage electrode connected to the storage electrode line and having a width wider than that of the storage electrode line, wherein the drain electrode is connected to the pixel electrode. It is preferable that the width is extended and this portion overlaps with the sustain electrode.

The pixel electrode may be connected to the drain electrode through a contact hole penetrating through the passivation layer and the organic layer, and the sidewall of the contact hole may have a stepped profile.

In addition, the pixel electrode is preferably in contact with the gate insulating film through the contact hole.

In addition, the method of manufacturing a thin film transistor array panel according to the present invention includes forming a gate line and a storage electrode wiring on a substrate, forming a gate insulating film and a semiconductor layer on the gate line and the storage electrode wiring, and a data line on the semiconductor layer. And forming a drain electrode, wherein a portion of the drain electrode is formed so as to expose the gate insulating film, depositing a protective film and an organic film on the data line and the drain electrode, a protective film formed on the contact hole, and Performing photolithography on the organic layer, and forming a pixel electrode connected to a part of the drain electrode through the contact hole, and performing photolithography on the passivation layer and the organic layer using a photomask having a slit region. Thin gate insulating film formed in contact hole To form is preferred.                     

In addition, the photomask may include a blocking region and a slit region, an organic layer and a protective layer may be formed in a portion corresponding to the blocking region, and the gate insulating layer may be partially etched in a portion corresponding to the slit region.

Then, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

Hereinafter, a thin film transistor array panel and a method of manufacturing the same according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

First, a thin film transistor array panel according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1, 2A, and 2B.

1 is a layout view of a thin film transistor array panel for a liquid crystal display according to an exemplary embodiment of the present invention, and FIGS. 2A and 2B illustrate the thin film transistor array panel of FIG. 1 taken along lines IIa-IIa 'and IIb-IIb', respectively. One cross section.                     

1 to 2B, a plurality of gate lines 121 and a plurality of storage electrode lines 131 are formed on the insulating substrate 110.

The gate line 121 and the storage electrode line 131 mainly extend in the horizontal direction and are separated from each other. The gate line 121 transmits a gate signal, and a portion of each gate line 121 protrudes upward to form a plurality of gate electrodes 124. The storage electrode line 131 receives a predetermined voltage such as a common voltage, and includes the storage electrode 137 formed by an extension extending upward and downward.

The gate line 121 and the storage electrode line 131 include a conductive film formed of a silver-based metal such as silver (Ag) or a silver alloy having a low resistivity, or an aluminum-based metal such as aluminum (Al) or an aluminum alloy. In addition to conductive films, chromium (Cr), titanium (Ti), tantalum (Ta), molybdenum (Mo) and alloys thereof with good physical, chemical and electrical contact properties with other materials, in particular ITO or IZO [see: Molybdenum-Tungsten (MoW) alloy] may have a multilayer film structure including another conductive film. An example of the combination of the bottom film and the top film is a chromium / aluminum-neodymium (Nd) alloy.

Sides of the gate line 121 and the storage electrode line 131 are inclined, and the inclination angle is in a range of about 30-80 ° with respect to the surface of the substrate 110.

A gate insulating layer 140 made of silicon nitride (SiNx) is formed on the gate line 121 and the storage electrode line 131.

The thickness of the gate insulating film 140 formed on the sustain electrode 137 is thinner than the thickness of the gate insulating film 140 of another portion. Therefore, the sustain capacitance formed between the extension 177 of the drain electrode and the sustain electrode 137 connected to the pixel electrode 190 to be described later can be increased.

A plurality of linear semiconductors 151 made of hydrogenated amorphous silicon (amorphous silicon is abbreviated a-Si) and the like are formed on the gate insulating layer 140. The linear semiconductor 151 extends mainly in the longitudinal direction, from which a plurality of extensions 154 extend toward the gate electrode 124.

A plurality of linear and island ohmic contacts 161 and 165 made of a material such as n + hydrogenated amorphous silicon doped with silicide or n-type impurities at a high concentration are formed on the semiconductor 151. have. The linear contact member 161 has a plurality of protrusions 163, and the protrusions 163 and the island contact members 165 are paired and positioned on the protrusions 154 of the semiconductor 151.

Side surfaces of the semiconductor 151 and the ohmic contacts 161 and 165 are also inclined, and the inclination angle is 30 to 80 degrees.

A plurality of data lines 171 and a plurality of drain electrodes 175 are formed on the ohmic contacts 161 and 165 and the gate insulating layer 140, respectively.                     

The data line 171 mainly extends in the vertical direction to cross the gate line 121 and transmit a data voltage. A plurality of branches extending from the data line 171 toward the drain electrode 175 forms a source electrode 173. The pair of source electrode 173 and the drain electrode 175 are separated from each other and positioned opposite to the gate electrode 123. The drain electrode 175 extends toward the extension portion 137 of the storage electrode line 131 and has an extension portion 177 overlapping the extension portion 137. The gate electrode 123, the source electrode 173, and the drain electrode 175 form a thin film transistor (TFT) together with the exposed portion 154 of the semiconductor 151, and a channel of the thin film transistor It is formed in the exposed portion 154 between the source electrode 173 and the drain electrode 175.

The data line 171 and the drain electrode 175 may also include a conductive film made of a silver metal or an aluminum metal. In addition to the conductive film, chromium (Cr), titanium (Ti), tantalum (Ta), and molybdenum (Mo) may be used. ) And other conductive films made of alloys thereof. Sides of the data line 171 and the drain electrode 175 are also inclined, and the inclination angle is in the range of about 30-80 ° with respect to the horizontal plane.

A passivation layer 180p made of silicon nitride is formed on the data line 171, the drain electrode 175, and the exposed semiconductor portion 154.

An organic layer 180q made of an organic insulating material is formed on the passivation layer 180p. The passivation layer 180p and the organic layer 180q have contact holes 182 exposing a part 179 of the data line 171 and contact holes 186 and 187 exposing a part of the drain electrode 175.

Here, the first contact hole 186 is formed in the passivation film 180p, and the second contact hole 187 is formed in the organic film 180q. The sidewall of the second contact hole 187 is formed to have a predetermined inclination angle with respect to the surface of the insulating substrate 110. That is, it is formed to have a gentle inclination between 30 degrees and 85 degrees with respect to the surface of the insulating substrate 110. The side walls of the contact holes 186 and 187 are formed to have a stepped profile.

In addition, these contact holes 182, 186, and 187 may be formed in various shapes having an angle or a circle.

A plurality of pixel electrodes 190 and a plurality of contact assistants 82 made of ITO or IZO are formed on the organic layer 180q.

The pixel electrode 190 is physically and electrically connected to the drain electrode 175 through the contact holes 186 and 187 to receive a data voltage from the drain electrode 175.

The pixel electrode 190 to which the data voltage is applied rearranges the liquid crystal molecules of the liquid crystal layer between the two electrodes by generating an electric field together with a common electrode (not shown) of the upper panel.

In addition, the pixel electrode 190 and the common electrode form a capacitor (hereinafter referred to as a liquid crystal capacitor) to maintain an applied voltage even after the thin film transistor is turned off. There are other capacitors connected in parallel, called storage electrodes. The storage capacitor is made of the overlap of the pixel electrode 190 and the storage electrode line 131 and the overlap of the pixel electrode 190 and the neighboring gate line 121 (which is referred to as a prior gate line). In order to increase the capacitance of the capacitor, that is, the storage capacitor, an expansion unit 137 extending the storage electrode line 131 is provided to increase the overlap area, while drain connected to the pixel electrode 190 and overlapping the expansion unit 137. An extension 177 of the electrode 175 is placed under the passivation layer 180p to close the distance between the two.

The contact auxiliary member 82 is connected to the end portion 179 of the data line 171 through the contact hole 182. The contact assisting member 82 is not essential to serve to protect adhesiveness between the end portion 179 of the data line 171 and an external device and to protect them, and application thereof is optional.

Next, a method of manufacturing the thin film transistor array panel according to the first exemplary embodiment of the present invention will be described in detail with reference to FIGS. 3 to 11B and FIGS. 1 to 2B.

3, 5, 7, and 9 are layout views at an intermediate stage in the method of manufacturing the thin film transistor array panel according to the exemplary embodiment shown in FIGS. 1 to 2B, and FIGS. 4A and 4B are IVa- FIGS. Sectional views taken along lines IVa 'and IVb-IVb', FIGS. 6A and 6B are cross-sectional views at the next stage of FIGS. 4A and 4B, and FIGS. 8A and 8B are cross-sectional views at the next stage of FIGS. 6A and 6B. 10A and 10B are cross-sectional views in the next step of FIGS. 8A and 8B, and FIGS. 11A and 11B are cross-sectional views illustrating steps of forming contact holes using an optical mask.

First, as shown in FIGS. 3 to 4B, a metal such as chromium, molybdenum, aluminum, silver, or an alloy thereof is deposited on the transparent insulating substrate 110 by sputtering to form a single layer or a plurality of gate metal layers. Form. Thereafter, the metal layer is dry or wet etched by a photolithography process using a mask to form gate lines 121 and 124 on the substrate 110. At this time, the sidewalls of the 121 and 124 are formed to be tapered, and the tapered shape allows the layers formed on them to be in close contact with each other.

Next, as shown in FIGS. 5 to 6B, the gate insulating layer 140 made of silicon nitride or silicon oxide, the semiconductor such as hydrogenated amorphous silicon, and the amorphous silicon doped at high concentration with n-type impurities such as phosphorus (P) are used. Continuous deposition using chemical vapor deposition and patterning in a photolithography process using a photomask to pattern the amorphous silicon layer doped with impurities and the amorphous silicon layer doped with impurities in order to resist the semiconductor layer 151 and the upper portion thereof. The contact layer 164 is formed.

In this case, as shown in FIGS. 11A and 11B, a blocking region 51, a slit region 52, and an opening region 53 are formed in the photomask 50, and correspond to the blocking region 51. The semiconductor layer 151 and the ohmic contact layer 164 are formed in the portion, and the semiconductor layer and the ohmic contact layer are etched in the sustain electrode portion 137, which is a portion corresponding to the opening region 53. 140 is also partially etched so that the gate insulating layer 140 on the storage electrode 137 is thinly formed. The semiconductor layer and the ohmic contact layer are etched in the remaining region including the pixel region corresponding to the slit region 52, and only the gate insulating layer 140 remains below.

Next, as shown in FIGS. 7 to 8B, a conductive layer such as a metal is deposited by a method such as sputtering, and then patterned by a photolithography process using a mask to form a data line 171 and a drain electrode having the source electrode 173. 175 is formed.

Next, the ohmic contact layer which is not covered by the source electrode 173 and the drain electrode 175 is etched to expose the semiconductor layer 154 between the source electrode 173 and the drain electrode 175, and the ohmic contact layer 164 is formed. Separate into parts 161 and 165.

Next, as shown in Figs. 9 to 10B, silicon nitride or silicon oxide is laminated to form a protective film 180p. Thereafter, an organic layer 180q made of an organic insulating material is formed on the passivation layer 180p. The first contact hole 186 and the second contact hole 187 exposing a part of the data line through the passivation layer 180p and the organic layer 180q, respectively, and one end portion of the data line 171 are exposed. Contact holes 182 and 184 are formed.

This will be described in detail with reference to FIGS. 11A and 11B.

As shown in FIGS. 11A and 11B, when the organic layer 180q is exposed and developed using an optical mask 50 having an opening region 53 and a slit region 52, the organic film 180q is illustrated in FIGS. 10A and 10B. Stepped contact holes are formed in the organic film 180q. That is, the slit area 52 of the photomask is a part for smoothing the slope of the sidewall of the contact hole or having a stepped profile in order to alleviate the problem of the step of the contact holes 184 and 187. Arrange so as to correspond to the part to be a side wall.

As such, when the organic layer 180q is exposed through the photomask having the slit region 52, all of the portions to be the contact holes 184 and 187 of the organic layer 180q are exposed, and the portions to be the sidewalls of the contact holes are Partially exposed. Photosensitive means that the polymer is decomposed by light.

Next, when the curing process and the protection layer 180p and the organic layer 180q are etched to the passivation layer 180p and the organic layer 180q, as shown in FIGS. 9 to 10B, the organic layer 180q is formed. Due to its own reflow phenomenon, part of the organic layer 180q and etching of the passivation layer 180p, contact holes 182, 184, 186, and 187 without undercuts may be formed.

Next, as illustrated in FIGS. 1 and 2B, a pixel electrode electrically connected to the thin film transistor is formed on the organic layer through the first contact hole 186 and the second contact hole 187. That is, a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO), is deposited on the substrate 110, and is etched by a photolithography process using a mask to form a drain electrode through the contact holes 186 and 187. The contact auxiliary member 82 connected to one end 179 of the data line is formed through the pixel electrode 190 connected to the 175 and the contact holes 182 and 184.

A thin film transistor array panel according to a second exemplary embodiment of the present invention is illustrated in FIGS. 12 to 13B. Here, the same reference numerals as in the above-described drawings indicate the same members having the same function.

12 is a layout view of a thin film transistor array panel for a liquid crystal display according to a second exemplary embodiment of the present invention, and FIGS. 13A and 13B are cut along the XIIIa-XIIIa 'line and the XIIIb-XIIIb' line of FIG. 12, respectively. It is sectional drawing.

A portion of the second embodiment of the present invention that is different from the first embodiment is a portion where contact holes 186, 187, and 188 are formed, and the extension 177 of the drain electrode contacts the gate insulating layer 140 to expose it. The hole 188 is formed. That is, the contact hole 188 is formed in the part where the extension part 177 of the drain electrode and the organic electrode 137 overlap. The pixel electrode 190 is in contact with the gate insulating layer 140 through the contact hole 188. The thickness of the gate insulating film 140 formed on the sustain electrode 137 is thinner than the thickness of the gate insulating film 140 of another portion. Therefore, the storage capacitance formed between the extension 177 of the drain electrode and the storage electrode 137 connected to the pixel electrode 190 to be described later can be improved.

Next, a method of manufacturing the thin film transistor array panel according to the second exemplary embodiment of the present invention will be described in detail with reference to FIGS. 14 to 22b and FIGS. 12 to 13b.

14, 16, 18, and 20 are layout views at an intermediate stage in the method of manufacturing the thin film transistor array panel according to the exemplary embodiment shown in FIGS. 12 to 13B, and FIGS. 15A and 15B are XVa- FIGS. Cross-sectional views taken along lines XVa 'and XVb-XVb', and FIGS. 17A and 17B are cross-sectional views at the next stage of FIGS. 15A and 15B, and FIGS. 19A and 19B are cross-sectional views at the next stage of FIGS. 17A and 17B. 21A and 21B are sectional views in the next step of FIGS. 19A and 19B, and FIGS. 22A and 22B are sectional views showing a step of forming a contact hole using an optical mask.                     

First, as shown in FIGS. 14 to 15B, a metal such as chromium, molybdenum, aluminum, silver, or an alloy thereof is deposited on the transparent insulating substrate 110 by sputtering to form a single layer or a plurality of gate metal layers. Form. Thereafter, the metal layer is dry or wet etched by a photolithography process using a mask to form gate lines 121 and 124 on the substrate 110. At this time, the sidewalls of the 121 and 124 are formed to be tapered, and the tapered shape allows the layers formed on them to be in close contact with each other.

Next, as shown in FIGS. 16 to 17B, a gate insulating film 140 made of silicon nitride or silicon oxide, a semiconductor such as hydrogenated amorphous silicon, and an amorphous silicon doped at high concentration with an n-type impurity such as phosphorus (P) are used. Continuous deposition using chemical vapor deposition and patterning in a photolithography process using a photomask to pattern the amorphous silicon layer doped with impurities and the amorphous silicon layer doped with impurities in order to resist the semiconductor layer 151 and the upper portion thereof. The contact layer 164 is formed.

Next, as shown in FIGS. 18 to 19B, a conductive layer such as a metal is deposited by a method such as sputtering, and then patterned by a photolithography process using a mask to form a data line 171 and a drain electrode having the source electrode 173. 175 is formed.

In this case, a contact hole 188 through which the gate insulating film is exposed is formed in the extension 177 of the drain electrode.

Next, the ohmic contact layer which is not covered by the source electrode 173 and the drain electrode 175 is etched to expose the semiconductor layer 154 between the source electrode 173 and the drain electrode 175, and the ohmic contact layer 164 is formed. Separate into parts 161 and 165.                     

Next, as shown in FIGS. 20-21B, the silicon nitride or silicon oxide is laminated | stacked, and the protective film 180p is formed. Thereafter, an organic layer 180q made of an organic insulating material is formed on the passivation layer 180p. The first contact hole 186 and the second contact hole 187 exposing a part of the data line through the passivation layer 180p and the organic layer 180q, respectively, and one end portion of the data line 171 are exposed. Contact holes 182 and 184 are formed.

This will be described in detail with reference to FIGS. 22A and 22B.

As shown in FIGS. 22A and 22B, the organic mask 180q includes an optical mask 50 having a blocking region 51, an opening region 53, and a first slit region 52a and a second slit region 52b. When exposed to light and developed using the above step, a stepped contact hole (not shown) is formed in the organic film 180q. That is, the first slit region 52a of the photomask is in contact with a portion for smoothing the slope of the sidewall of the contact hole or having a stepped profile in order to alleviate the problem of the step difference of the contact holes 184 and 187. Arrange so as to correspond to the portion to be the side wall of the hole. The second slit region 52b of the photomask is disposed to correspond to the portion to be a contact hole, and is formed to have a higher transmittance than the first slit region and a lower transmittance than the opening region.

The opening area of the photomask is disposed so as to correspond to a portion which will be a contact hole exposing one end of the data line so as to be completely exposed.

When the organic layer 180q is exposed through the photomask having the first and second slit regions 52a and 52b, all of the portions to be the contact holes 184 of the organic layer exposing one end of the data line are exposed. The portion to be the contact hole 187 of the organic film exposing the drain electrode is partially exposed, and the portion to be the sidewall of the contact hole is partially exposed. Photosensitive means that the polymer is decomposed by light. At this time, the portion to be the contact hole 187 of the organic film exposing the drain electrode is more sensitive than the portion to be the sidewall of the contact hole.

Next, the same as shown in Figs. 20 to 21b when proceeding the curing (Curing) Process and the protective layer (180p), and the organic layer (180q) the etching process to the protective film (180p), and the organic layer (180q), an organic layer (180q By the reflow phenomenon of itself, the organic layer 180q and the etching of the passivation layer 180p, contact holes 182, 184, 186, and 187 without undercuts may be formed. At this time, since the gate insulating layer 140 is overetched through the contact hole 188 through which the gate insulating layer is exposed, the thickness of the expansion portion 177 of the drain electrode is thinner than that of the gate insulating layer 140 of the other portion.

Next, as illustrated in FIGS. 12 to 13B, a pixel electrode electrically connected to the thin film transistor is formed on the organic layer through the first contact hole 186 and the second contact hole 187. That is, a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO), is deposited on the substrate 110, and is etched by a photolithography process using a mask to form a drain electrode through the contact holes 186 and 187. The contact auxiliary member 82 connected to one end 179 of the data line is formed through the pixel electrode 190 connected to the 175 and the contact holes 182 and 184.

A thin film transistor array panel according to a third exemplary embodiment of the present invention is illustrated in FIG. 23. Here, the same reference numerals as in the above-described drawings indicate the same members having the same function.

As shown in FIG. 23, one end portion 129 of the gate line 121 is used to receive a signal transmitted from a gate driving circuit (not shown) and has a width wider than the width of the gate line 121. Can be.

The passivation layer 180p and the organic layer 180q have a plurality of contact holes 181 exposing the end portion 129 of the gate line 121, and the contact hole 181 has an end of the gate line 121. A plurality of contact assisting members 81 are formed in contact with the portion 129. The contact auxiliary member 81 and the contact hole 181 may include a display panel 100 or a flexible circuit board (not shown) in the form of a chip in which a gate driving circuit (not shown) that supplies a signal to the gate line 121 is provided. Required if mounted on On the other hand, when the gate driving circuit is made of a thin film transistor or the like directly on the substrate 110, the contact hole 181 and the contact auxiliary member 81 are not required as in the case of FIGS. 1 to 2B.

Unlike the above first embodiment, the color filter may be formed on the thin film transistor array panel. This structure will be described as a fourth embodiment.

24 is a layout view of a liquid crystal display according to a fourth exemplary embodiment of the present invention, FIG. 25A is a cross-sectional view taken along the line XXVa-XXVa 'of FIG. 24, and FIG. 25B is a cross-sectional view taken along the line XXVb-XXVb' of FIG. 24. .

The thin film transistor array panel for a liquid crystal display according to the fourth embodiment has the following characteristics as compared with the first embodiment.                     

A plurality of three primary color filters 230, for example, the color filters 230 of red 230R, green 230G, and blue 230B, are formed on the passivation layer 180p. The color filter 230 extends vertically along an area between two neighboring data lines 171. The neighboring color filters 230 partially overlap each other on the data line 171 to form a hill.

An organic layer 180q made of an organic insulating material is formed on the color filter 230. The color filter 230 is removed from the contact hole portions 186 and 187 on the drain electrode.

Although the present invention has been described with reference to one embodiment shown in the accompanying drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Could be. Accordingly, the true scope of protection of the invention should be defined only by the appended claims.

The thin film transistor array panel according to the present invention has an advantage in that the aperture ratio can be increased without reducing the sustain capacitance by reducing the thickness of the gate insulating film formed in the overlapping portion between the sustain electrode and the drain electrode.

Claims (15)

  1. delete
  2. delete
  3. delete
  4. delete
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  6. delete
  7. Forming a gate line and a sustain electrode wiring on the substrate,
    Forming a gate insulating film and a semiconductor layer on the gate line and the sustain electrode wiring;
    Forming a data line and a drain electrode on the semiconductor layer;
    Depositing a passivation layer and an organic layer on the data line and the drain electrode;
    Photo-etching the passivation layer and the organic layer to form contact holes exposing the drain electrode;
    Forming a pixel electrode connected to the drain electrode through the contact hole
    Including,
    In the forming of the gate insulating film and the semiconductor layer, the gate insulating film of the first portion overlapping the storage electrode wiring and the drain electrode by photo etching the gate insulating film and the semiconductor layer using an optical mask having a slit region. The thin film transistor array panel manufacturing method of claim 2, wherein the thin film transistor array panel is formed to have a thickness thinner than that of the gate insulating layer of the second portion overlapping the gate line.
  8. In claim 7,
    In the photomask having the slit region, a blocking region and an opening region are formed in addition to the slit region, and a semiconductor layer is formed at a portion corresponding to the blocking region, and a semiconductor layer is etched at a portion corresponding to the slit region. A method of manufacturing a thin film transistor array panel in which a semiconductor layer is etched and a gate insulating layer under the semiconductor layer is etched in a corresponding portion.
  9. delete
  10. delete
  11. delete
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  14. Forming a gate line and a sustain electrode wiring on the substrate,
    Forming a gate insulating film and a semiconductor layer on the gate line and the sustain electrode wiring;
    Forming a data line and a drain electrode on the semiconductor layer, and forming a contact hole in the drain electrode to expose the gate insulating layer;
    Depositing a passivation layer and an organic layer on the data line and the drain electrode;
    Photo-etching the passivation layer and the organic layer formed on the contact hole;
    Forming a pixel electrode connected to the drain electrode through the contact hole
    Including,
    In the photolithography of the passivation layer and the organic layer, the gate insulating layer of the first portion corresponding to the contact hole is formed to have a thickness thinner than that of the gate insulating layer of the second portion corresponding to the gate line using an optical mask having a slit region. The manufacturing method of the thin film transistor array panel.
  15. The method of claim 14,
    A blocking region and a slit region are formed in the photomask, an organic layer and a protective layer are formed in a portion corresponding to the blocking region, and the gate insulating layer is etched in a portion corresponding to the slit region.
KR1020030055419A 2003-08-11 2003-08-11 Thin film transistor array panel and manufacturing method thereof KR101026797B1 (en)

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KR1020030055419A KR101026797B1 (en) 2003-08-11 2003-08-11 Thin film transistor array panel and manufacturing method thereof
US10/915,958 US7190000B2 (en) 2003-08-11 2004-08-11 Thin film transistor array panel and manufacturing method thereof
US11/674,457 US7955908B2 (en) 2003-08-11 2007-02-13 Thin film transistor array panel and manufacturing method thereof
US11/770,012 US7655952B2 (en) 2003-08-11 2007-06-28 Thin films transistor array panel and manufacturing method thereof

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KR101525806B1 (en) * 2008-01-23 2015-06-05 삼성디스플레이 주식회사 Thin film transistor array panel

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07191348A (en) * 1993-12-27 1995-07-28 Rohm Co Ltd Manufacture of liquid crystal display device
JPH1048668A (en) * 1996-08-02 1998-02-20 Sharp Corp Liquid crystal display device and its production
KR100205388B1 (en) 1995-09-12 1999-07-01 구자홍 Liquid crystal display device and its manufacturing method
JP2003029297A (en) * 2001-07-13 2003-01-29 Nec Kagoshima Ltd Active matrix substrate and method of manufacturing the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07191348A (en) * 1993-12-27 1995-07-28 Rohm Co Ltd Manufacture of liquid crystal display device
KR100205388B1 (en) 1995-09-12 1999-07-01 구자홍 Liquid crystal display device and its manufacturing method
JPH1048668A (en) * 1996-08-02 1998-02-20 Sharp Corp Liquid crystal display device and its production
JP2003029297A (en) * 2001-07-13 2003-01-29 Nec Kagoshima Ltd Active matrix substrate and method of manufacturing the same

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