KR100997970B1 - Thin film transistor array panel and manufacturing method thereof - Google Patents

Abstract

The thin film transistor array panel according to the present invention is connected to an insulating substrate, a gate line formed on the insulating substrate, a storage electrode line formed on the insulating substrate and separated from the gate line, and insulated from and crosses the gate line. Predetermined regions of the thin film transistor, the protective film covering the thin film transistor, the pixel electrode formed on the protective film and connected to the thin film transistor, and the protective film corresponding to the storage electrode line are thinner than other portions.

Thin film transistors, holding capacitance, protective film

Description

Thin film transistor array panel and manufacturing method thereof

1 is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view of the thin film transistor array panel of FIG. 1 taken along the line II-II ',

3A is a layout view at an intermediate stage of a method of manufacturing a thin film transistor array panel according to the exemplary embodiments illustrated in FIGS. 1 and 2.

3B is a cross-sectional view taken along the line IIIb-IIIb ′ of FIG. 3A;

4A is a layout view in the next step of FIG. 3A,

4B is a cross-sectional view taken along the line IVb-IVb ′ of FIG. 4A;

FIG. 5A is a layout view in the next step of FIG. 4A, and FIG.

5B is a cross-sectional view taken along the line Vb-Vb ′ of FIG. 5A;

6 is a cross-sectional view at the next step of FIG. 5B,

FIG. 7A is a layout view in the next step of FIG. 6,

FIG. 7B is a cross-sectional view taken along the line VIIb-VIIb ′ of FIG. 7A;

8 is a layout view of a thin film transistor array panel according to another exemplary embodiment of the present invention.

9 is a cross-sectional view taken along the line IX-IX 'of FIG. 8,                 

FIG. 10A is a layout view at an intermediate stage of the method of manufacturing the thin film transistor array panel according to the exemplary embodiment illustrated in FIGS. 8 and 9.

FIG. 10B is a cross-sectional view taken along the line Xb-Xb ′ of FIG. 10A;

11 is a sectional view at the next step of FIG. 10b,

12 is a sectional view at the next step of FIG. 11,

13A is a layout view at the next step of FIG. 12,

FIG. 13B is a cross-sectional view taken along the line XIIIb-XIIIb ′ of FIG. 13A;

14 is a sectional view at the next step of FIG. 13B,

FIG. 15A is a layout view at the next step of FIG. 14;

FIG. 15B is a cross-sectional view taken along the line XVb-XVb ′ of FIG. 15A;

16 is a layout view of a thin film transistor array panel according to another exemplary embodiment of the present invention.

FIG. 17 is a cross-sectional view taken along the line XVII-XVII ′ of FIG. 16;

FIG. 18 is a cross-sectional view of a thin film transistor array panel according to another exemplary embodiment, taken along the line XVII-XVII ′ of FIG. 16.

※ Code explanation about main part of drawing ※

110: insulated substrate 121: gate line

150, 151, 154: semiconductor layers 161, 165: ohmic contact layers

171: data line 175: drain electrode

160, 180, 601, 602: Protective film 190: Pixel electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing metal wirings and thin film transistor array panels, and more particularly, to a method for manufacturing thin film transistor array panels used as a substrate of a liquid crystal display device.

The liquid crystal display device includes a liquid crystal material, a polarizing film, a compensation film, and the like, which are injected between a lower panel including a thin film transistor and an upper panel including a color filter. Such a liquid crystal display forms an electric field by using an electrode in a liquid crystal material injected between two display panels, and displays an image by controlling the intensity of the electric field to adjust the amount of transmitted light.

At this time, in order for the liquid crystal to maintain the arrangement for a predetermined time, a storage capacitor capable of maintaining the voltage until the next voltage is applied after the voltage is applied to the pixel is required.

The holding capacitor can be divided into a shear gate method and an independent wiring method. Here, the front gate method is a method of forming a capacitor by expanding a portion of the gate line and overlapping a conductor pattern to which a predetermined voltage is applied. The independent wiring method is a method of forming a capacitor by applying a constant voltage such as a common voltage after forming a separate wiring.

In order to sufficiently obtain the holding capacity of the holding capacitor, the area of the holding capacitor should be wide. However, liquid crystal displays are currently pursuing high resolution, and the size of the pixels is becoming very small. Therefore, when the area of the storage capacitor is increased, there is a problem that the aperture ratio of the pixel decreases.

In order to solve the above problems, the present invention provides a thin film transistor array panel and a method of manufacturing the same, which can obtain a safe holding capacitance without reducing the aperture ratio of a pixel.

In order to achieve the above object, the present invention forms a thickness of the protective film constituting the storage capacitor thinner than other portions.

Specifically, the thin film transistor array panel according to the present invention includes an insulating substrate, a gate line formed on the insulating substrate, a storage electrode line formed on the insulating substrate and separated from the gate line, a data line, a gate line, and data intersecting the gate line. Predetermined regions of the thin film transistor connected to the line, the protective film covering the thin film transistor, the pixel electrode connected to the thin film transistor and the protective film corresponding to the storage electrode line are thinner than other portions.

The thin film transistor may include a gate electrode formed in a portion or a branch of a gate line, a semiconductor layer overlapping a portion of the gate electrode, a source electrode formed in a portion or a branch of the data line, and at least partially overlapping the semiconductor layer. And a drain electrode overlapping at least a portion thereof and facing the source electrode with respect to the gate electrode.

The semiconductor device may further include an ohmic contact layer formed between the semiconductor layer, the source electrode, and the drain electrode.

In this case, the ohmic contact layer preferably has the same planar pattern as the data line and the drain electrode having the source electrode, and the ohmic contact layer has the same planar pattern as the semiconductor layer except for a predetermined region of the semiconductor layer.

In addition, the sustain electrode line preferably has a plurality of branches.

In addition, the semiconductor layer is preferably formed of polycrystalline silicon or amorphous silicon.

According to another aspect of the present invention, there is provided a method of manufacturing a thin film transistor array panel, including forming a gate line and a storage electrode line on an insulating substrate, forming a gate insulating layer covering the gate line, and forming a semiconductor layer on the gate insulating layer. Forming a resistive contact layer on the semiconductor layer, forming a data line and a drain electrode on the resistive contact layer, forming a passivation film having first and second thickness regions on the substrate, and forming a drain electrode on the passivation layer. And forming a pixel electrode to be connected, wherein the first thickness region is formed to correspond to the storage electrode line.

In this case, the forming of the passivation layer having the first and second thickness regions preferably includes forming a photosensitive passivation layer on the substrate, and exposing and developing the passivation layer through an optical mask having a slit or a translucent layer.                     

In addition, the forming of the protective film having the first and second thickness regions may include forming a protective film on the substrate, forming a photoresist film on the protective film, and exposing and developing the photoresist film through a photomask having a slit or translucent film. Forming a, it is preferable to include the step of etching the protective film using a photosensitive film pattern as a mask.

In this case, the pixel electrode may be connected to the drain electrode through a contact hole formed in the passivation layer.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

Next, a thin film transistor array panel according to an exemplary embodiment of the present invention will be described in detail with reference to the drawings.

[First Embodiment]                     

1 is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view of the thin film transistor array panel of FIG. 1 taken along line II-II ′.

1 and 2, in a thin film transistor array panel according to an exemplary embodiment, a plurality of gate lines 121 and a plurality of storage electrode lines 131 are formed on an insulating substrate 110. It is.

The gate line 121 transmits a gate signal, and a part of each gate line 121 forms a gate electrode 124 of the thin film transistor. The gate electrode 124 is deformed into various shapes to form a gate line. It may also be a protrusion of 121.

The storage electrode line 131 is formed in the pixel area to increase the storage capacitance of the pixel, is separated from the gate line 121, and mainly extends in the horizontal direction. The storage electrode line 131 receives a predetermined predetermined voltage such as a common voltage applied to a common electrode (not shown) of another display panel (not shown). In order to increase the storage capacitance, the storage electrode line 131 may have a plurality of branches (not shown).

The gate line 121 and the storage electrode line 131 may include a conductive film made of an aluminum-based metal such as aluminum (Al) or an aluminum alloy. In addition to the conductive film, other materials such as indium tin oxide (ITO) or IZO may be used. chromium (Cr), titanium (Ti), tantalum (Ta), molybdenum (Mo) and their alloys (eg, molybdenum-tungsten (MoW) alloys) with good physical, chemical and electrical contact with indium zinc oxide It can be formed into a multilayer film structure including another conductive film made of. An example of the combination of the lower layer and the upper layer is chromium / aluminum-neodymium (AlNd) alloy.

A gate insulating layer 140 made of silicon nitride (SiNx) is formed on the 121 and 131.

A plurality of linear semiconductor layers 151 made of hydrogenated amorphous silicon (amorphous silicon is abbreviated a-Si) and the like are formed on the gate insulating layer 140. The linear semiconductor layer 151 mainly extends in the vertical direction and has a plurality of extensions 154 extending therefrom to the gate electrode 124.

The linear semiconductor layer 151 has a portion that is not covered between the source electrode 173 and the drain electrode 175 which will be described later, and the width of the linear semiconductor layer 151 is smaller than the width of the data line 171.

On top of the semiconductor layers 151 and 154 a plurality of linear and island ohmic contacts 161 and 165 made of a material such as n + hydrogenated amorphous silicon doped with a high concentration of silicide or n-type impurities. Is formed. The linear ohmic contact layer 161 has a plurality of protrusions 163, and the protrusion 163 and the island contact layer 165 are paired and positioned on the protrusion 154 of the semiconductor layer 151.

The ohmic contacts 161 and 165 exist only between the semiconductor layers 151 and 154 below the data line 171 and the drain electrode 175 thereon, and serve to lower the contact resistance therebetween. The ohmic contacts 161 and 165 have the same planar pattern as the semiconductor layer 151 except for a predetermined region of the semiconductor layer 151. The predetermined region of the semiconductor layer 154 is a channel portion that forms a channel of the thin film transistor.

The semiconductor layer 151 may increase in width at the portion where the semiconductor layer 151 meets the gate line 121 to enhance insulation between the gate line 121 and the data line 171 (not shown). The portion of the linear semiconductor layer 151 under the data line 171 may not be formed according to the parasitic capacitance between the semiconductor layer 151 and the data line 171.

Sidewalls of the semiconductor layers 151 and 154 and the ohmic contacts 161 and 165 are formed to be tapered so that the layers formed thereon can be tightly adhered to each other.

A plurality of data lines 171 and a plurality of drain electrodes 175 are formed on the ohmic contacts 161 and 165 and the gate insulating layer 140, respectively.

The data line 171 is formed on the linear ohmic contact layer 161 and mainly extends in the vertical direction to cross the gate line 121 and transmit a data voltage. The drain electrode 175 is formed on the island resistive contact layer 165.

A plurality of branches extending from the data line 171 toward the drain electrode 175 forms a source electrode 173. The pair of source and drain electrodes 173 and 175 are separated from each other and positioned opposite to the gate electrode 124. The gate electrode 124, the source electrode 173, and the drain electrode 175 form a thin film transistor (TFT) together with the protrusion 154 of the semiconductor layer 151, and the channel of the thin film transistor The protrusion 154 is formed between the source electrode 173 and the drain electrode 175.

One end of the data line 171 may be wider than the width of the data line 171 to receive a signal transmitted from a data driving circuit (not shown). A portion of the drain electrode 175 connected to the pixel electrode 190 overlaps the storage electrode line 131.

The data line 171 and the drain electrode 175 may also include a conductive film made of a silver metal or an aluminum metal. In addition to the conductive film, chromium (Cr), titanium (Ti), and tantalum (Ta) may be used. , Molybdenum (Mo) and alloys thereof, and the like, and may be formed in a multilayer film structure including another conductive film.

The passivation layer 180 is formed on the substrate to cover the data line 171, the drain electrode 175, and the exposed semiconductor layer 154. In this case, the passivation layer 180 of the portion corresponding to the storage electrode line 131 has a groove (H). That is, the groove is formed by a portion formed thinner than other portions of the protective film 180.

The passivation layer 180 is a-Si: C: O, a-Si: O: F, which is formed of an organic material having excellent planarization characteristics and photosensitivity, and plasma enhanced chemical vapor deposition (PECVD). Low dielectric constant insulating materials such as silicon nitride or inorganic materials.

The passivation layer 180 may be formed of a low dielectric constant organic material having a dielectric constant of 4.0 or less. In this case, the thickness of the passivation layer 180 is thicker than that of the inorganic material, and thus the pixel electrode 190 and the data line 171 are formed. Since the coupling phenomenon does not occur, the edge of the pixel electrode 190, which will be described later, may overlap the data line 171 to maximize the aperture ratio of the pixel.

In the passivation layer 180, a plurality of contact holes 182 exposing end portions of the data line 171 and a plurality of contact holes 185 exposing the drain electrode 175 are formed.

A plurality of pixel electrodes 190 made of indium tin oxide (ITO) or indium zinc oxide (IZO) and a plurality of contact assistants 82 are formed on the passivation layer 180.

The pixel electrode 190 is physically and electrically connected to the drain electrode 175 through the contact hole 185 to receive a data voltage from the drain electrode 175. The pixel electrode 190 to which the data voltage is applied rearranges the liquid crystal molecules between the two electrodes by generating an electric field together with a common electrode (not shown) of another display panel.

The pixel electrode 190 forms a storage capacitor between the storage electrode lines 131 to which a constant voltage such as a common voltage is applied. The holding capacitance is inversely proportional to the distance between both electrodes and is proportional to the area of the corresponding two electrodes. Therefore, since the thickness of the passivation layer 180 between the pixel electrode 190 and the storage electrode line 131 is different, the storage capacitors C1 and C2 formed in the respective portions are different. That is, the holding capacitance C1 of the first thickness region A, which is thinly formed, is larger than the holding capacitance C2 of the second thickness region B, which is thickly formed. Thus, sufficient holding capacity can be obtained without increasing the area of the holding capacitor.                     

When the passivation layer 180 is formed of a low dielectric constant organic material, the aperture ratio may be increased by partially overlapping the pixel electrode 190 with the neighboring gate line 121 and the data line 171.

The contact auxiliary member 82 is connected to one end of the data line 171 through the contact hole 182. When the end portion of the gate line 121 also has a structure for connecting with the driving circuit like the end portion of the data line 171, a gate contact auxiliary member is formed on the passivation layer 180.

The contact assisting member 82 is to compensate for adhesion to the outside, and is particularly necessary when the contact auxiliary member 82 is mounted on the substrate 110 or a fusible circuit board (not shown) in the form of a chip. If it is made of a thin film transistor or the like directly above, it is not formed.

Finally, an alignment layer 11 is formed on the pixel electrode 190, the contact auxiliary member 82, and the passivation layer 180. The alignment layer 11 is subjected to a rubbing process for determining the horizontal direction of the liquid crystal molecules.

Next, the method of manufacturing the thin film transistor array panel for the liquid crystal display described above will be described in detail with reference to FIGS. 3 to 7B and FIGS. 1 and 2.

FIG. 3A is a layout view at an intermediate stage in the method of manufacturing the TFT panel according to the exemplary embodiment shown in FIGS. 1 and 2, FIG. 3B is a cross-sectional view taken along line IIIb-IIIb ′ of FIG. 3A, and FIG. 4A is 3A is a layout view at the next stage, FIG. 4B is a cross-sectional view taken along the line IVb-IVb 'of FIG. 4A, FIG. 5A is a layout view at the next stage of FIG. 4A, and FIG. 5B is a Vb-Vb' of FIG. FIG. 6 is a cross-sectional view taken along the line, FIG. 6 is a cross-sectional view at the next step of FIG. 5B, FIG. 7A is a layout view at the next step of FIG. 6, and FIG. 7B is a cross-sectional view taken along the line VIIb-VIIb ′ of FIG. 7A.

First, as shown in FIGS. 3A and 3B, a metal film is formed by depositing a metal on the transparent insulating substrate 110 by sputtering or the like, and then patterned by a photolithography process to form a gate line 121 and a storage electrode line 131. To form.

The metal may be formed by depositing aluminum, silver-based metal, chromium, titanium, tantalum, molybdenum or an alloy thereof in a single layer or a plurality of layers.

Next, as shown in FIGS. 4A and 4B, the gate insulating layer 140 made of silicon nitride or silicon oxide, the semiconductor such as hydrogenated amorphous silicon, and the amorphous silicon doped with high concentration of n-type impurities such as phosphorus (P) are used. Continuous deposition using chemical vapor deposition (CVD) and patterning by a photolithography process using a mask to pattern an amorphous silicon film doped with impurities and an amorphous silicon film not doped with impurities in order to form a semiconductor layer 151. 154 and an ohmic contact layer 164 thereon.

5A and 5B, a metal is deposited on the substrate by a sputtering method, and then patterned by a photolithography process to form a data line 171 and a drain electrode 175 having the source electrode 173. do.

Subsequently, the ohmic contact layer 164 not covered by the source electrode 173 and the drain electrode 175 is etched to expose the semiconductor layer 154 between the source electrode 173 and the drain electrode 175 to expose the ohmic contact layer 164. ) Into two parts (161, 165).

Next, as shown in FIG. 6, an inorganic material such as silicon nitride and silicon oxide and an organic material having a low dielectric constant are stacked to form a passivation layer 180. Subsequently, after the photoresist is formed on the passivation layer 180, the photoresist is exposed using a photomask MP having a slit, followed by development to form a photoresist pattern PR having different thicknesses. Here, the slit corresponds to the predetermined region S of the storage electrode line 131. At this time, the area of the slit S corresponding to the storage electrode line 131 is changed according to the required storage capacitance. That is, when the storage capacitance is sufficient, only a part of the storage electrode line 131 corresponds to the slit S, and when it is not sufficient, the entire storage electrode line 131 corresponds to the entirety (see Embodiment 2).

In addition, there may be various methods of changing the thickness of the passivation layer 180 in addition to the slits, which will be described in detail in the second embodiment.

Next, as shown in FIGS. 7A and 7B, the passivation layer 180 is etched using the photoresist pattern PR as a mask to form contact holes 182 and 185. At this time, the passivation layer 180 of the portion corresponding to the sustain electrode line 131 is also etched to form a thinner thickness than the passivation layer 180 of the other portion.

When the passivation layer 180 is formed of an organic material having photosensitivity, the passivation layer 180 is exposed using the photomask MP having the slit S, and then developed after the passivation layer 180 is not formed. , 185).

1 and 2, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) is deposited on the passivation layer 180, and then etched by a photolithography process using a mask. The pixel electrode 190 connected to the drain electrode 175 through 185 and the contact auxiliary member 82 connected to one end of the data line 171 through the contact hole 182 are formed. When the driving circuit is directly formed on the substrate 110, the contact auxiliary member 82 is not formed. Then, the alignment layer 11 is formed to cover the pixel electrode 190.

Second Embodiment

The thin film transistor array panel according to the above embodiment may be manufactured by a photolithography process using each thin film as a photoresist pattern as an etching mask, and the thin film transistor array panel may be completed through a manufacturing method according to another embodiment. In this case, the thin film transistor array panel has a structure different from the above embodiment, which will be described in detail with reference to the accompanying drawings.

First, the structure of the completed thin film transistor array panel will be described in detail with reference to FIGS. 8 and 9. FIG. 8 is a layout view of a thin film transistor array panel according to another exemplary embodiment, and FIG. 9 is a cross-sectional view taken along the line IX-IX ′ of FIG. 8.

As shown in Figs. 8 and 9, most single layer structures are the same as Figs. That is, the gate line 121 and the storage electrode line 131 are formed on the insulating substrate 110. The gate insulating layer 140 is formed to cover the gate line 121 and the storage electrode line 131. The semiconductor layer 151 and the ohmic contact layers 161 and 165 are formed on the gate insulating layer 140. The data line 175 and the drain electrode 175 are formed on the ohmic contact layers 161 and 165, and the passivation layer 180 is formed to cover them 171 and 175, and the drain electrode is formed on the passivation layer 180. The pixel electrode 190 connected to the 175 is formed.

However, the data line 171 and the drain electrode 175 have the same planar pattern as the ohmic contacts 161 and 165, and the semiconductor layer 151 has a channel portion between the source electrode 173 and the drain electrode 175. It has the same planar pattern as the ohmic contacts 161 and 165 except that it is connected.

Next, a method of manufacturing the thin film transistor array panel according to the exemplary embodiment illustrated in FIGS. 8 and 9 will be described in detail with reference to FIGS. 8 and 9.

FIG. 10A is a layout view at an intermediate stage in the method of manufacturing the thin film transistor array panel according to the exemplary embodiment illustrated in FIGS. 8 and 9, FIG. 10B is a cross-sectional view taken along the line Xb-Xb ′ of FIG. 10A, and FIG. FIG. 12 is a sectional view at the next step of FIG. 11, FIG. 12A is a sectional view at the next step of FIG. 12, and FIG. 13B is a sectional view taken along the line XIIIb-XIIIb 'of FIG. 13A. 14 is a cross-sectional view at the next step of FIG. 13B, FIG. 15A is a layout view at the next step of FIG. 14, and FIG. 15B is a cross-sectional view taken along the line XVb-XVb ′ of FIG. 15A.

First, as shown in FIGS. 10A and 10B, a metal film is formed by depositing a metal on the transparent insulating substrate 110 by sputtering or the like, and then patterned by a photolithography process to form a gate line 121 and a storage electrode line 131. To form.

The metal may be formed by depositing aluminum, silver-based metal, chromium, titanium, tantalum, molybdenum or an alloy thereof in a single layer or a plurality of layers. In the case of containing aluminum or silver-based metal, it is preferable to form a plurality of layers including other metals having excellent bonding properties such as ITO, IZO, and the like, such as chromium and titanium.

Next, as shown in FIG. 11, an insulating material such as silicon nitride covering the gate line 121 is deposited to form a gate insulating layer 140. Subsequently, amorphous silicon without doping the impurities and amorphous silicon doped with the impurities are deposited on the gate insulating layer 140 to sequentially form the amorphous silicon film 150 without the impurities and the amorphous silicon film 160 with the impurities doped. Laminated by. The amorphous silicon film 150 not doped with impurities is formed of hydrogenated amorphous silicon, and the like, and the amorphous silicon film 160 doped with impurities is heavily doped with an n-type impurity such as phosphorus (P). It is formed of silicon or silicide.

Then, the conductive film 170 is formed by depositing a metal on the amorphous silicon film 160 doped with impurities by sputtering or the like. In this case, the metal may be formed by depositing a metal such as aluminum, silver, chromium, molybdenum, or an alloy thereof in a single layer or a plurality of layers.

Thereafter, a photoresist layer is formed on the conductive layer 170, and then exposed and developed to form photoresist patterns 52 and 54 having different thicknesses.

As described above, there may be various methods of varying the thickness of the photoresist film according to the position, and the transparent mask and the light blocking area as well as the translucent area may be provided in the exposure mask. Yes. The translucent region is provided with a slit pattern, a lattice pattern, or a thin film having a medium transmittance or a medium thickness. When using the slit pattern, it is preferable that the width of the slits and the interval between the slits are smaller than the resolution of the exposure machine used for the photographic process. Another example is to use a photoresist film that can be reflowed. That is, a thin portion is formed by forming a reflowable photoresist pattern with a normal mask having only a transparent region and a light shielding region and then reflowing so that the photoresist film flows into an area where no photoresist remains.

Given the appropriate process conditions, the lower layers may be selectively etched due to the difference in thickness of the photoresist patterns 52 and 54. Accordingly, a plurality of data lines 171 and a plurality of drain electrodes 175 including a plurality of source electrodes 173 as shown in FIGS. 13A and 13B are formed through a series of etching steps, and a plurality of protrusions ( A plurality of linear ohmic contacts 161 each including 163, a plurality of island-like ohmic contacts 165, and a plurality of linear semiconductor layers 151 including a plurality of protrusions 154 are formed.

For convenience of description, the conductive film 170 of the portion where the wiring is to be formed, the amorphous silicon film 160 doped with impurities and the amorphous silicon film 150 without doping impurities are referred to as the wiring portion A. A portion of the impurity doped amorphous silicon film 160 and a portion of the amorphous silicon film 150 not doped with impurities is called a channel portion B, and impurities located in regions other than the channel and wiring portions are formed. The portion of the doped amorphous silicon film 160 and the doped amorphous silicon film 150 will be referred to as the other portion (C).

One example of the order of forming such a structure is as follows.

First, (1) removing the impurity amorphous silicon film 160 and the amorphous silicon film 150 in the other part (C), (2) removing the photosensitive film 54 located in the channel part (B), and (3) the channel part ( The impurity amorphous silicon film 160 located in B) is removed, and (4) the photosensitive film 52 located in the wiring portion A is removed.

Other methods include (1) removing the photosensitive film 54 located in the channel portion B, (3) removing the impurity amorphous silicon film 160 and the amorphous silicon film 150 located in the other portion C, and (4) Removing the conductive film located in the channel portion B, (5) removing the photoresist film 52 located in the wiring region A, and (6) removing the impurity amorphous silicon film 160 located in the channel portion B. You can also proceed.

This section describes the first example.

First, as shown in FIG. 12, the conductive film 170 exposed to the other region C is removed by wet etching or dry etching, and the other portion C of the amorphous silicon film 160 doped with impurities thereunder. Expose

The data line 171 and the drain electrode 175 are still attached. In the case of using dry etching, the upper portions of the photoresist films 52 and 54 may be cut to a certain thickness.

Next, the amorphous silicon film 160 doped with impurities in the other portion C and the amorphous silicon film 150 without dopants under the impurities are removed, and the photoresist film 54 of the channel portion B is removed. It removes and exposes the lower conductive film 174.

Removal of the photoresist of the channel portion B may be performed simultaneously with or separately from the removal of the amorphous silicon layer 160 doped with impurities in the other region C and the amorphous silicon layer 150 without the impurities. Residue of the photoresist film 54 remaining in the channel region B is removed by ashing. In this step, the semiconductor layers 151 and 154 are completed.

Here, when the conductive film 170 is a material that can be dry etched, the manufacturing process may be performed by continuously dry etching the amorphous silicon layer 160 doped with impurities below and the amorphous silicon layer 150 doped with impurities. In this case, it may or may not be performed in an in-situ manner in which dry etching is sequentially performed on the three layers 170, 160, and 150 in the same etching chamber.

Next, as shown in FIGS. 13A and 13B, the conductive layer 174 located in the channel portion B and the amorphous silicon layer 164 doped with impurities are etched and removed. In addition, the photosensitive film 52 of the remaining wiring portion A is also removed.

In this case, the upper portion of the amorphous silicon film that is not doped with impurities in the channel portion B may be partially removed to reduce the thickness, and the photosensitive film 52 of the wiring portion A may be etched to some extent.

In this way, each conductive film 174 is completed while being separated into one data line 171 and a plurality of drain electrodes 175, and the amorphous silicon film 164 doped with impurities also includes the linear ohmic contact layer 161. Completed by dividing into island resistive contact layer 165

Next, as shown in FIG. 14, an organic material having excellent planarization characteristics and a photosensitive chemical property to cover the semiconductor layer 154 that is not covered by the data lines 171 and 173 and the drain electrode 175, and a plasma chemical vapor phase. A protective film 180 made of a low dielectric constant insulating material such as a-Si: C: O, a-Si: O: F, or silicon nitride, which is an inorganic material, is formed by deposition.

Thereafter, after the photoresist is formed on the passivation layer 180, the photoresist is exposed using a photomask MP having a slit S, followed by development to form a photoresist pattern PR having a different thickness. Here, the slit S corresponds to the entire sustain electrode line 131.

Here, if the storage capacitance is sufficient, it corresponds to the predetermined region of the storage electrode line 131 as in the first embodiment.

As shown in FIGS. 15A and 15B, the passivation layer 180 is etched using the photoresist pattern PR as a mask to form contact holes 182 and 185. At this time, the passivation layer 180 of the portion corresponding to the sustain electrode line 131 is also etched to form a thickness thinner than the passivation layer 180 of the other portion.

When the passivation layer 180 is formed of an organic material having photosensitivity, the passivation layer 180 is exposed using the photomask MP having the slit S, and then developed after the passivation layer 180 is not formed. , 185).

Subsequently, as shown in FIGS. 8 and 9, a transparent conductive material such as ITO or IZO is deposited on the substrate 110, and is etched by a photolithography process using a mask to etch one end of the data line through the contact hole 182. The contact auxiliary member 82 connected to the portion 179 and the pixel electrode 190 connected to the drain electrode 175 through the contact hole 185 are formed.

In the case of forming the chip-type gate driving circuit on the substrate, the contact auxiliary member is not formed. In the case where the passivation layer 180 is formed of the organic layer, the pixel electrode 190 may be extended to the upper portion of the data line 171, thereby increasing the aperture ratio of the pixel.

[Examples 3 and 4]

16 is a layout view of a thin film transistor array panel according to a third exemplary embodiment of the present invention, FIG. 17 is a cross-sectional view taken along the line XVII-XVII ′ of FIG. 16, and FIG. 18 is a thin film transistor according to the fourth exemplary embodiment of the present invention. A cross-sectional view of the display panel, taken along a line XVIII-XVIII 'of FIG. 16.

In the third embodiment, unlike the first and second embodiments, the semiconductor layer is formed using polycrystalline silicon.

Referring to FIGS. 16 and 17, a blocking film 111 made of silicon oxide or the like is formed on the transparent insulating substrate 110. The semiconductor layer 150 is formed on the blocking layer 111 and includes a source region 153, a drain region 155, and a channel region 154 that is not doped with impurities. A lightly doped drain 152 is formed between the source region 153 and the channel region 154 and the drain region 155 and the channel region 154 of the semiconductor layer.

The lightly doped region 152 prevents leakage current or punch through. The source region 153 and the drain region 155 are heavily doped with conductive impurities, and the lightly doped region 152 has a lower concentration than the source and drain regions 153 and 155.

The conductive impurity is a P-type or N-type impurity, and boron (B), gallium (Ga), etc. are used as the P-type conductivity, and phosphorus (P), arsenic (As), etc. are used as the N-type impurity. This can be used.

A gate insulating layer 140 made of silicon nitride, silicon oxide, or the like is formed on the semiconductor layer 150. In addition, a gate line 121 extending in one direction is formed on the gate insulating layer 140, and a portion of the gate line 121 extends to overlap the channel region 154 of the semiconductor layer 150. The portion overlapping the channel region 154 is used as the gate electrode 124 of the thin film transistor. The gate electrode 124 may overlap (not shown) the lightly doped region 152.

In addition, the storage electrode line 131 for increasing the storage capacitance of the pixel is parallel to the gate line 121 and is formed in the same layer with the same material. A portion of the storage electrode line 131 overlapping the semiconductor layer 150 becomes the storage electrode 133, and the semiconductor layer 150 overlapping the storage electrode 133 becomes the storage electrode region 157. One end of the gate line 121 may be formed wider than the width of the gate line 121 in order to connect to an external circuit (not shown).

The first interlayer insulating layer 601 is formed on the gate insulating layer 140 including the gate line 121 and the storage electrode line 131. The first interlayer insulating layer 601 includes first and second contact holes 161 and 162 exposing the source region 153 and the drain region 155, respectively.

A data line 171 is formed on the first interlayer insulating layer 601 to cross the gate line 121 to define a pixel area. A portion or branched portion of the data line 171 is connected to the source region 153 through the first contact hole 161, and the portion 173 connected to the source region 153 is a source electrode (eg, a thin film transistor). 173). One end of the data line 171 may be formed wider than the width of the data line 171 to connect to an external circuit.

A drain electrode 175 is formed on the same layer as the data line 171 and is separated from the source electrode 173 and connected to the drain region 155 through the second contact hole 162.

A second interlayer insulating layer 602 is formed on the first interlayer insulating layer 601 including the drain electrode 175 and the data line 171. The second interlayer insulating layer 602 has a third contact hole 163 exposing the drain electrode 175.

The thickness of the second interlayer insulating film 602 overlapping the storage electrode lines 131 and 133 is thinner than that of other portions. When the storage capacitance is sufficient, as in the first embodiment, only a portion of the thickness of the second interlayer insulating layer 602 corresponding to the storage electrode lines 131 and 133 may be thinly formed.

As such, the process of forming a thin portion of the second interlayer insulating layer 602 may be simultaneously performed when the third contact hole 163 is formed in the second interlayer insulating layer 602. In this case, as in the first and second embodiments, the photomask is formed together with the contact hole by using an optical mask having a slit or a translucent film.

In addition, as shown in FIG. 18, the thickness of the first interlayer insulating film 601 may be formed thin to increase the storage capacitance. In this case, when the first and second contact holes 161 and 162 are formed, the thickness may be reduced by using a slit or the like. In addition, the thickness of the first and second interlayer insulating layers may be made thin (not shown), thereby making the thickness of the interlayer insulating layer thinner, thereby maximizing the storage capacitance.

The pixel electrode 190 connected to the drain electrode 175 is formed on the second interlayer insulating layer 602 through the third contact hole 163, and the alignment layer 11 is formed on the pixel electrode 190. have.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, when the thickness of the protective film is different, the holding capacity can be easily increased without adding a separate process, thereby providing a high quality thin film transistor array panel.

Claims (10)

Insulation board, A gate line formed on the insulating substrate, A storage electrode line formed on the insulating substrate and separated from the gate line; A data line insulated from and intersecting the gate line, A thin film transistor connected to the gate line and the data line, A protective film covering the thin film transistor, A pixel electrode formed on the passivation layer and connected to the thin film transistor; And the passivation layer is formed to be thinner than the thickness of the portion corresponding to the storage electrode line. In claim 1, The thin film transistor may include a gate electrode connected to the gate line, A semiconductor layer overlapping the gate electrode; A source electrode connected to the data line and overlapping the semiconductor layer; And a drain electrode overlapping the semiconductor layer and facing the source electrode with respect to the gate electrode. In claim 1, And a resistive contact layer formed between the semiconductor layer and the source electrode and the drain electrode. 4. The method of claim 3, The ohmic contact layer has the same planar pattern as the data line and the drain electrode having the source electrode, The semiconductor layer includes a portion overlapping the data line and the drain electrode having the source electrode, and a portion positioned between the source electrode and the drain electrode. A thin film transistor array panel having the same planar pattern as a portion overlapping the data line having the source electrode and the drain electrode. In claim 1, The storage electrode line has a plurality of branches. In claim 2, And the semiconductor layer is formed of polycrystalline silicon or amorphous silicon. Forming a gate line and a storage electrode line on the insulating substrate, Forming a gate insulating film covering the gate line; Forming a semiconductor layer on the gate insulating film, Forming an ohmic contact layer over the semiconductor layer; Forming a data line and a drain electrode on the ohmic contact layer; Forming a protective film having first and second thickness regions on the insulating substrate, Forming a pixel electrode connected to the drain electrode on the passivation layer, The first thickness region is formed to correspond to the storage electrode line. The forming of the passivation layer having the first and second thickness regions may be performed by etching a photoresist pattern formed through a photomask having a slit or translucent layer with a mask, or exposing and developing the passivation layer with the slit or translucent layer. A method of manufacturing a thin film transistor array panel comprising the step of forming. delete delete In claim 7, The pixel electrode is connected to the drain electrode through a contact hole formed in the passivation layer.

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