KR20060128601A - Thin film transistor array panel - Google Patents

Abstract

A thin film transistor array panel is provided to prevent a leakage current generated by a backlight light applied to semiconductors, by covering the semiconductors with a gate metal layer. Gate lines(121) are formed on an insulating substrate and include gate electrodes(124). Data lines(171) cross the gate lines, being insulated, and include source electrodes(173). Drain electrodes(175) are opposite to the source electrodes on the gate lines. Semiconductors are formed under the data lines, and have protruded parts(154) extended under the drain electrodes. A part of the semiconductor placed at the drain electrode side, out of the data lines, is placed at the inside of an area occupied by the gate lines including the gate electrodes.

Description

Thin film transistor array panel

1 is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention.

2 and 3 are cross-sectional views of lines II-II and III-III of FIG. 1, respectively.

4 is a layout view of a thin film transistor array panel in a first step of manufacturing the thin film transistor array panel illustrated in FIGS. 1 to 3.

5A and 5B are sectional views taken along line VA-VA and VB-VB in FIG. 4, respectively.

6A and 6B are cross-sectional views taken along line VA-VA and VB-VB in Fig. 4, respectively, and are cross-sectional views in the next steps of Figs. 5A and 5B,

FIG. 7 is a layout view of a thin film transistor array panel in the next step of FIGS. 6A and 6B.

8A and 8B are cross-sectional views taken along line VIIIA-VIIIA and VIIIB-VIIIB in FIG. 7, respectively.

9A, 10A, 11A and 9B, 10B, 11B are cross-sectional views of lines VIIIA-VIIIA and VIIIB-VIIIB in FIG. 7, respectively, illustrating the following steps in the order of the process, FIGS.

12A and 12B are cross-sectional views of a thin film transistor array panel in the next steps of FIGS. 11A and 11B,

13 is a layout view of a thin film transistor array panel according to another exemplary embodiment of the present invention.

FIG. 14 is a pattern diagram of a photomask used when manufacturing the thin film transistor array panel of FIG. 13.

15 is a layout view of a thin film transistor array panel according to another exemplary embodiment of the present invention.

FIG. 16 is a pattern diagram of a photomask used when manufacturing the thin film transistor array panel of FIG. 15.

17 is a layout view of a thin film transistor array panel according to another exemplary embodiment of the present invention.

18 is a cross-sectional view taken along line XVIII-XVIII in FIG. 17.

<Explanation of symbols for the main parts of the drawings>

110: insulating substrate 124: gate electrode

131: storage electrode line 140: gate insulating film

150: intrinsic amorphous silicon layer 160: impurity amorphous silicon layer

170: conductor layer 173: source electrode

175: drain electrode 177: conductor for storage capacitor

180: protective film 181, 182, 185: contact hole

190: pixel electrode 81, 82: contact auxiliary member

The present invention relates to a thin film transistor array panel.

The thin film transistor array panel is used as a circuit board for independently driving each pixel in a liquid crystal display device, an organic EL (electro luminescence) display device, or the like. The thin film transistor array panel has a gate line that transmits a scan signal and a data line that transmits an image signal, and includes a thin film transistor connected to the gate line and the data line, a pixel electrode connected to the thin film transistor, and a gate covering and insulating the gate line. And an insulating film, a thin film transistor, and a protective film for insulating the data line. The thin film transistor includes a semiconductor forming a gate electrode and a channel as part of a gate line, a source electrode and a drain electrode as part of a data line, a gate insulating film, a protective film, and the like. The thin film transistor is a switching device that transfers or blocks an image signal transmitted through a data line to a pixel electrode according to a scan signal transmitted through a gate line.

Manufacturing a thin film transistor array panel requires several photolithography processes. However, the greater the number of photolithography processes, the more complicated the manufacturing process and the higher the manufacturing cost. Accordingly, efforts have been made to reduce the number of photolithography processes required to manufacture thin film transistor array panels.

On the other hand, the thin film transistor preferably has as little current (leakage current) as possible when off. However, leakage current is generated due to the characteristics of the device itself or external factors. In particular, when the semiconductor layer constituting the thin film transistor receives light, leakage current increases greatly due to the generation of photoelectrons.

An object of the present invention is to solve this problem to reduce the leakage current of the thin film transistor.

In order to solve this problem, in the present invention, the semiconductor constituting the thin film transistor is covered with a gate metal.

Specifically, an insulating substrate, a gate line formed on the insulating substrate and including a gate electrode, a data line insulated from and intersecting with the gate line, including a source electrode, a drain electrode facing on the source electrode and the gate line, A semiconductor layer formed under the data line and having a protrusion extending to a lower portion of the drain electrode, wherein a portion of the semiconductor, positioned beyond the data line and positioned toward the drain electrode, is occupied by a gate line including the gate electrode; A thin film transistor array panel located inside the area is prepared.

According to an embodiment of the present invention, the drain electrode is located inside an area occupied by the semiconductor.

According to an embodiment of the present invention, the protrusion of the semiconductor is located in an area occupied by the gate line including the gate electrode.

According to an embodiment of the present invention, the pixel electrode may further include a pixel electrode connected to the drain electrode, wherein the pixel electrode has a branch extending toward the drain electrode and the branch is connected to the drain electrode.

According to an embodiment of the present invention, the pixel electrode does not overlap the gate line at portions except the branch portion.

According to an embodiment of the present invention, the pixel electrode is in contact with the top and side surfaces of the drain electrode, and the pixel electrode is in contact with the semiconductor.

Or an insulating substrate, a gate line formed on the insulating substrate and including a gate electrode, a gate insulating film formed on the gate line, a linear semiconductor formed on the gate insulating film and having a protrusion, and formed on the linear semiconductor, A data line intersecting a gate line and including a source electrode, a drain electrode formed on the protrusion of the linear semiconductor, a passivation layer formed on the data line and the drain electrode and having a contact hole exposing the drain electrode, and formed on the passivation layer And a pixel electrode connected to the drain electrode through the contact hole, and a portion of the linear semiconductor, positioned beyond the data line and positioned toward the drain electrode, within an area occupied by a gate line including the gate electrode. The TFT array panel positioned and arranged.

According to an embodiment of the present invention, the drain electrode is located inside an area occupied by the semiconductor.

According to an embodiment of the present invention, the protrusion of the semiconductor is located in an area occupied by the gate line including the gate electrode.

According to an embodiment of the present invention, the pixel electrode has a branch extending toward the drain electrode, the branch is connected to the drain electrode, and the pixel electrode does not overlap the gate line except at the branch.

According to an embodiment of the present invention, the contact hole exposes the drain electrode and the semiconductor around the drain electrode, and the pixel electrode is in contact with the top and side surfaces of the drain electrode exposed through the contact hole. And the semiconductor exposed through the contact hole.

According to an embodiment of the present invention, the pixel electrode has a branch portion, the branch portion is connected to the drain electrode and the semiconductor, and only a part of the portion exposed through the contact hole of the semiconductor is covered with the pixel electrode. .

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

A thin film transistor array panel for a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail.

1 is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention, and FIGS. 2 and 3 are cross-sectional views taken along lines II-II and III-III of FIG. 1, respectively.

As shown in FIGS. 1 to 3, the layer structure of the thin film transistor array panel for the liquid crystal display according to the present exemplary embodiment is extended in width to connect the plurality of gate electrodes 124 to an external device on the substrate 110. A plurality of gate lines 121 including extended portions 129 are formed, and a plurality of storage electrode lines 131 electrically separated from the gate lines 121 are formed.

The gate line 121 and the storage electrode line 131 include two layers having different physical properties, that is, the lower layers 121p and 131p and the upper layers 121q and 131q thereon. The upper layer 121q of the gate line is made of a metal having a low specific resistance, such as aluminum (Al) or an aluminum alloy, so as to reduce delay or voltage drop of the gate signal. In contrast, the lower layer 121p is a material having excellent physical, chemical, and electrical contact properties with other materials, particularly ITO and IZO, such as molybdenum (Mo), molybdenum alloy, chromium (Cr), tantalum (Ta), and titanium (Ti). ) And so on. An example of the combination of the lower layer 121p and the upper layer 121q may be a chromium / aluminum-neodymium (Nd) alloy.

Like the gate line 121, the storage electrode line 131 also includes a lower layer 131p and an upper layer 131q, and the storage electrode line 131 receives a predetermined voltage such as a common voltage from the outside. The storage electrode line 131 may be omitted when the storage capacitor generated due to the overlap between the pixel electrode 190 and the gate line 121 is sufficient. In this case, the storage capacitor conductor 177, which will be described later, is also omitted.

Side surfaces of the gate films 121 and the lower electrodes 121p and 131p and the upper layers 121q and 131q of the storage electrode line 131 are inclined, respectively, and the inclination angle is about 30 to 80 degrees with respect to the surface of the substrate 110. .

A gate insulating layer 140 made of silicon nitride is formed on the gate line 121.

A plurality of linear semiconductors 151 made of hydrogenated amorphous silicon or the like are formed on the gate insulating layer 140, and the linear semiconductors 151 mainly extend in the vertical direction, and extend in the form of branches from the gate electrode 124. A plurality of protrusions 154 covering the tops are formed. In addition, a linear semiconductor 157 covering a part of the sustain electrode line 131 is also formed.

The protrusion 154 of the linear semiconductor 151 overlaps with the gate electrode 124, and is located inside the area occupied by the gate line 121 including the gate electrode 124 on the surface of the insulating substrate 110. It is formed to lie. That is, the edge of the protrusion 154 of the linear semiconductor 151 is placed in an area surrounded by the edge of the gate line 121 including the gate electrode 124. Therefore, when viewed from below the insulating substrate 110, the protrusion 154 is not visible due to the gate electrode 124 and the gate line 121.

A plurality of linear and island resistive contact members 161, 165, and 167 formed of a material such as n + hydrogenated amorphous silicon in which silicide or n-type impurities are heavily doped is formed on the semiconductor 151. The linear contact member 161 has a plurality of protrusions 163, and the protrusions 163 and the island contact members 165 are paired and positioned on the protrusions 154 of the semiconductor 151. Meanwhile, an island contact member 167 is formed on the island semiconductor 157.

 Side surfaces of the semiconductors 151 and 157 and the ohmic contacts 161, 165 and 167 are also inclined and have an inclination angle of 30 to 80 degrees.

A plurality of data lines 171, a plurality of drain electrodes 175, and a plurality of storage capacitor conductors 177 are formed on the ohmic contacts 161, 165, 167, and the gate insulating layer 140, respectively.

The data line 171 mainly extends in the vertical direction and crosses the gate line 121 to transmit a data voltage. Each data line 171 includes an expansion unit 179 which is extended in width for connection with an external device. Most of the data line 171 is located in the display area, but the extension 179 of the data line 171 is located in the peripheral area.

A plurality of branches extending in a branch shape from each data line 171 toward the drain electrode 175 forms the source electrode 173. The pair of source electrode 173 and the drain electrode 175 are separated from each other and positioned opposite to the gate electrode 124.

Here, the data line 171, the drain electrode 175, and the conductor 177 for the storage capacitor are completely placed on the upper surfaces of the ohmic contacts 161, 165, and 167. In particular, the drain electrode 175 has a planar shape substantially the same as the island-type ohmic contact 165 that is completely placed on the protrusion 154 of the linear semiconductor 151. Accordingly, the edge of the drain electrode 175 is disposed in an area surrounded by the edge of the protrusion 154 of the linear semiconductor 151. When viewed from the bottom of the insulating substrate 110, the gate electrode 124 and the gate line 121 are disposed. The drain electrode 175 is not visible.

The gate electrode 124, the source electrode 173, and the drain electrode 175 form a thin film transistor together with the protrusion 154 of the semiconductor 151, and the channels of the thin film transistor are the source electrode 173 and the drain electrode 175. It is formed in the projection 154 therebetween.

The storage capacitor conductor 177 overlaps a part of the storage electrode line 131 and is formed on the island-like semiconductor 157 and the island-type ohmic contact 167.

The data line 171, the drain electrode 175, and the conductive capacitor conductor 177 have two conductive films having different physical properties, that is, the lower films 171p, 175p, and 177p, and the upper films 171q and 175q thereon. 177q). The upper layers 171q, 175q, and 177q are made of a low resistivity metal such as aluminum based metal, silver based metal, copper based metal, etc. to reduce signal delay or voltage drop. 177p) is preferably made of refractory metals such as molybdenum, chromium, tantalum and titanium or alloys thereof. A good example of such a combination is a chromium or molybdenum (alloy) bottom film and an aluminum (alloy) top film, the top film 175q of the drain electrode 175 and the top film of the end portion 179 of the data line 171. A part of (179q) is removed to expose the lower films 179p and 175p. However, the data line 171, the drain electrode 175, and the conductor 177 for the storage capacitor may have a single film structure made of the aforementioned materials, and may be made of various other various metals or conductors. have.

The lower layers 171p, 175p, and 177p and the upper layers 171q, 175q, and 177q of the data line 171, the drain electrode 175, and the storage capacitor conductor 177 also have the gate line 121 and the storage electrode line ( Like 131, its sides are inclined at an angle of about 30-80 degrees.

The ohmic contacts 161, 165, and 167 exist only between the semiconductors 151 and 157 thereunder and the data line 171, the drain electrode 175, and the storage capacitor conductor 177 thereon. It lowers resistance. The linear semiconductor 151 has an exposed portion between the source electrode 173 and the drain electrode 175, and is not covered by the data line 171 and the drain electrode 175, and the island type semiconductor 157 is used for a storage capacitor. It is at the bottom of the ohmic contact 167 at the bottom of the conductor 177.

On the data line 171, the drain electrode 175, the conductive capacitor 177 for the storage capacitor, and the exposed portion of the semiconductor 151, an organic material having excellent planarization characteristics and photosensitive properties, plasma enhanced chemical vapor deposition (PECVD) A protective film 180 made of a low dielectric constant insulating material having a dielectric constant of 4.0 or less, such as a-Si: C: O, a-Si: O: F, formed by chemical vapor deposition, or an inorganic material, such as silicon nitride, is formed.

The passivation layer 180 includes a plurality of contact holes 185 exposing the drain electrode 175, the conductive capacitor 177 for the storage capacitor, and the lower layers 175p, 177p, and 179p of the extension 179 of the data line 171, respectively. , 187, and 182 are formed, and a plurality of contact holes 181 are formed in the passivation layer 180 and the gate insulating layer 140 to expose the lower layer 129p of the extension portion 129 of the gate line 121. have.

A plurality of pixel electrodes 190 and a plurality of contact auxiliary members 81 and 82 are formed on the passivation layer 180.

The pixel electrode 190 is made of a transparent conductive material such as ITO or IZO.

The pixel electrode 190 is physically and electrically connected to the drain electrode 175 and the storage capacitor conductor 177 through the contact holes 185 and 187, respectively, so that the data voltage is applied from the drain electrode 175. Transfer data voltage to 177.

The pixel electrode 190 to which the data voltage is applied rearranges the liquid crystal molecules of the liquid crystal layer between the two electrodes by generating an electric field together with the common electrode of another display panel to which the data voltage is applied.

In addition, the pixel electrode 190 and the common electrode form a capacitor to maintain an applied voltage even after the thin film transistor is turned off. In order to enhance the voltage holding capability, another capacitor connected in parallel with the liquid crystal capacitor is disposed and a "storage capacitor" electrode) ". The storage capacitor is formed by overlapping the pixel electrode 190 and the storage electrode line 131. The storage capacitor 177 is placed under the passivation layer 180 to increase the storage capacitance.

The pixel electrode 190 also overlaps the neighboring gate line 121 and the data line 171 to increase the aperture ratio, but may not overlap.

The contact auxiliary members 81 and 82 are connected to the extension part 129 of the gate line and the extension part 179 of the data line through contact holes 181 and 182, respectively. The contact auxiliary members 81 and 82 serve to protect adhesiveness between the extension portions 129 and 179 of the gate line 121 and the data line 171 and the external device.

These contact auxiliary members 81 and 82 are also formed of a transparent conductor such as ITO or IZO.

As described above, when the protrusion 154 of the linear semiconductor 151 is formed so as to lie inside the area occupied by the gate electrode 124 and the gate line 121, the backlight light is provided to the gate electrode 124 and the gate line 121. It is blocked by) and does not reach the protrusion 154. Therefore, it is possible to prevent the leakage current caused by the photoelectron in the state where the thin film transistor is turned off.

In this case, the entirety of the protrusion 154 of the linear semiconductor 151 does not necessarily need to be placed inside the area occupied by the gate line 121 including the gate electrode 124, but at least includes the source electrode 173. The gate line 121 including the gate electrode 124 is occupied by the semiconductor under the drain electrode 175, including the channel semiconductor, which is a portion between the data line 171 and the drain electrode 175. It is preferable to form so that it may lie in the inside of the area to make. In other words, the semiconductor positioned away from the data line 171 toward the drain electrode 175 may be formed so as to lie inside the area occupied by the gate line 121 including the gate electrode 124.

Then, referring to FIGS. 4 to 12B and FIGS. 1, 2 and 3 for a method of manufacturing the thin film transistor array panel for the liquid crystal display device shown in FIGS. 1, 2 and 3 according to an embodiment of the present invention. It will be described in detail.

4 is a layout view of a thin film transistor array panel in a first step of manufacturing the thin film transistor array panel illustrated in FIGS. 1 to 3, and FIGS. 5A and 5B are cross-sectional views taken along line VA-VA and VB-VB in FIG. 4, respectively. 6A and 6B are cross-sectional views of the VA-VA line and the VB-VB line in FIG. 4, respectively, and are cross-sectional views in the next steps of FIGS. 5A and 5B, and FIG. 7 is a thin film transistor in the next steps of FIGS. 6A and 6B. 8A and 8B are cross-sectional views of lines VIIIA-VIIIA and VIIIB-VIIIB in FIG. 7, and FIGS. 9A, 10A, 11A and 9B, 10B and 11B are lines VIIIA-VIIIA in FIG. 7, respectively. And FIG. 8A and FIG. 8B next steps as a cross-sectional view for the VIIIB-VIIIB line, and FIG. 12A and FIG. 12B are cross-sectional views of the thin film transistor array panel in the next step of FIGS. 11A and 11B.

First, two layers of the metal film, that is, the lower metal film and the upper metal film, are sequentially stacked on the insulating substrate 110 made of transparent glass. The upper metal film is made of an aluminum-based metal such as an Al-Nd alloy, and preferably has a thickness of about 2,500 kPa. The Al-Nd sputtering target preferably contains 2 atm% Nd.

As shown in FIGS. 4 and 5A and 5B, the upper metal film and the lower metal film are sequentially patterned to form a gate line 121 including the plurality of gate electrodes 124, and electrically connected to the gate line 121. A plurality of separated storage electrode lines 131 are formed.

6A and 6B, a gate insulating film 140 made of silicon nitride, an intrinsic amorphous silicon layer, and an impurity amorphous silicon layer are successively stacked, followed by two metal layers, that is, a lower layer and an upper layer. After the film is laminated in order by sputtering, the photoresist film 210 is coated. Thereafter, light is irradiated onto the photosensitive film 210 through a photomask and then developed. The thickness of the developed photosensitive film is formed differently depending on the position as shown in FIGS. 8A and 8B. In this case, the channel portion C of the thin film transistor, that is, the first portion 214 located between the source electrode 173 and the drain electrode 175, of the photoresist patterns 212 and 214 may have a portion A formed therein. The thickness is made smaller than the second part located at, and all the photoresist of the remaining part B is removed. At this time, the ratio of the thickness of the photoresist film 214 remaining in the channel portion C and the thickness of the photoresist film 212 remaining in the A portion should be different depending on the process conditions in the etching process, which will be described later. Preferably, the thickness of 214 is 1/2 or less of the thickness of the second portion 212.

As described above, there may be various methods of varying the thickness of the photoresist film according to the position. For example, the transmissive region as well as the transparent region and the light shielding region may be provided in the exposure mask. The translucent region is provided with a slit pattern, a lattice pattern, or a thin film having a medium or medium transmittance. When using a slit pattern, it is preferable that the width | variety of a slit, and the space | interval between slits is smaller than the resolution of the exposure machine used for a photography process. Another example is to use a photoresist film that can be reflowed. That is, a thin portion is formed by forming a reflowable photoresist pattern with a normal mask having only a transparent region and a light shielding region and then reflowing so that the photoresist film flows into an area where no photoresist remains.

Subsequently, the photoresist patterns 212 and 214 and the underlying layers are etched. At this time, the data line in the region A and the films below it remain as it is, only the semiconductor remains in the channel portion C, and the gate insulating layer 140 is exposed in the remaining portion B.

First, as shown in FIGS. 9A and 9B, the exposed conductors of the remaining portion B are removed to expose the resistive contact member 160 thereunder. In this process, both a dry etching method and a wet etching method may be used. In this case, the conductor may be etched and the photoresist films 212 and 214 may be hardly etched. However, in the case of dry etching, it is difficult to find a condition in which only the conductor is etched and the photoresist layers 212 and 214 are not etched, so that the photoresist patterns 212 and 214 may also be etched together. In this case, the thickness of the first portion 214 is made thicker than that of the wet etching so that the first portion 214 is removed in this process so that the lower conductor is not exposed.

In this way, as shown in Figs. 9A and 9B, only the conductors of the channel portion C and the region A, that is, the source / drain conductor 178 and the storage capacitor conductor 177 remain, and the other portion (B). All of the conductors are removed to expose the resistive contact member 160 thereunder. In this case, the remaining conductors 178 are different from those of FIGS. 1 to 3 in that the source and drain electrodes 173 and 175 are connected without being separated.

Subsequently, as shown in FIGS. 10A and 10B, the exposed ohmic contact member 160 of the other portion B and the semiconductor 150 thereunder are subjected to a dry etching method together with the first portion 214 of the photoresist film. Remove at the same time. The etching may be performed under the condition that the photoresist films 212 and 214, the ohmic contact member 160, and the semiconductor 150 are simultaneously etched, and the gate insulating layer 140 is not etched. In particular, the photoresist films 212 and 214 may be etched. It is preferable to etch under conditions in which the etching ratio with respect to the semiconductor 150 is almost the same. For example, by using a mixed gas of SF6 and HCl or a mixed gas of SF6 and O2, the two films can be etched to almost the same thickness. When the etch ratios for the photoresist layers 212 and 214 and the semiconductor 150 are the same, the thickness of the first portion 214 should be equal to or smaller than the sum of the thicknesses of the semiconductor 150 and the ohmic contact member 160.

This removes the first portion 214 of the channel portion C, as shown in FIGS. 10A and 10B, to reveal the source / drain conductor 178. On the other hand, since the second portion 212 of the region A is also etched, the thickness becomes thin.

Subsequently, ashing removes photoresist residue remaining on the surface of the source / drain conductor 178 of the channel part C.

Next, as illustrated in FIGS. 11A and 11B, the source / drain conductor 178 of the channel portion C and the resistive contact member 160 thereunder are etched and removed. In this case, the etching may be performed only by dry etching with respect to both the source / drain conductor 178 and the ohmic contact member 160. The etching may be performed by wet etching with respect to the source / drain conductor 178. 160 may be performed by dry etching. In the former case, it is preferable to perform etching under a condition where the source / drain conductor 178 and the ohmic contact member 160 have a large etching selectivity. This is difficult to find an etching end point when the etching selectivity is not large. This is because it is not easy to control the thickness of the remaining semiconductor. In the latter case of alternating between wet etching and dry etching, the side surface of the source / drain conductor 178 to be wet etched is etched, but the dry contact resistive contact member 160 is hardly etched, and thus is formed in a step shape. Examples of the etching gas used to etch the ohmic contact member 160 and the semiconductor 150 include a mixture of CF4 and HCl, or a mixture of CF4 and O2, and using CF4 and O2 in a uniform thickness. The semiconductor 150 may be left. At this time, as shown in FIG. 11B, a portion of the semiconductor 154 may be removed to reduce the thickness, and the second photosensitive layer pattern 212 may be etched so that the photoresist pattern is thick so that the data lines below it are not exposed. Of course it is desirable.

In this way, the source electrode 173 and the drain electrode 175 are separated, thereby completing the data line and the ohmic contact 160 below the data line.

Finally, the photoresist second portion 212 remaining in the area A is removed. However, removal of the second portion 212 may be made after removing the channel portion C source / drain conductor 178 and before removing the ohmic contact 160 thereunder.

As mentioned earlier, wet and dry etching can be alternately used or only dry etching can be used. In the latter case, since only one type of etching is used, the process is relatively easy, but it is difficult to find a suitable etching condition. On the other hand, in the former case, the etching conditions are relatively easy to find, but the process is more cumbersome than the latter.

Next, as shown in FIGS. 12A and 12B, a silicon nitride, an a-Si: C: O film, or an a-Si: O: F film is grown by chemical vapor deposition (CVD) or an organic insulating film is coated. The passivation layer 180 is formed.

Next, the passivation layer 180 is photo-etched together with the gate insulating layer 140 to drain the electrode 175, the extension 125 of the gate line 121, the extension 179 of the data line 171, and the storage capacitor. Contact holes 181, 182, 185, and 187 exposing each of the conductors 177 are formed.

Finally, as shown in FIGS. 1 to 3, the IZO layer and the ITO layer are deposited and photo-etched to thereby connect the pixel electrode 190, the gate line, and the drain electrode 175 and the conductive capacitor conductor 177. Contact auxiliary members 81 and 82 are formed to be connected to extension portions 129 and 179 of the data line, respectively.

1, 2, and 3, the data metals 171, 175, and 177, the contact layer patterns 161, 165, and 167, and the semiconductors 151 and 157 below the data metals 171, 175, and 157 may be formed. The manufacturing process may be simplified by forming using a mask and separating the source electrode 173 and the drain electrode 175 in this process. However, when using such a manufacturing method, semiconductors 151 and 157 are always present under the data metals 171, 175 and 177. On the other hand, when the semiconductor is exposed to a backlight or the like, leakage current increases, thereby reducing the reliability of the thin film transistor and reducing the display quality of the liquid crystal display. In order to prevent this, in the exemplary embodiment of the present invention, a portion of the semiconductor 151 constituting the thin film transistor, which is located on the drain electrode 175 side away from the data line, and the drain electrode 175 includes the gate line 124. Place them inside the area they occupy.

A thin film transistor array panel according to another exemplary embodiment of the present invention will be described.

FIG. 13 is a layout view of a thin film transistor array panel according to another exemplary embodiment, and FIG. 14 is a pattern diagram of a photo mask used when manufacturing the thin film transistor array panel of FIG. 13.

The layer structure of the thin film transistor array panel of FIG. 13 is generally similar to the thin film transistor array panel illustrated in FIGS. 1 to 3.

That is, the gate line 121 and the storage electrode line (not shown) are formed on the insulating substrate 110, the gate insulating layer 140 is formed on the gate line 121 and the storage electrode line, and on the gate insulating layer 140. A semiconductor and an ohmic contact layer (not shown) including the protrusion 154 is formed. The data line 171 and the drain electrode 175 including the source electrode 173 are formed on the ohmic contact layer, and a protective film (not shown) is formed on the data line 171 and the drain electrode. The passivation layer has a contact hole 185 exposing the drain electrode 175, and a pixel electrode 190 connected to the drain electrode 175 through the contact hole 185 is formed on the passivation layer.

At this time, in the thin film transistor array panel of FIG. 13, unlike the thin film transistor array panel of FIGS. 1 to 3, the pixel electrode 190 has branch portions 191 extending toward the drain electrode 175 and the branch portions 191 are in contact with each other. It is connected to the drain electrode 175 through the sphere 185. Other portions of the pixel electrode 190 except for the branch 191 do not overlap the gate electrode 124.

This is to prevent the flicker caused by the kickback voltage by reducing the parasitic capacitance formed between the pixel electrode 190 and the gate electrode 124. That is, when the area where the pixel electrode 190 and the gate electrode 124 overlap is large, the parasitic capacitance formed between them is so large that the pixel electrode voltage drops accordingly when the gate voltage drops from the on voltage to the off voltage ( Kickback) is getting worse to prevent this.

FIG. 14 sequentially deposits a gate insulating film, a semiconductor layer, an ohmic contact layer, and a data metal layer on an insulating substrate on which the gate line 121 including the gate electrode 124 is formed, and in a state in which a photosensitive film is coated on the data metal layer. The light shielding pattern of the photomask used at the process of forming the photosensitive film for patterning a metal layer, an ohmic contact layer, and a semiconductor layer together is shown.

As shown in FIG. 14, a slit pattern 751 is disposed between the data line light shielding pattern 710 and the drain electrode light shielding pattern 750. Here, the light blocking pattern 750 and the slit pattern 751 for the drain electrode are disposed inside an area occupied by the gate line 121 including the gate electrode 124.

A thin film transistor array panel according to still another embodiment of the present invention will be described.

15 is a layout view of a thin film transistor array panel according to another exemplary embodiment of the present invention, and FIG. 16 is a pattern diagram of a photomask used when manufacturing the thin film transistor array panel of FIG. 15.

The thin film transistor array panel of FIG. 15 has a structure generally similar to that of the thin film transistor array panel shown in FIG. 13.

That is, the gate line 121 and the storage electrode line (not shown) are formed on the insulating substrate 110, the gate insulating layer 140 is formed on the gate line 121 and the storage electrode line, and on the gate insulating layer 140. A semiconductor and an ohmic contact layer (not shown) including the protrusion 154 is formed. The data line 171 and the drain electrode 175 are formed on the ohmic contact layer, and a protective film (not shown) is formed on the data line 171 and the drain electrode 175. The passivation layer has a contact hole 185 exposing the drain electrode 175, and a pixel electrode 190 connected to the drain electrode 175 through the contact hole 185 is formed on the passivation layer.

In this case, unlike the thin film transistor array panel of FIG. 13, the thin film transistor array panel of FIG. 15 does not have a source electrode from which the data line 171 protrudes. Instead, the drain electrode 175 protrudes from the data line 171. It is increasing the width facing. This ensures a sufficient channel width of the thin film transistor.

FIG. 16 sequentially deposits a gate insulating film, a semiconductor layer, an ohmic contact layer, and a data metal layer on an insulating substrate on which the gate line 121 including the gate electrode 124 is formed, and in a state in which a photosensitive film is coated on the data metal layer. The light shielding pattern of the photomask used at the process of forming the photosensitive film for patterning a metal layer, an ohmic contact layer, and a semiconductor layer together is shown.

As shown in FIG. 16, a slit pattern 751 is disposed between the data line light shielding pattern 710 and the drain electrode light shielding pattern 750. Here, the light blocking pattern 750 and the slit pattern 751 for the drain electrode are disposed inside an area occupied by the gate line 121 including the gate electrode 124.

A thin film transistor array panel according to still another embodiment of the present invention will be described.

17 is a layout view of a thin film transistor array panel according to another exemplary embodiment of the present invention, and FIG. 18 is a cross-sectional view taken along line XVIII-XVIII of FIG. 17.

The layered structure of the thin film transistor array panel illustrated in FIGS. 17 and 18 is generally similar to the thin film transistor array panel illustrated in FIGS. 1 to 3.

That is, the gate line 121 including the gate electrode 124 and the storage electrode line (not shown) are formed on the insulating substrate 110, and the gate insulating layer 140 is formed on the gate line 121 and the storage electrode line. The semiconductor and ohmic contact layer 165 including the protrusion 154 is formed on the gate insulating layer 140. The data line 171 and the drain electrode 175 including the source electrodes 173a and 173b are formed on the ohmic contact layer 165, and the passivation layer 180 is formed on the data line 171 and the drain electrode 175. Formed. The passivation layer 180 has a contact hole 185 exposing the drain electrode 175, and a pixel electrode 190 connected to the drain electrode 175 through the contact hole 185 is formed on the passivation layer 180. have.

In this case, in the thin film transistor array panel of FIGS. 17 and 18, unlike the thin film transistor array panel of FIGS. 1 to 3, the pixel electrode 190 has branch portions 191 extending toward the drain electrode 175 and branch portions 191. ) Is connected to the drain electrode 175 through the contact hole 185. This is to prevent the flicker caused by the kickback voltage by reducing the parasitic capacitance formed between the pixel electrode 190 and the gate electrode 124.

The source electrodes 173a and 173b extend in two branches, and the drain electrode 175 is disposed between the two source electrodes 173a and 173b, and the drain electrode 175 is formed in an elongated bar shape.

The protrusion 154 of the semiconductor also extends outward from the source electrodes 173a and 173b and the drain electrode 175. Therefore, a margin area is provided around the drain electrode 175.

The contact hole 185 exposes the far side of the data line 171 of both ends of the drain electrode 175, and not only the drain electrode 175 but also the protrusion 154 of the semiconductor around the drain electrode 175 together. Exposed Accordingly, the branch 191 of the pixel electrode 190 is in contact with the side surface as well as the upper surface of the drain electrode 175 and is also in contact with the exposed protrusion 154 of the semiconductor.

As such, when the branch 191 of the pixel electrode 190 contacts the upper surface and the side surface of the drain electrode 175, electrical contact between the pixel electrode 190 and the drain electrode 175 may be strengthened. To this end, the contact hole 185 should be formed to expose not only the drain electrode 175 but also the periphery of the drain electrode 175. In this case, the contact hole 185 is widely distributed around the drain electrode 175. The area exposed by) can be limited over the semiconductor. Since the semiconductor may sufficiently increase the selectivity of the passivation layer 180 and the etching selectivity made of an insulating material, when the passivation layer 180 is etched to form the contact hole 185, the semiconductor layer may act as an etch blocking layer to form a lower gate insulating layer 140. This can be prevented from being damaged.

Herein, the protrusion 154 of the semiconductor overlaps with the gate electrode 124 as in the previous embodiment, and the area of the surface of the insulating substrate 110 occupied by the gate line 121 including the gate electrode 124 occupies. It is formed to lie inside. That is, the edge of the protrusion 154 of the semiconductor is placed in an area surrounded by the edge of the gate line 121 including the gate electrode 124. Therefore, when viewed from below the insulating substrate 110, the protrusion 154 is not visible due to the gate electrode 124 and the gate line 121.

At this time, the entire projecting portion 154 of the semiconductor is not necessarily placed inside the area occupied by the gate line 121 including the gate electrode 124, but at least a data line including the source electrodes 173a and 173b. An area occupied by the gate line 121 including the gate electrode 124 includes a channel semiconductor, which is a portion between the drain electrode 171 and the drain electrode 175, and a semiconductor disposed below the drain electrode 175. It is preferable to form so as to lie inside. In other words, the semiconductor positioned away from the data line 171 toward the drain electrode 175 may be formed so as to lie inside the area occupied by the gate line 121 including the gate electrode 124.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the exemplary embodiment of the present invention, the gate metal layer covers the semiconductor constituting the thin film transistor to prevent leakage current generated by the backlight light being emitted to the semiconductor.

In addition, a wide contact hole for connecting the pixel electrode and the drain electrode can be formed on the semiconductor to enhance the connection between the pixel electrode and the drain electrode.

Claims (18)

Insulation board, A gate line formed on the insulating substrate and including a gate electrode; A data line insulated from and intersecting the gate line and including a source electrode; A drain electrode facing the source electrode and the gate line; A semiconductor formed under the data line and having a protrusion extending down to the drain electrode And a portion positioned away from the data line of the semiconductor toward the drain electrode, and positioned inside an area occupied by the gate line including the gate electrode. In claim 1, The drain electrode is positioned in an area occupied by the semiconductor. In claim 1, The protrusion of the semiconductor is positioned in an area occupied by a gate line including the gate electrode. In claim 1, The thin film transistor array panel of claim 1, further comprising a pixel electrode connected to the drain electrode. In claim 4, The pixel electrode has a branch extending toward the drain electrode and the branch is connected to the drain electrode. In claim 5, The pixel electrode does not overlap the gate line at portions except the branch portion. In claim 4, The pixel electrode is in contact with the top and side surfaces of the drain electrode. In claim 7, The pixel electrode is in contact with the semiconductor. Insulation board, A gate line formed on the insulating substrate and including a gate electrode; A gate insulating film formed on the gate line, A linear semiconductor formed on the gate insulating film and having a protrusion; A data line formed on the linear semiconductor and intersecting the gate line and including a source electrode, A drain electrode formed on the protrusion of the linear semiconductor, A protective film formed on the data line and the drain electrode and having a contact hole exposing the drain electrode; A pixel electrode formed on the passivation layer and connected to the drain electrode through the contact hole; And a portion positioned outside the data line of the linear semiconductor toward the drain electrode, and positioned within an area occupied by the gate line including the gate electrode. In claim 9, The drain electrode is positioned in an area occupied by the semiconductor. In claim 9, The protrusion of the semiconductor is positioned in an area occupied by a gate line including the gate electrode. In claim 9, The pixel electrode has a branch extending toward the drain electrode and the branch is connected to the drain electrode. In claim 12, The pixel electrode does not overlap the gate line at portions except the branch portion. In claim 9, The contact hole exposes the drain electrode and the semiconductor around the drain electrode. The method of claim 14, The pixel electrode is in contact with the top and side surfaces of the drain electrode exposed through the contact hole. The method of claim 15, The pixel electrode is in contact with the semiconductor exposed through the contact hole. The method of claim 16, The pixel electrode has a branch part, and the branch part is connected to the drain electrode and the semiconductor. The method of claim 17, And a portion of the portion exposed through the contact hole of the semiconductor is covered with the pixel electrode.

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