KR20060028517A - Thin film transistor array panel and method for manufacturing the same - Google Patents

Abstract

The thin film transistor array panel according to the present invention includes an insulating substrate, a gate line formed on the insulating substrate, a data line insulated from and intersecting the gate line, a thin film transistor connected to the gate line and the data line, and a pixel electrode connected to the thin film transistor. And at least one of the gate line and the data line includes a first conductive film made of aluminum or an aluminum alloy, and a second conductive film formed on the first conductive film and having a relatively compressive force than the first conductive film.

Aluminum, Wiring, Hillock, Molybdenum, Thin Film Transistor

Description

Thin film transistor array panel and method for manufacturing the same {Thin film transistor array panel and method for manufacturing the same}

1 is a layout view illustrating a structure of a thin film transistor array panel for a liquid crystal display according to a first exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view of the thin film transistor array panel of FIG. 1 taken along the line II-II ',

3A, 4A, 5A, and 6A are layout views of a thin film transistor array panel at an intermediate stage of a method of manufacturing the thin film transistor array panel illustrated in FIGS. 1 and 2 according to an embodiment of the present invention, in the order thereof. Are listed,

3B is a cross-sectional view taken along the line IIIb-IIIb ′ of FIG. 3A;

4B is a cross-sectional view taken along the line IVb-IVb ′ of FIG. 4A;

5B is a cross-sectional view taken along the line Vb-Vb ′ of FIG. 5A;

FIG. 6B is a cross-sectional view taken along the line VIb-VIb ′ of FIG. 6A;

7 is a layout view of a thin film transistor array panel for a liquid crystal display according to another exemplary embodiment of the present invention.

FIG. 8 is a cross-sectional view taken along the line VIII-VII ′ of FIG. 7;

9A, 11A, 12A, and 13A are layout views at an intermediate stage in the method of manufacturing the thin film transistor display panel according to the second embodiment;

FIG. 9B is a cross-sectional view taken along the line IX-IX ′ of FIG. 9A;

10 is a cross-sectional view at the next step of FIG. 9B,

FIG. 11B is a cross-sectional view taken along the line XIb-XIb ′ of FIG. 11A;

12B is a sectional view at the next step in FIG. 11,

FIG. 13B is a cross sectional view at the next step of FIG. 12B;

14 is a layout view of a thin film transistor array panel according to a third exemplary embodiment of the present invention.

FIG. 15 is a cross-sectional view taken along the line XIV-XIV ′ of FIG. 14;

16A and 17A are layout views at an intermediate stage in the method of manufacturing the thin film transistor array panel according to the third embodiment;

FIG. 16B is a cross-sectional view taken along the line XVIb-XVIb ′ of FIG. 16A;

FIG. 17B is a cross-sectional view taken along the line XVIIb-XVIIb ′ of FIG. 17A.

※ Code explanation about main part of drawing ※

110: insulated substrate 121: gate line

140: gate insulating film 151, 154: semiconductor layer

171: data line 175: drain electrode

180: protective film or interlayer insulating film 190: pixel electrode

230R, 230G, 230B: Color Filter

The present invention relates to a thin film transistor array panel and a manufacturing method thereof, and more particularly, to a thin film transistor array panel having a low resistance signal line and a method of manufacturing the same.

The thin film transistor array panel is used as a circuit board for independently driving each pixel in a liquid crystal display device, an organic EL (electro luminescence) display device, or the like.

The thin film transistor array panel includes a scan line or a gate line for transmitting a scan signal and an image signal line or a data line for transmitting an image signal, a thin film transistor connected to the gate line and a data line, a pixel electrode connected to the thin film transistor, and a gate line. And a gate insulating film covering and insulating the thin film transistor, and a protective film covering and insulating the data line.

The thin film transistor includes a semiconductor layer forming a gate electrode and a channel, which are part of a gate line, a source electrode and a drain electrode, which are part of a data line, a gate insulating film, a protective film, and the like. Such a thin film transistor is a switching element that transfers or blocks an image signal transmitted through a data line to a pixel electrode according to a scan signal transmitted through a gate line.

As liquid crystal display devices and organic EL devices using such thin film transistor display panels become larger and larger in size, the lengths of data lines, gate lines, and the like increase greatly, and conversely, the width decreases.                         

Accordingly, a signal distortion problem caused by an increase in resistance of wiring and various parasitic capacitances has emerged as a serious problem. For this reason, the wiring uses a low resistance metal such as aluminum or an aluminum alloy, but aluminum has a problem in that hillock or the like occurs at a high temperature.

In order to solve this problem, an auxiliary conductive film of another conductive material is deposited on the conductive film of aluminum. However, due to the difference in the characteristics of the aluminum conductive film and the auxiliary conductive film, a crack or the like occurs in the upper film in a high temperature deposition process, thereby driving circuits. Alternatively, the contact portion of the wiring connected to the pixel electrode has a weak contact characteristic.

SUMMARY OF THE INVENTION The present invention provides a thin film transistor array panel and a method of manufacturing the same, which can improve contact characteristics of wirings by minimizing hillocks and cracks.

The thin film transistor array panel according to the present invention for achieving the above object is an insulating substrate, a gate line formed on the insulating substrate, a data line insulated from and crosses the gate line, a thin film transistor connected to the gate line and the data line, a thin film transistor And a pixel electrode connected to the at least one of the gate line and the data line, the first conductive layer comprising aluminum or an aluminum alloy and a first conductive layer formed on the first conductive layer and having a compressive force relative to that of the first conductive layer. 2 conductive films.                     

The color filter may further include red, green, and blue color filters formed on the insulating substrate and positioned under the pixel electrode.

The thin film transistor preferably includes a gate electrode that is a part of the gate line, a source electrode that is a part of the data line, a drain electrode connected to the pixel electrode, and a semiconductor disposed between the gate electrode and the source electrode and the drain electrode.

In this case, the semiconductor except for the source electrode and the drain electrode preferably has the same planar pattern as the data line and the drain electrode.

In addition, the second conductive film is preferably formed of one of Mo, MoW, MoN, MoZr, or MoNb.

At this time, the compressive force of Mo has a range of -1 GPa ~ 10 GPa, the compressive force of MoN and MoZr has a range of -2 GPa ~ 5 GPa, MoW has a detection value of -15 GPa ~ 15 GPa desirable.

In addition, the aluminum alloy is preferably AlNd.

At this time, the compressive force of Al is in the range of -0.2 GPa to 0.4 GPa, and the compressive force of AlNd is preferably in the range of 0.1 GPa to 0.4 GPa.

According to another aspect of the present invention, there is provided a method of manufacturing a thin film transistor array panel, the method including: forming a gate line on a substrate, forming a data line insulated from and intersecting the gate line, and a thin film transistor connected to the gate line and the data line. Forming a pixel electrode connected to the thin film transistor, wherein at least one of the gate line or the data line is formed on the first conductive film, and is formed on the first conductive film. And forming a second conductive film having a compressive force relatively to that of the first conductive film.

The method may further include forming a color filter of red, green, and blue on the substrate and under the pixel electrode.

The second conductive film is preferably formed of one of Mo, MoW, MoN, MoZr or MoNb.

At this time, the compressive force of Mo has a range of -1 GPa ~ 10 GPa, the compressive force of MoN and MoZr has a range of -2 GPa ~ 5 GPa, MoW has a range of -15 GPa ~ 15 GPa desirable.

In addition, the aluminum alloy is preferably formed of AlNd, and the compressive force of Al is preferably in the range of -0.2 GPa to 0.4 GPa, and the compressive force of AlNd is preferably in the range of 0.1 GPa to 0.4 GPa.

In addition, MoN is preferably formed by a sputtering process and is preferably formed by injecting nitrogen gas during the sputtering process.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right on" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

A method of manufacturing a thin film transistor array panel for a liquid crystal display according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

First, the structure of a thin film transistor array panel for a liquid crystal display according to a first exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a layout view illustrating a structure of a thin film transistor array panel for a liquid crystal display according to a first exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view of the thin film transistor array panel of FIG. 1 taken along line II-II ′.

A plurality of gate lines 121 are formed on the insulating substrate 110 to transfer gate signals. The gate line 121 mainly extends in the horizontal direction, and a part of each gate line 121 forms a plurality of gate electrodes 124. In addition, another portion of each gate line 121 protrudes downward to form a plurality of expansions 127.

The gate line 121 includes first conductive layers 121a, 124a and 127a and second conductive layers 121b, 124b and 127b formed on the first conductive layers 121a, 124a and 127a. The conductive films 121a, 124a, and 127a include a conductive material such as aluminum-based metal such as aluminum (Al) or an aluminum alloy, and the second conductive films 121b, 124b, and 127b include the first conductive films 121a, 124a, A relatively compressive conductive material for 127a), such as Mo, MoN, MoZr, MoNb or MoW. The second conductive layers 121b, 124b, and 127b preferably have physical, chemical, and electrical contact properties with indium tin oxide (ITO) or indium zinc oxide (IZO).

Here, the compressive force of Mo has a range of -1 GPa to 10 GPa, and MoN and MoZr have a range of -2 GPa to 5 GPa. Al has a range of -0.2 GPa to 0.4 GPa, AlNd has a range of 0.1 GPa to 0.4 GPa, and MoW has a range of -15 GPa to 15 GPa.

Side surfaces of the gate line 121 and the gate electrode 124 are inclined, respectively, and the inclination angle is about 30-80 ° with respect to the surface of the substrate 110.

A gate insulating layer 140 made of silicon nitride (SiNx) is formed on the gate line 121.

A plurality of linear semiconductor layers 151 made of hydrogenated amorphous silicon (hereinafter referred to as a-Si) are formed on the gate insulating layer 140. The linear semiconductor layer 151 mainly extends in the longitudinal direction, from which a plurality of extensions 154 extend toward the gate electrode 124. In addition, the linear semiconductor layer 151 increases in width near the point where it meets the gate line 121 to cover a large area of the gate line 121.

A plurality of linear and island ohmic contacts 161 and 165 formed of a material such as n + hydrogenated amorphous silicon doped with a high concentration of silicide or n-type impurities are formed on the semiconductor layer 151. It is. The linear ohmic contact 161 has a plurality of protrusions 163, and the protrusion 163 and the island-type ohmic contact 165 are paired and positioned on the protrusion 154 of the semiconductor layer 151. Side surfaces of the semiconductor layer 151 and the ohmic contacts 161 and 165 are also inclined, and the inclination angle is 30 to 80 ° with respect to the substrate 110.

The plurality of data lines 171, the plurality of drain electrodes 175, and the plurality of storage capacitors are disposed on the ohmic contacts 161 and 165 and the gate insulating layer 140, respectively. conductor 177 is formed.

The data line 171 mainly extends in the vertical direction to cross the gate line 121 and transmit a data voltage. A plurality of branches extending from the data line 171 toward the drain electrode 175 forms a source electrode 173. The pair of source electrode 173 and the drain electrode 175 are separated from each other and positioned opposite to the gate electrode 124.

The gate electrode 124, the source electrode 173, and the drain electrode 175 form a thin film transistor (TFT) together with the protrusion 154 of the semiconductor 151, and the channel of the thin film transistor is a source. A protrusion 154 is formed between the electrode 173 and the drain electrode 175. The storage capacitor conductor 177 overlaps the extension portion 127 of the gate line 121.

The data line 171, the drain electrode 175, and the conductive capacitor 177 for the storage capacitor may also be formed of a conductive film such as aluminum (Al) or an aluminum alloy, such as the gate line 121. In addition to the conductive film, chromium (Cr), titanium (Ti), tantalum (Ta), molybdenum (Mo) and other materials with good physical, chemical and electrical contact properties with other materials, especially indium tin oxide (ITO) or indium zinc oxide (IZO) It may have a multilayer film structure including another conductive film made of an alloy thereof (eg, molybdenum-tungsten (MoW) alloy). An example of such a structure is a chromium / aluminum-neodymium (AlNd) alloy. In the case of the double film, the aluminum-based conductive film is preferably positioned below the other conductive film, and in the case of the triple film, the aluminum-based conductive film is preferably positioned as the intermediate layer.

Similarly to the gate line 121, the data line 171, the drain electrode 175, and the storage capacitor conductor 177 are also inclined at an angle of about 30 to 80 ° with respect to the substrate 110.

The ohmic contacts 161 and 165 exist only between the lower semiconductor layer 151 and the upper data line 171 and the drain electrode 175 and lower the contact resistance. The linear semiconductor layer 151 has an exposed portion between the source electrode 173 and the drain electrode 175, and is not covered by the data line 171 and the drain electrode 175, and in most places, the linear semiconductor layer ( Although the width of the 151 is smaller than the width of the data line 171, as described above, the width of the 151 is increased at the portion where the gate line 121 meets, thereby increasing the insulation between the gate line 121 and the data line 171.

A passivation layer 180 made of an organic material having excellent planarization characteristics is formed on the data line 171, the drain electrode 175, the storage capacitor conductor 177 and the exposed semiconductor layer 151. . The passivation layer 180 may be formed of an organic material having photosensitivity.

In order to prevent the organic material of the passivation layer 180 from coming into contact with the exposed portion of the semiconductor layer 154 between the data line 171 and the drain electrode 175, the passivation layer 180 is formed of silicon nitride or silicon oxide under the organic layer. An insulating film (not shown) may be added.

In the passivation layer 180, a plurality of contact holes 185, 187, and 182 exposing end portions of the drain electrode 175, the storage capacitor conductor 177, and the data line 171 are formed. . In this case, an end portion of the data line 171 may have a width wider than that of the data line 171 and the gate line 121 as necessary.

A plurality of pixel electrodes 190 and a plurality of contact assistants 82 made of IZO or ITO are formed on the passivation layer 180.

The pixel electrode 190 is physically and electrically connected to the drain electrode 175 and the storage capacitor conductor 177 through the contact holes 185 and 187, respectively, to receive the data voltage from the drain electrode 175 and to maintain the storage capacitor. The data voltage is transmitted to the existing conductor 177.

The pixel electrode 190 to which the data voltage is applied rearranges the liquid crystal molecules of the liquid crystal layer by generating an electric field together with a common electrode (not shown) of another display panel (not shown) to which a common voltage is applied. .

In addition, as described above, the pixel electrode 190 and the common electrode form a capacitor (hereinafter, referred to as a "liquid crystal capacitor") to maintain an applied voltage even after the thin film transistor is turned off. For the purpose of strengthening, another capacitor connected in parallel with the liquid crystal capacitor is provided, which is referred to as a "storage electrode". The storage capacitor is made of a superposition of the pixel electrode 190 and a neighboring gate line 121 (which is referred to as a "previous gate line"), and the like, to increase the capacitance of the storage capacitor, that is, the storage capacitance. In order to increase the overlapped area by providing an extension part 127 extending the gate line 121, a protective film conductor 177 connected to the pixel electrode 190 and overlapping the extension part 127 is provided as a protective film. 180) Place it underneath to bring the distance between the two closer.

The pixel electrode 190 also overlaps the neighboring gate line 121 and the data line 171 to increase the aperture ratio, but may not overlap.

The contact auxiliary members 81 and 82 are connected to the ends of the gate lines and the data lines 121 and 171 through the contact holes 181 and 182, respectively. The contact auxiliary members 81 and 82 compensate for and protect the adhesion between the respective ends of the gate line 121 and the data line 171 and an external device such as a driving integrated circuit.

Next, a method of manufacturing the thin film transistor array panel for the liquid crystal display device illustrated in FIGS. 1 to 2 according to one embodiment of the present invention will be described in detail with reference to FIGS. 3A to 6B and FIGS. 1 and 2.

3A, 4A, 5A, and 6A are layout views of a thin film transistor array panel in an intermediate step of a method of manufacturing the thin film transistor array panel illustrated in FIGS. 1 and 2 according to an embodiment of the present invention. 3B is a cross-sectional view taken along the line IIIb-IIIb 'of FIG. 3A, FIG. 4B is a cross-sectional view taken along the line IVb-IVb' of FIG. 4A, and FIG. 5B is a line Vb-Vb 'of FIG. 5A. 6B is a cross-sectional view taken along the line VIb-VIb ′ of FIG. 6A.

First, as illustrated in FIGS. 3A and 3B, a conductive material including aluminum and a conductive material having a relatively higher compressive force than aluminum are sequentially stacked on an insulating substrate 110 made of transparent glass, such as sputtering. After patterning by a photolithography process, the first conductive layers 121a, 124a, and 127a and the second conductive layers 121b, 124b, and 127b are formed, and the plurality of gate electrodes 124 and the plurality of extensions 127 are formed. A gate line 121 is formed.

The first conductive film is a conductive material made of an aluminum-based metal such as aluminum (Al) or an aluminum alloy, and the second conductive film is a conductive material made of a molybdenum alloy-based metal such as Mo, MoN, MoZr, MoNb, MoW, or the like. It is formed of the same conductive material. In this case, the second conductive film has good physical, chemical, and electrical contact properties with indium tin oxide (ITO) or indium zinc oxide (IZO), and preferably has a higher atomic weight than the first conductive film.

Since the second conductive film has a relatively higher compressive force than the first conductive film, the first conductive film is subjected to tension during deposition or a subsequent manufacturing process, and thus no hillock occurs in the first conductive film. Here, the compressive force of Mo has a range of -1 GPa to 10 GPa, and MoN and MoZr have a range of -2 GPa to 5 GPa. Al preferably has a range of -0.2 GPa to 0.4 GPa, AlNd has a range of 0.1 GPa to 0.4 GPa, and MoW has a range of -15 GPa to 15 GPa.

In this case, in order to have a higher compressive force than the first conductive film, the second conductive film may be formed by slowing the deposition rate or increasing the deposition pressure.

As in the embodiment of the present invention, since the material particles of the second conductive film have a higher atomic weight than the first conductive film, the amount of impact that the argon particles impinge on the target is increased in the sputtering process, so that the thin films are laminated while having a high compressive force. The conductive film has a higher compressive force than the first conductive film.

In addition, MoN is laminated by sputtering process, but is added while adding nitrogen gas when sputtering pure molybdenum. At this time, while the N electrons are located between the molybdenum atoms, the second conductive film of MoN has a relatively higher compressive force than the first conductive film containing aluminum.

As such, when the first conductive film is subjected to the stretching force, the second conductive film is relatively compressed. Then, even if a subsequent process is performed at a high temperature, the occurrence of hillock in the first conductive film is reduced, and cracks or the like can be prevented from being formed in the second conductive film.

Next, as illustrated in FIGS. 4A and 4B, the gate insulating layer 140, the intrinsic amorphous silicon, and the impurity amorphous silicon layer cover the gate line 121 and the gate electrode 124. The three-layered film of ()) is successively stacked, and the linear intrinsic semiconductor layer 151 including the plurality of impurity semiconductor patterns 164 and the plurality of protrusions 154 is formed by photo etching the impurity amorphous silicon layer and the intrinsic amorphous silicon layer. do. The gate insulating film 140 is preferably formed of silicon nitride with a thickness of 2,000 to 5,000 GPa.

Next, as shown in FIGS. 5A and 5B, a conductive film is formed on the substrate 110 by sputtering or the like. In this case, the conductive film for the data line may also be formed of the same material as the gate line 121 by the same method. That is, in the case of including a conductive film made of aluminum or an aluminum alloy, a conductive film that receives a compressive force relative to the conductive film is further formed on the conductive film.

Thereafter, a photosensitive film is formed on the conductive film, and the conductive film is patterned using an etch mask to form a plurality of data lines 171, a plurality of drain electrodes 175, and a plurality of conductive capacitors, each of which includes a plurality of source electrodes 173. Form 177.

Subsequently, the photosensitive layer on the data line 171 and the drain electrode 175 is removed or left untouched, and is exposed without being covered by the data line 171, the drain electrode 175, and the storage capacitor conductor 177. By removing the portion of the impurity semiconductor layer 164, the plurality of linear ohmic contact members 161 and the plurality of island type ohmic contact members 165 each including a plurality of protrusions 163 are completed, while the intrinsic semiconductor ( 154) expose the part.

Next, as shown in FIGS. 6A and 6B, an organic material having excellent planarization characteristics and photosensitivity so as to cover a portion of the semiconductor 151 exposed on the substrate, and plasma enhanced chemical vapor deposition , A passivation layer 180 is formed of a low dielectric constant insulating material such as a-Si: C: O, a-Si: O: F, or silicon nitride, which is an inorganic material, formed by PECVD.

Then, the passivation layer 180 is etched by a photolithography process to form a plurality of contact holes 182, 185, and 187.

When the protective film is formed of an organic material having photosensitivity, the contact roll may be formed only by a photographic process.

The contact holes 181, 182, 185, and 187 expose the ends of the gate and data lines 121 and 171, the drain electrode 175, and the conductive capacitor 177 for the storage capacitor. In this case, when the end portion of the gate line 121 is exposed or another thin film made of the same layer as the gate line 121 is exposed, the gate insulating layer 140 is also etched together.

Next, as shown in FIGS. 1 and 2, the IZO or ITO film is deposited on the substrate by sputtering, and the plurality of pixel electrodes 190 and the first and second contact auxiliary members 81 and 82 are formed by a photolithography process. To form.

 Second Embodiment

In the above description, the embodiment of the present invention is applied to a manufacturing method for forming a semiconductor layer and a data line by a photolithography process using different masks. However, the manufacturing method according to the present invention uses a semiconductor layer and data to minimize manufacturing costs. The same applies to the manufacturing method of the thin film transistor array panel for a liquid crystal display device in which lines are formed by a photolithography process using one photosensitive film pattern.

This will be described in detail with reference to the drawings.                     

7 is a layout view of a TFT panel for a liquid crystal display according to another exemplary embodiment. FIG. 8 is a cross-sectional view taken along the line VIII-VII ′ of FIG. 7.

As shown in Figs. 7 and 8, the layer structure of the thin film transistor array panel for liquid crystal display device according to the present embodiment is generally the same as the layer structure of the thin film transistor array panel for liquid crystal display devices shown in Figs. That is, the plurality of linear semiconductors including the plurality of gate lines 121 including the plurality of gate electrodes 124 is formed on the substrate 110, and the gate insulating layer 140 and the plurality of protrusions 154 thereon. A layer 151, a plurality of linear ohmic contact members 161 each including a plurality of protrusions 163, and a plurality of island-type ohmic contact members 165 are sequentially formed. On the ohmic contacts 161 and 165 and the gate insulating layer 140, a plurality of data lines 171 including a plurality of source electrodes 153, a plurality of drain electrodes 175, and a plurality of conductive capacitors 177. ) Is formed and a passivation layer 180 is formed thereon. A plurality of contact holes 182 and 185 are formed in the passivation layer 180, and a plurality of pixel electrodes 190 and a plurality of contact assistant members are formed on the passivation layer 180.

However, unlike the thin film transistor array panel shown in FIGS. 1 and 2, the thin film transistor array panel according to the present embodiment is electrically connected to the gate line 121 on the same layer as the gate line 121 instead of having an extension portion on the gate line 121. A plurality of storage electrode lines 131 separated by the plurality of layers are overlapped with the drain electrode 175 to form a storage capacitor. The storage electrode line 131 receives a predetermined voltage such as a common voltage from the outside, and the storage electrode line 131 may be omitted when the storage capacitor generated due to the overlap of the pixel electrode 190 and the gate line 121 is sufficient. In order to maximize the aperture ratio of the pixel, the pixel may be disposed at an edge of the pixel area.

The semiconductor layer 151 has a planar shape substantially the same as the data line 171, the drain electrode 175, and the ohmic contacts 161 and 165, except for the protrusion 154 where the thin film transistor is located. have. Specifically, the linear semiconductor layer 151 may include the source electrode 173 and the drain electrode (aside from the data line 171, the drain electrode 175, and the portions below the ohmic contacts 161 and 165 below). 175) has exposed portions between them.

Further, in the second embodiment, the data line has a triple film structure, and as in the first embodiment, the gate line may be formed in a double film structure.

Next, a method of manufacturing the thin film transistor array panel according to the exemplary embodiment illustrated in FIGS. 9A and 13B will be described in detail with reference to FIGS. 7 and 8 described above with reference to the accompanying drawings.

9A, 11A, 12A, and 13A are layout views at an intermediate stage in the method of manufacturing the thin film transistor array panel according to the second embodiment, and FIG. 9B is a cross-sectional view taken along the line IX-IX ′ of FIG. 9A. FIG. 10 is a cross-sectional view at the next step of FIG. 9B, FIG. 11B is a cross-sectional view taken along the line XIb-XIb ′ of FIG. 11A, FIG. 12B is a cross-sectional view at the next step of FIG. 11, and FIG. 13B is a view of FIG. This is a cross section in the next step.

First, as shown in FIGS. 9A and 9B, after forming a conductive film on the substrate 110, a gate line 121 having the gate electrode 124 is formed by a photolithography process.

Next, as shown in FIG. 10, an insulating material such as silicon nitride covering the gate line 121 is deposited to form a gate insulating layer 140. Subsequently, an amorphous silicon without doping impurities and an amorphous silicon doped with impurities are deposited on the gate insulating layer 140 to sequentially form the amorphous silicon film 150 without the impurities and the amorphous silicon film 160 with the impurities. Laminated by. The amorphous silicon film 150 not doped with impurities is formed of hydrogenated amorphous silicon, and the like, and the amorphous silicon film 160 doped with impurities is heavily doped with an n-type impurity such as phosphorus (P). It is formed of silicon or silicide.

Then, the first to third conductive films 701 to 703 are laminated on the amorphous silicon film 160 doped with impurities by a method such as sputtering to form a conductive film 170 including a triple film.

The second conductive film 702 is a conductive material made of an aluminum-based metal such as aluminum (Al) or an aluminum alloy. The first and third conductive films 701 and 703 are made of a conductive material made of a molybdenum alloy-based metal. For example, it is formed of a conductive material such as Mo, MoN, MoZr, MoNb, MoW. In this case, the first and third conductive films have good physical, chemical, and electrical contact properties with indium tin oxide (ITO) or indium zinc oxide (IZO), and are preferably a material having more atomic weight than the second conductive film.

Since the first and third conductive films 701 and 702 have a relatively higher compressive force than the second conductive film 702, the second conductive film 702 is subjected to tension during deposition or a subsequent manufacturing process. Through the second conductive film 702, the hillock does not occur. Here, the compressive force of Mo has a range of -1 GPa to 10 GPa, MoN and MoZr have a range of -2 GPa to 5 GPa, and MoW has a range of -15 GPa to 15 GPa. And Al preferably has a range of -0.2 GPa to 0.4 GPa, AlNd has a range of 0.1 GPa to 0.4 GPa.

In this case, in order to have a higher compressive force than the first conductive film, the second conductive film may be formed by slowing the deposition rate or increasing the deposition pressure.

Thereafter, a photoresist layer is formed on the conductive layer 170, and then exposed and developed to form photoresist patterns 52 and 54 having different thicknesses.

As such, there may be various methods of varying the thickness of the photoresist film according to the position, and it is not only to have a transparent area and a light blocking area but also a translucent area in the exposure mask. That's an example. The semi-transmissive region includes a slit pattern, a lattice pattern, or a thin film having a medium transmittance or a medium thickness. When using the slit pattern, it is preferable that the width of the slits and the interval between the slits are smaller than the resolution of the exposure machine used for the photographic process. Another example is to use a photoresist film that can be reflowed. That is, a thin portion is formed by forming a reflowable photoresist pattern with a normal mask having only a transparent region and a light shielding region and then reflowing so that the photoresist film flows into an area where no photoresist remains.

Given the appropriate process conditions, the lower layers may be selectively etched due to the difference in thickness of the photoresist patterns 52 and 54. Accordingly, a plurality of data lines 171 and a plurality of drain electrodes 175 including a plurality of source electrodes 173 as shown in FIGS. 13A and 13B are formed through a series of etching steps, and a plurality of protrusions ( A plurality of linear ohmic contacts 161 each including 163, a plurality of island-like ohmic contacts 165, and a plurality of linear semiconductor layers 151 including a plurality of protrusions 154 are formed.

For convenience of description, the conductive film 170 of the portion where the wiring is to be formed, the amorphous silicon film 160 doped with impurities and the amorphous silicon film 150 without doping impurities are referred to as the wiring portion A. A portion of the impurity doped amorphous silicon film 160 and a portion of the amorphous silicon film 150 not doped with impurities is called a channel portion B, and impurities located in regions other than the channel and wiring portions are formed. The portion of the doped amorphous silicon film 160 and the doped amorphous silicon film 150 will be referred to as the other portion (C).

One example of the order of forming such a structure is as follows.

First, (1) removing the impurity amorphous silicon film 160 and the amorphous silicon film 150 in the other part (C), (2) removing the photosensitive film 54 located in the channel part (B), and (3) the channel part ( The impurity amorphous silicon film 160 located in B) is removed, and (4) the photosensitive film 52 located in the wiring portion A is removed.

Other methods include (1) removing the photosensitive film 54 located in the channel portion B, (3) removing the impurity amorphous silicon film 160 and the amorphous silicon film 150 located in the other portion C, and (4) Removing the conductive film located in the channel portion B, (5) removing the photoresist film 52 located in the wiring region A, and (6) removing the impurity amorphous silicon film 160 located in the channel portion B. You can also proceed.

This section describes the first example.                     

First, as shown in FIGS. 12A and 12B, the conductive film 170 exposed to the other region C is removed by wet etching or dry etching, and the other portion of the amorphous silicon film 160 doped with impurities thereunder is removed. Expose part (C).

The data line and the drain electrode are still attached (174). In the case of using dry etching, the upper portions of the photoresist films 52 and 54 may be cut to a certain thickness.

Next, the amorphous silicon film 160 doped with impurities in the other portion C and the amorphous silicon film 150 without dopants under the impurities are removed, and the photoresist film 54 of the channel portion B is removed. It removes and exposes the conductive film 174 which consists of triple layers 174a-174c below.

Removal of the photoresist of the channel portion B may be performed simultaneously with or separately from the removal of the amorphous silicon layer 160 doped with impurities in the other region C and the amorphous silicon layer 150 without the impurities. Residue of the photoresist film 54 remaining in the channel region B is removed by ashing. In this step, the semiconductor layers 151 and 154 are completed.

Here, when the conductive film 170 is a material capable of dry etching, the manufacturing process may be performed by continuously dry etching the amorphous silicon layer 160 doped with impurities below and the amorphous silicon layer 150 without doping impurities. In this case, it may or may not be performed in an in-situ manner in which dry etching is sequentially performed on the three layers 170, 160, and 150 in the same etching chamber.

Next, as shown in FIGS. 13A and 13B, the conductive film 174 located in the channel portion B and the amorphous silicon layer 164 doped with impurities are etched and removed. In addition, the photosensitive film 52 of the remaining wiring portion A is also removed.

In this case, the upper portion of the amorphous silicon film that is not doped with impurities in the channel portion B may be partially removed to reduce the thickness, and the photosensitive film 52 of the wiring portion A may be etched to some extent.

In this way, each of the conductive films 174 is completed while being separated into one data line 171 and a plurality of drain electrodes 175 including triple films 171a to 171c and 175a to 175c, and doped with amorphous silicon. The membrane 164 is also divided into a linear ohmic contact 161 and an island resistive ohmic contact 165.

Next, as shown in FIGS. 14A and 14B, the planarization characteristic is excellent and photosensitivity is provided so as to cover the semiconductor layer 154 that is not covered by the data lines 171 and 173 and the drain electrode 175. Protective films such as organic materials, low dielectric constant insulating materials such as a-Si: C: O, a-Si: O: F formed by plasma enhanced chemical vapor deposition (PECVD), or silicon nitride, which is an inorganic material Form 180. Thereafter, the passivation layer 180 is etched to form contact holes 182 and 185.

Subsequently, as shown in FIGS. 7 and 8, a transparent conductive material such as ITO or IZO is deposited on the substrate 110, and is etched by a photolithography process using a mask to etch one end of the data line through the contact hole 182. The pixel electrode 190 connected to the drain electrode 175 is formed through the contact auxiliary member 82 and the contact hole 185 respectively connected to the portion.

Third Embodiment

Unlike the above-described embodiment, the color filter may be formed on the thin film transistor array panel of the liquid crystal display.

In the thin film transistor array panel according to the exemplary embodiment of the present invention, as shown in FIGS. 14 and 15, most single layer structures are the same as those of the first and second embodiments.

FIG. 14 is a layout view of a thin film transistor array panel according to a third exemplary embodiment of the present invention, and FIG. 15 is a cross-sectional view taken along the line XV-XV ′ of FIG. 14.

As shown in Figs. 14 and 15, they have substantially the same interlayer structure as those of the first and second embodiments. Gate lines 121, 124, and 127 formed of double layers 121a, 121b, 124a, 124b, 127a, and 127b are formed on the insulating substrate 110, and a gate insulating film is formed on the gate lines 121, 124, and 127. 140 is formed. The data line 171, the drain electrode 175, and the storage capacitor conductor 177 are formed on the gate insulating layer 140.

Color filters 230R, 230G, and 230B are formed on the data line 171, the drain electrode 175, and the storage capacitor conductor 177. A passivation layer (not shown) may be formed on the semiconductor layer 154 that is not covered by the data line 171, the drain electrode 175, and the storage capacitor conductor 177.

The color filters 230R, 230G, and 230B extend the red, green, and blue color filters 230R, 230G, and 230B in a direction parallel to the data line 171 along the pixel column defined by the data line 171. Are alternately formed in the pixel column.                     

Here, the red, green, and blue color filters 230R, 230G, and 230B are not formed at the end of the gate line 121 or the data line 171 to be connected to the external circuit. The edges of these 230R, 230G, and 230B overlap the upper portion of the data line 171. As such, the edges of the color filters 230R, 230G, and 230B are formed to overlap each other to block light leaking between the pixel areas, and the red, green, and blue color filters are overlapped together on the upper portion of the data line 171. It can also be arranged.

An interlayer insulating layer 180 is further formed on the color filters 230R, 230G, and 230B. The interlayer insulating layer 180 prevents the pigments of the color filters 230R, 230G, and 230B from flowing into the pixel electrode 190.

As such, when the color filter is formed on the thin film transistor array panel, a black matrix may be formed only on the thin film transistor array panel on the upper panel, thereby increasing the aperture ratio of the pixel.

A method of manufacturing the thin film transistor array panel according to the exemplary embodiment of the present invention described above will be described in detail with reference to FIGS. 16A to 17B.

16A and 17A are layout views at an intermediate stage in the method of manufacturing the thin film transistor array panel according to the third embodiment, FIG. 16B is a cross-sectional view taken along the line XVIb-XVIb ′ of FIG. 16A, and FIG. 17B is a cross-sectional view of FIG. 17A. Sectional drawing taken along the line XVIIb-XVIIb '.

First, as shown in FIGS. 3A to 5B of the first embodiment, the gate line 121, the storage electrode line 131, the gate insulating layer 140, the semiconductor layers 151 and 154, and the transparent insulating substrate 110 are provided. The ohmic contacts 161, 163, and 165 are formed. Next, the data line 171, the drain electrode 175, and the storage capacitor conductor 177 are formed on the ohmic contacts 161, 163, and 165.

Then, as shown in FIGS. 17A and 17B, the photosensitive organic materials including red, green, and blue pigments are applied in turn, and the red, green, and blue color filters 230R, 230G, and 230B are applied through respective photographic processes. Form in turn. In this case, a protective film (not shown) may be formed by stacking inorganic materials such as silicon nitride or silicon oxide, and then color filters may be formed. This protects the semiconductor layer from the pigment of the color filter.

When the red, green, and blue color filters 230R, 230G, and 230B are formed by a photo process using a mask, openings 235 and 237 are formed in portions corresponding to the drain electrode 175 and the conductive capacitor conductor 177. Form.

18A and 18B, an interlayer insulating layer 180 is formed by applying an organic material having a low dielectric constant of 4.0 or less on top of the color filters 230R, 230G, and 230B.

Then, the interlayer insulating layer 180 is patterned by a photolithography process using a mask to form contact holes 182, 185, and 187 exposing the openings 235 and 237. The method of forming the contact hole is the same as in the first or second embodiment.

Thereafter, as shown in FIGS. 14 and 15, a transparent conductive material such as ITO or IZO is deposited on the substrate 110, and the drain electrode is formed through the openings 235 and 237 and the contact holes 185 and 187 by a photolithography process. A pixel electrode 190 connected to the 175 is formed.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As such, in the present invention, the lower layer is formed to receive the stretching force and the upper layer is formed to receive the relatively compressive force to minimize the occurrence of hillock on the lower layer formed of aluminum. In addition, the formation of cracks in the upper layer can be minimized, thereby improving the contact characteristics of the upper conductive layer in contact with these wirings, thereby providing a high quality thin film transistor display panel without interrupting the signal.

Claims (15)

Insulation board, A gate line formed on the insulating substrate, A data line insulated from and intersecting the gate line, A thin film transistor connected to the gate line and the data line, A pixel electrode connected to the thin film transistor, At least one of the gate line and the data line is a first conductive film made of aluminum or an aluminum alloy, And a second conductive layer formed on the first conductive layer and having a compressive force relatively to that of the first conductive layer. In claim 1, And a red, green, and blue color filter formed on the insulating substrate and disposed under the pixel electrode. In claim 1, The thin film transistor includes a gate electrode which is a part of the gate line, a source electrode that is a part of the data line, a drain electrode connected to the pixel electrode, and a semiconductor disposed between the gate electrode and the source electrode and the drain electrode. . In claim 3, And the semiconductor except for the source electrode and the drain electrode have the same planar pattern as the data line and the drain electrode. In claim 1, The second conductive layer is formed of one of Mo, MoW, MoN, MoZr or MoNb. In claim 1, The aluminum alloy is AlNd thin film transistor array panel. In claim 5, The compressive force of Mo has a range of -1 GPa to 10 GPa, the compressive force of MoN and MoZr has a range of -2 GPa to 5 GPa, and the MoW has a range of -15 GPa to 15 GPa Transistor display panel. In claim 6, The compressive force of Al is in the range of -0.2 GPa to 0.4 GPa, and the compressive force of AlNd is in the range of 0.1 GPa to 0.4 GPa. Forming a gate line on the substrate, Forming a data line insulated from and intersecting the gate line; Forming a thin film transistor connected to the gate line and the data line; Forming a pixel electrode connected to the thin film transistor, Forming at least one of the gate line and the data line with a first conductive film made of aluminum or an aluminum alloy; And forming a second conductive film formed on the first conductive film and having a compressive force relatively to that of the first conductive film. In claim 9, And forming red, green, and blue color filters on the substrate and beneath the pixel electrodes. In claim 9, The second conductive film is formed of one of Mo, MoW, MoN, MoZr or MoNb. In claim 9, The aluminum alloy is formed of AlNd. In claim 11, The compressive force of Mo is in the range of -1 GPa to 10 GPa, and the compressive force of MoN and MoZr is in the range of -2 GPa to 5 GPa. In claim 12, The compressive force of Al is in the range of -0.2 GPa to 0.4 GPa, and the compressive force of AlNd is in the range of 0.1 GPa to 0.4 GPa. In claim 11, The MoN is formed by a sputtering process and is formed by injecting nitrogen gas during the sputtering process.

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