KR20050117055A - Thin film transistor array panel and method for manufacturing the same - Google Patents

Abstract

The thin film transistor array panel according to the present invention is formed on an insulating substrate and an insulating substrate, and is positioned between a source region and a drain region, a source region and a drain region, and a source region and a channel region, and a region between the drain region and the channel region. A semiconductor layer having a lightly doped region, a gate insulating film covering the semiconductor layer, a metal pattern corresponding to the channel region and the lightly doped region, a metal pattern corresponding to the channel region and the metal layer, and a gate electrode partially overlapping the channel region. A gate line, a data line having a source electrode formed on the first interlayer insulating film and a first interlayer insulating film formed on the gate line, and a drain formed on the first interlayer insulating film and electrically connected to the drain region. On the electrode, data line and drain electrode Claim that consists of second interlayer insulating film, is formed on the second interlayer insulating film comprises a pixel electrode connected to the drain electrode.

Description

Thin film transistor array panel and method for manufacturing the same {Thin film transistor array panel and method for manufacturing the same}

The present invention relates to a method for manufacturing a thin film transistor array panel, and more particularly, to a method for manufacturing a thin film transistor array panel using polycrystalline silicon as a semiconductor layer.

A thin film transistor array panel is used as a circuit board for independently driving each pixel in a liquid crystal display device, an organic electroluminescence (EL) display device, or the like.

The thin film transistor array panel includes a thin film transistor formed by crossing a scan signal line or a gate line for transmitting a scan signal and an image signal line or a data line for transmitting an image signal, disposed in each pixel, and connected to the gate line and the data line; And a pixel electrode connected to the thin film transistor.

The thin film transistor includes a semiconductor layer forming a channel and a gate electrode which is a part of the gate line, a source electrode which is a part of the data line, and a drain electrode facing the source electrode around the semiconductor layer. The thin film transistor is a switching device that transfers or blocks an image signal transmitted through a data line to a pixel electrode according to a scan signal transmitted through a gate line.

In this case, the semiconductor layer may be formed of amorphous silicon and crystalline silicon according to the crystal state of silicon. Amorphous silicon can be deposited at a low temperature to form a thin film, and is mainly used in semiconductor layers of switching elements of display devices that use glass having a low melting point as a substrate.

Since the polysilicon thin film transistor using polycrystalline silicon as a semiconductor layer has a much higher driving speed than an amorphous silicon thin film transistor, a driving circuit for driving a pixel together with the thin film transistor in the pixel region can be formed on the substrate together with the thin film transistor. have.

However, polysilicon thin film transistors require a low concentration doped region to prevent punch through, and in order to form such a low concentration doped region, a doping mask is formed to form a low concentration doped region by forming a spacer or the like on the sidewall of the gate electrode. Since it is necessary to use a photo-etching process to form a low concentration doped region, there is a problem that the manufacturing process is complicated.

The present invention provides a thin film transistor array panel and a method of manufacturing the same, which can minimize the doping process of forming a low concentration doped region.

A thin film transistor array panel according to the present invention for achieving the above object is formed on an insulating substrate, an insulating substrate, a channel region, a source region and a channel region and a drain located between the source region and the drain region, the source region and the drain region A semiconductor layer having a lightly doped region located between the region and the channel region, a gate insulating film covering the semiconductor layer, a metal pattern formed on the gate insulating film and corresponding to the channel region and the lightly doped region, formed on the metal pattern, and partially formed in the channel region. A gate line having an overlapping gate electrode, a first interlayer insulating film formed on the gate line, a data line having a source electrode formed on the first interlayer insulating film and electrically connected to the source region, and formed on the first interlayer insulating film, and having a drain A drain electrode electrically connected to the region, It formed on the second interlayer insulating film, the second interlayer insulating film that is formed on the data line and the drain electrode and includes a pixel electrode connected to the drain electrode.

Or a semiconductor formed over an insulating substrate, an insulating substrate, and having a source region and a drain region, a channel region located between the source region and a drain region, a source region and a channel region, and a lightly doped region located between the drain region and the channel region. A layer, a gate insulating film covering the semiconductor layer, a metal pattern formed on the gate insulating film and corresponding to the channel region and the lightly doped region, a gate line formed on the metal pattern and partially overlapping the channel region, and a gate line adjacent to each other. A data connecting portion electrically connecting the data metal piece formed between the lines, the gate line and the interlayer insulating film formed on the data metal piece, and the data metal piece formed on the interlayer insulating film and interposed with the gate line and positioned between the gate lines through a contact hole. On interlayer insulation film Form and comprises a pixel electrode that is connected through the contact hole and the drain region.

It is preferable to further include a blocking film formed on the entire surface of the substrate and positioned below the semiconductor layer.

The metal pattern may have a thickness of 80 to 120 nm, and the gate line may have a thickness of 200 to 300 nm.

In addition, the metal pattern and the gate line preferably have the same planar pattern. In this case, it is preferable that the boundary line of the gate line is formed inside the boundary line of the metal pattern, and the width of the metal pattern exposed out of the gate line is preferably equal to the width of the lightly doped region.

In addition, the metal pattern, the gate line, and the data metal piece preferably have the same planar pattern, and the boundary line of the gate line and the data metal piece is preferably formed inside the boundary line of the metal pattern.

According to another aspect of the present invention, there is provided a method of manufacturing a thin film transistor array panel, the method including forming a semiconductor layer on an insulating substrate, forming a gate insulating layer covering the semiconductor layer, and an etching condition with a conductive layer on the gate insulating layer. Stacking a conductive film for a gate having an etching rate faster than that of the conductive film, and patterning the gate conductive film and the conductive film by a photolithography process including etching conditions to form a gate line and a metal pattern; Forming a source region, a drain region, and a lightly doped region by doping a conductive impurity ion in the semiconductor layer using a metal pattern as a mask, forming a first interlayer insulating layer to cover the gate line and the semiconductor layer, and a first interlayer insulating layer Connected to the data line and the drain region having a source electrode connected to the source region thereon Which includes the step, the data line and the phase, forming a pixel electrode connected to the drain electrode on the second interlayer insulating film to form a second interlayer insulating film on the drain electrode to form a drain electrode.

Or forming a semiconductor layer over the insulating substrate, forming a gate insulating film covering the semiconductor layer, forming a gate conductive film having a faster etching rate than the conductive film and the conductive film on the gate insulating film, and forming the gate conductive film and the conductive film. Forming a gate line, a data metal piece, and a metal pattern by a photolithography process; forming a source region, a drain region, and a lightly doped region by doping conductive semiconductor impurity ions into the semiconductor layer using the gate line and the metal pattern as a mask; Forming an interlayer insulating film covering the line and data metal pieces; forming a data connection part connected to the source region and the data metal piece and a pixel electrode connected to the drain area on the interlayer insulating film.

The conductive impurity ions are preferably P-type.

In addition, the conductive film is preferably formed to a thickness of 80 to 120 nm, and the gate conductive film is preferably formed to a thickness of 200 to 300 nm.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, area, plate, etc. is over another part, this includes not only the part directly above the other part but also another part in the middle. On the contrary, when a part is just above another part, it means that there is no other part in the middle.

Next, a thin film transistor array panel according to an exemplary embodiment of the present invention will be described in detail with reference to the drawings.

1 is a layout view schematically illustrating a structure of a thin film transistor array panel according to an exemplary embodiment of the present invention.

As shown in FIG. 1, the thin film transistor array panel generates an image signal and a scan signal input to the pixel portion A to control the pixel portion A and the pixel portion A on which a plurality of pixels are disposed. It includes a driving circuit portion (B) which is arranged together for various peripheral circuit elements (not shown).

The pixel portion A includes a thin film transistor for controlling a pixel, a gate line transferring a scan signal or a scanning signal connected to the thin film transistor, a data line crossing the gate line and transferring an image signal, a pixel electrode, a gate line, and a data line. P-type thin film transistors and the like that are electrically connected and control image signals transmitted to the pixel electrodes are disposed. The driving circuit unit B is electrically connected to the gate line and the data line of the display area, and a plurality of driving elements and the like including a P-type thin film transistor for outputting an image signal, a scan signal, and the like are disposed.

Next, a thin film transistor, which is a basic element among the pixel structure of the pixel unit A and the driving element of the driver B according to an exemplary embodiment of the present invention, will be described in detail with reference to the accompanying drawings.

FIG. 2 is a layout view illustrating a unit pixel structure formed in a pixel portion of a thin film transistor array panel according to an exemplary embodiment of the present invention. FIG. 3 is a cross-sectional view taken along line III-III ′ of FIG. 2. 4 is a layout view of a driving unit of a thin film transistor array panel according to an exemplary embodiment of the present invention, and FIG. 5 is a cross-sectional view taken along the line VV ′ of FIG. 4.

2 to 5, a blocking film 111 made of silicon oxide or silicon nitride is formed on the transparent insulating substrate 110, and P-type impurities are formed in the pixel portion A on the blocking film 111. A first semiconductor layer 150a is formed that includes a heavily doped source region 153a and a drain region 155a and a channel region 154a disposed therebetween.

A low concentration doped region 152a is formed between the source region 153a and the channel region 154a and between the drain region 155a and the channel region 154a in which the P-type conductive impurity ions are lightly doped.

Similarly to the pixel portion A, a second region having a source region 153b, a drain region 155b, and a channel region 154b therebetween that is heavily doped with P-type impurities, similarly to the pixel portion A, on the blocking film of the driving unit B. The semiconductor layer 150b is formed. A low concentration doped region 152b is formed between the source region 153b and the channel region 154b and between the drain region 155b and the channel region 154b in which P-type impurities are lightly doped.

A gate insulating layer 140 made of silicon oxide or silicon nitride is formed on the substrate 110 including the first and second semiconductor layers 150a and 150b.

Metal patterns 120a and 120b are formed on the lightly doped regions 152a and 152b of the pixel portion A and the driver B and the gate insulating layer 140 corresponding to the channel regions 154a and 154b.

A gate line 121 extending in one direction is formed on the gate insulating layer 140 of the pixel portion A, and a portion of the gate line 121 extends to correspond to the metal pattern 120a corresponding to the channel region 154a. A portion of the overlapped gate line 121 is used as the first gate electrode 124a as a gate electrode of the thin film transistor. One end of the gate line 121 may be formed wider than the width of the gate line 121 in order to connect to an external circuit (not shown).

In addition, the storage electrode line 131 for increasing the storage capacitance of the pixel is parallel to the gate line 121 and is formed in the same layer with the same material. A portion of the storage electrode line 131 overlapping the semiconductor layer 150a becomes the storage electrode 133, and the semiconductor layer 150a overlapping the storage electrode 133 becomes the storage electrode region 157.

The second gate electrode 124b overlapping the metal pattern 120b corresponding to the channel region 154b is formed on the gate insulating layer 140 of the driving unit B. The second gate electrode 124 is connected to a driving circuit and a signal line (not shown) for applying a gate signal.

The metal pattern 120 is formed of aluminum, aluminum alloy, or chromium in a thickness of 80 to 120nm, the gate line 121 and the sustain electrode line 131 is made of aluminum, aluminum alloy, molybdenum, molybdenum alloy, etc. 200 ~ 300nm It is preferable to form in thickness. The width where the metal pattern 120 is exposed on both the gate line 121 and the storage electrode line is preferably 1 μm or less. When the metal pattern 120 is aluminum or an aluminum alloy including aluminum, the gate line 121 and The storage electrode line 131 is preferably molybdenum or molybdenum alloy, and when the metal pattern 120 is chromium, the gate line 121 and the storage electrode line 131 are preferably aluminum or aluminum alloy.

The first interlayer insulating film 601 made of silicon oxide, silicon nitride, or the like is formed on the gate line 121, the gate electrodes 124a and 124b, the storage electrode 133, and the storage electrode line 131. The first interlayer insulating layer 601 includes first and third contact holes 161 and 163 and second and fourth contact holes 162 and 164 exposing the source regions 153a and 153b and the drain regions 155a and 155b. ).

A data line 171 is formed on the first interlayer insulating layer 601 of the pixel portion A to define a pixel region by crossing the gate line 121. A portion or branched portion of the data line 171 is connected to the source region 153a through the first contact hole 161, and the portion 173a connected to the source region 153a is a source electrode of the thin film transistor. Used as One end of the data line 171 may be formed wider than the width of the data line 171 to be connected to an external circuit (not shown).

The drain electrode 175a is formed on the same layer as the data line 171 and is separated from the source electrode 173a and connected to the drain region 155a through the second contact hole 162.

A source electrode 173b and a drain electrode 175b connected to the source region 153b, the drain region 155b are formed on the first interlayer insulating layer 601 of the driving unit B, respectively. The source electrode 173b and the drain electrode 175b are also connected to data lines (not shown) for applying a voltage to them.

The drain electrode 175 and the data line 171 may be formed of a conductive film such as aluminum (Al) or an aluminum alloy such as an aluminum alloy. In addition to the conductive film, other materials such as indium tin oxide (ITO) or IZO ( chromium (Cr), titanium (Ti), tantalum (Ta), molybdenum (Mo) and their alloys (eg molybdenum-tungsten (MoW) alloys) with good physical, chemical and electrical contact properties with indium zinc oxide It may have a multilayer film structure including other conductive films made up. An example of such a structure is a chromium / aluminum-neodymium (AlNd) alloy. In the case of the double film, the aluminum-based conductive film is preferably positioned below the other conductive film, and in the case of the triple film, the aluminum-based conductive film is preferably positioned as the intermediate layer.

The second interlayer insulating layer 602 is formed on the entire surface of the first interlayer insulating layer 601 on which the first drain electrode 175a and the data line 171 are formed. The second interlayer insulating layer 602 has a fifth contact hole 165 exposing the first drain electrode 175a in the pixel portion A. FIG.

The pixel electrode 190 connected to the first drain electrode 175a is formed on the second interlayer insulating layer 602. The second interlayer insulating layer 602 is a layer formed according to the structure of the thin film transistor formed in the pixel portion A and may not be formed in the driving portion B in some cases.

A method of manufacturing a thin film transistor array panel according to an exemplary embodiment of the present invention described above will be described in detail with reference to the accompanying drawings.

Hereinafter, one unit pixel including the P-type thin film transistor in the pixel unit A and the P-type thin film transistor in the driving unit B will be described as an example.

6A and 6B are layout views at an intermediate stage in the method of manufacturing a thin film transistor array panel according to the present invention, and FIG. 6C is a cross-sectional view taken along the line VIc-VIc′-VIc ″ of FIGS. 6A and 6B. FIG. 7B is a layout view at the next stage of FIGS. 6A and 6B, FIG. 7C is a cross-sectional view taken along the line VIIc-VIIc′-VIIc ″ in FIGS. 7A and 7B, and FIG. 8 is a cross-sectional view at the next stage of FIG. 7C. 9A and 9B are layout views of the next step of FIG. 8, FIG. 9C is a cross-sectional view taken along the line IXc-IXc′-IXc ″ of FIGS. 9A and 9B, and FIGS. 10A and 10B are FIGS. 9A and 9B. 9B is a layout view in the next step, and FIG. 10C is a cross-sectional view taken along the line Xc-Xc'-Xc "of FIGS. 10A and 10B.

First, as shown in FIGS. 6A to 6C, the blocking layer 111 is formed on the transparent insulating substrate 110. In this case, glass, quartz, sapphire, or the like may be used as the transparent insulating substrate 110, and the blocking layer 111 is formed by depositing silicon oxide (SiO ₂ ) or silicon nitride (SiNx) to a thickness of about 1,000 GPa. . Subsequently, impurities such as a native oxide film on the blocking film 111 are removed by cleaning.

Next, an amorphous silicon film not doped with impurities is formed to a thickness of 500 kPa or more by a method such as chemical vapor deposition. Preferably it is formed to a thickness of 500 ~ 1,200Å. Then, the amorphous silicon film is crystallized by an ELA (eximer laser anneal) method, a furnace heat treatment method, a sequential lateral solidification (SLS) method, a metal induced crystallization (MIC) method to form a polycrystalline silicon film.

Subsequently, the first and second semiconductor layers 150a and 150b made of polycrystalline silicon are formed on the pixel portion A and the driving portion B by patterning by a photolithography process using a photomask.

Next, as shown in FIGS. 7A to 7C, the first and second conductive layers are sequentially stacked on the gate insulating layer 140, and then the gate line 121 and the metal pattern 120 are formed by a photolithography process using a mask. .

At this time, it is preferable that the first conductive film is formed in the range of 80 to 120 nm, and the second conductive film has a thickness of 200 to 300 nm.

The first conductive film and the second conductive film are preferably formed of a material having an etching selectivity with respect to one etching condition, and the second conductive film is formed of a material having an etching rate faster than that of the first conductive film. This is because the edges of the first conductive film are exposed to the outside of the second conductive film to form sidewalls of the first and second conductive films with a stepped step so that the exposed edges of the first conductive film can be used as a doping mask. to be.

For example, when the metal pattern 120 is aluminum or an aluminum alloy containing aluminum (eg, aluminum neodymium), the gate line 121 and the storage electrode line 131 may be formed of molybdenum or molybdenum alloy (eg, , Molybdenum tungsten), and when the metal pattern 120 is chromium, the gate line 121 and the sustain electrode line 131 are preferably aluminum or an aluminum alloy (for example, aluminum neodymium).

Next, as shown in FIG. 8, P-type conductivity type impurity ions are implanted into the semiconductor layers 150a and 150b using the gate lines 121 and the metal patterns 120a and 120b as a mask to form the channel regions 154a and 154b. Define source / drain regions 153a, 153b, 155a, and 155b and lightly doped regions 152a and 152b.

The implantation of ions is set to a certain concentration at a certain depth, and then doping is performed. The distribution of ions around a target point shows a normal distribution curve. Therefore, in the embodiment of the present invention, if the ion is implanted with the target point in the source / drain region, since the lightly doped region is located at the edge of the normal distribution curve, the ion is doped at a lower concentration than the source / drain region so that the lightly doped region 152 is formed. To achieve.

In this case, in order to control the doping concentrations of the lightly doped regions 152a and 152b, the thicknesses of the metal pattern 120 and the gate line 121 may be adjusted according to process conditions (eg, doping energy or doping amount, etc.). To adjust the width, the etching conditions (eg, etching time or etchant) may be variously changed.

As such, in the exemplary embodiment of the present invention, the lightly doped region and the source / drain region may be formed by one doping process, thereby minimizing the process. In addition, by forming the same thin film transistor in the pixel portion and the driver portion, the doping process performed in each of the pixel portion and the driver portion can be simplified.

Next, as shown in FIGS. 9A to 9C, an insulating material is laminated on the entire surface of the substrate 110 including the gate electrode 124a in the pixel region and the gate electrode 124b in the driving unit to form the first interlayer insulating layer 601. Form. In this case, the first interlayer insulating layer 601 may be formed of silicon oxide, silicon nitride, or the like.

Subsequently, the first to fourth contact holes 161 to 164 exposing the source region 153a and the drain region 155a of the pixel portion A and the driving portion B, respectively, to the first interlayer insulating layer 601 by a photolithography method. ).

Thereafter, a data conductive layer is formed on the first interlayer insulating layer 601 including the first to fourth contact holes 164, and then the data line having the source electrode 173a of the pixel portion A by a photolithography process. 171a, the drain electrode 175a, and the source electrode 173b and the drain electrode 175b of the driver B are formed.

The data line 171a of the pixel portion A is connected to the source region 153a through the first contact hole 161, and the drain electrode 175a is connected to the drain region 155a through the second contact hole 162. Connect with In addition, the source electrode 173b of the driving unit B is connected to the source region 153b through the third contact hole 163, and the drain electrode 175b is connected to the drain region 155b through the fourth contact hole 164. Connect with

Next, as shown in FIGS. 10A to 10C, a second interlayer insulating layer 602 is formed on the source electrodes 173a and 173b and the drain electrodes 175a and 175b, and then etched by a photolithography process to form a fifth contact hole. Form 165.

The second interlayer insulating film 602 has excellent planarization characteristics and is formed of an organic material having photosensitivity, a-Si: C: O, a-Si: formed by plasma enhanced chemical vapor deposition (PECVD). Low dielectric constant insulating materials such as O: F or silicon nitride, which is an inorganic material.

2 to 5, an indium tin oxide (ITO), an indium zinc oxide (IZO), and the like, which are transparent materials, are deposited on the second interlayer insulating layer 602 including the inside of the fifth contact hole 165. Afterwards, the contact auxiliary member (not shown) connected to the pixel electrode 190 and one end of the gate line or the data line is patterned. The pixel electrode 190 is connected to the drain electrode 175a of the pixel area through the fifth contact hole 165.

When the second interlayer insulating layer 602 is formed of a low dielectric constant material of 4.0 or less, the pixel electrode 190 may overlap the data line 171 to improve the aperture ratio of the pixel.

As described above, the gate line and the metal pattern are formed of a material having a large difference in etching selectivity according to the exemplary embodiment of the present invention, thereby simultaneously forming a source / drain region and a low concentration doped region, which are highly doped regions, in a single doping process, thereby simplifying a manufacturing method. can do.

 Second Embodiment

FIG. 11 is a layout view of a thin film transistor array panel for a liquid crystal display according to another exemplary embodiment. FIG. 12 is a cross-sectional view taken along the line XII-XII′-XII of FIG. 11.

In Embodiment 2, the data connection part 171b and the pixel electrode 190 are formed on the same layer using the same material, and the pixel electrode 190 and the data connection part 171b are formed on the source and drain regions 153 and 155 of the semiconductor layer 150. ), Since the contact holes 161 and 162 for connecting to the plurality of holes are simultaneously formed, the number of masks can be reduced as compared with the first embodiment.

More specifically, as shown in FIGS. 11 and 12, the blocking layer 111 is formed on the transparent insulating substrate 110. A semiconductor layer including a source region 153, a drain region 155, and a channel region 154 formed of an intrinsic semiconductor between the conductive layer and the dopant having a high concentration of conductive impurities on the blocking layer 111. 150 is formed. The conductive dopant is less doped than the source and drain regions 153 and 155 between the source region 153 and the channel region 154 and between the drain region 155 and the channel region 154 of the semiconductor layer 150. It is.

The gate insulating layer 140 is formed on the substrate 110 including the semiconductor layer 150. The metal pattern 120 is formed on the gate doped region 140 corresponding to the lightly doped region 152 and the channel region 154.

A gate line 121 extending in one direction is formed on the gate insulating layer 140, and a portion of the gate line 121 extends to correspond to the channel region 154 and overlaps the metal pattern 120. A portion of the gate line 121 is used as the gate electrode of the thin film transistor as the first gate electrode 124. One end of the gate line 121 may be formed wider than the width of the gate line 121 in order to connect to an external circuit (not shown).

In addition, the storage electrode line 131 for increasing the storage capacitance of the pixel is parallel to the gate line 121 and is formed in the same layer with the same material. A portion of the storage electrode line 131 overlapping the semiconductor layer 150 becomes the storage electrode 133, and the semiconductor layer 150 overlapping the storage electrode 133 becomes the storage electrode region 157.

The data metal piece 171a is formed at a distance from the gate line 121 and extends in a direction perpendicular to the gate line 121, and is formed on the same layer as the gate line 121. The data metal piece 171a is formed not to be connected to the gate line 121 between two adjacent gate lines 121. In addition, the data metal piece 171a may enlarge and form one end of the data metal piece 171a in the outermost row in order to receive an image signal from an external circuit (not shown).

The gate line 121 and the data metal piece 171a have the same planar pattern as the metal pattern 120, and the gate line 121 and the data metal piece 171a are formed to be narrower than the metal pattern 120 by the width of the lightly doped region. It is.

The metal pattern 120 has a thickness of 80 to 120 nm, the gate line 121, and the storage electrode line 131 to a thickness of 200 to 300 nm. When the metal pattern 120 is formed of aluminum neodymium, the gate line 121 and the storage electrode line 131 are formed of molybdenum tungsten, and when the metal pattern 120 is formed of chromium, the gate line 121 and the storage line are formed of chromium. The electrode line 131 is preferably formed of aluminum neodymium.

An interlayer insulating layer 160 is formed on the gate insulating layer 140 including the gate line 121 and the storage electrode line 131.

The data connection part 171b, the pixel electrode 190, and the contact auxiliary member 82 are formed on the interlayer insulating layer 160. The data connection part 171b is formed to cross the gate line 121 and the storage electrode line 131 in the vertical direction.

The data metal piece 171a is connected to the data connecting portion 171b through the third contact hole 163 formed in the interlayer insulating layer 160, and the data connecting portion 171b is connected to the source through the first contact hole 161. It is connected to the area 153. That is, the data metal pieces 171a separated by the data connection part 171b are connected across the gate line 121 and the storage electrode line 131. The pixel electrode 190 is connected to the drain region 155 through a second contact hole 162 formed over the interlayer insulating layer 160 and the gate insulating layer 140, and the contact auxiliary member 82 is interlayered. The fourth contact hole 164 formed in the insulating layer 160 is connected to one end of the gate line 121 and the data metal piece 171a, respectively.

The contact auxiliary member 82 is not essential to serve to protect adhesion between the end of the data line 171a and the external device and to protect them, and application thereof is optional. In particular, when the driving circuit is formed together with the thin film transistor in the display area, it is not formed.

A method of manufacturing the thin film transistor array panel according to the second embodiment of the present invention described above will be described in detail with reference to FIGS. 11 and 12 described with reference to FIGS. 13A through 16B.

13A, 14A, and 16A are layout views in an intermediate step of manufacturing a thin film transistor array panel according to a second exemplary embodiment of the present invention, and FIG. 13B is a cross-sectional view taken along the line XIIIb-XIIIb'-XIIIb "of FIG. 13A. FIG. 14B is a cross-sectional view taken along the line XIVb-XIVb′-XIVb ″ of FIG. 14A, FIG. 15 is a cross-sectional view at the next step of FIG. 14B, FIG. 16A is a layout view at the next step of FIG. 15A, and FIG. 16B is It is sectional drawing cut along the XVIb-XVIb'-XVIb "line of FIG. 16A.

First, as shown in FIGS. 13A and 13B, the blocking layer 111 is formed on the transparent insulating substrate 110. In this case, glass, quartz, sapphire, or the like may be used as the transparent insulating substrate 110, and the blocking layer 111 is formed by depositing silicon oxide (SiO ₂ ) or silicon nitride (SiNx) to a thickness of about 1,000 GPa. . Subsequently, impurities such as a native oxide film on the blocking film 111 are removed by cleaning.

Next, an amorphous silicon film not doped with impurities is formed to a thickness of 500 kPa or more by a method such as chemical vapor deposition. Preferably it is formed to a thickness of 500 ~ 1,200Å. Then, the amorphous silicon film is crystallized by ELA method, furnace heat treatment method, SLS method, MIC method or the like to form a polycrystalline silicon film.

Thereafter, the polycrystalline silicon film is photo-etched using a photomask to form a semiconductor layer 150 made of polycrystalline silicon.

The gate insulating layer 140 is formed by depositing an insulating material such as silicon oxide on the semiconductor layer 150 by a chemical vapor deposition method.

Next, as shown in FIGS. 14A and 14B, first and second conductive layers are stacked on the gate insulating layer 140. At this time, the first conductive film is formed to a thickness of 80 ~ 120nm, the second conductive film is 200 ~ 300nm.

The first conductive film and the second conductive film are preferably formed of a material having an etching selectivity with respect to one etching condition, and the second conductive film is formed of a material having an etching rate faster than that of the first conductive film. This is because the edges of the first conductive film are exposed to the outside of the second conductive film to form sidewalls of the first and second conductive films with a stepped step so that the exposed edges of the first conductive film can be used as a doping mask. to be.

For example, when the metal pattern 120 is aluminum or an aluminum alloy containing aluminum (eg, aluminum neodymium), the gate line 121 and the storage electrode line 131 may be formed of molybdenum or molybdenum alloy (eg, , Molybdenum tungsten), and when the metal pattern 120 is chromium, the gate line 121 and the sustain electrode line 131 are preferably aluminum or an aluminum alloy (for example, aluminum neodymium).

Thereafter, a photoresist pattern is formed on the second conductive layer by a photo process, and then the first and second conductive layers are wet-etched using the photoresist pattern as an etch mask to form the metal pattern 120, the gate line 121, and the data metal piece 171a. do.

At this time, the metal pattern 120 and the gate line 121 are formed stepped due to the difference in the etching selectivity between the first and second conductive layers, and the width difference between the metal pattern 120 and the gate line 121 is necessary for the width of the lightly doped region. As much as different form.

Sides of the gate line 121, the storage electrode line 131, and the data metal piece 171a are formed to be tapered to increase adhesion to the upper layer. If the storage capacitor is sufficient, the storage electrode line 131 is not formed.

Next, as shown in FIG. 15, the P-type conductivity type impurity ions are implanted into the semiconductor layer 150 in the same manner as in the first embodiment by using the gate lines 121 and the metal patterns 120a and 120b as masks. Source / drain regions 153 and 155 and lightly doped region 152 defining 154 are formed.

Next, as illustrated in FIGS. 16A and 16B, an interlayer insulating layer 160 is formed of an insulating material on the entire surface of the substrate on which the source region 153, the drain region 155, and the channel region 154 are formed. The interlayer insulating layer 160 is an organic material having excellent planarization characteristics and a photosensitive property, a low dielectric constant insulating material such as a-Si: C: O, a-Si: O: F, or inorganic material formed by plasma chemical vapor deposition. It may be formed of silicon nitride or the like.

Thereafter, the first contact hole 161 exposing the source region 153, the second contact hole 162 exposing the drain region 155, and the data metal piece 171a are exposed on the interlayer insulating layer 160. The third contact hole 163 and the fourth contact hole 164 exposing one end of the data metal piece 171a are formed.

When the interlayer insulating film is formed of an organic material having photosensitivity, the contact hole may be formed only by a photographic process.

11 and 12, a conductive film is formed of a transparent conductive material on the interlayer insulating layer 160 including the first to fourth contact holes 161 to 164, and then patterned to form a data connection part 171b. The pixel electrode 190 and the contact auxiliary member 82 are formed.

The data metal piece 171a is connected to the data connector 171b through the third contact hole 163, and the data connector 171b is connected to the source region 153 through the first contact hole 161. The pixel electrode 190 is connected to the drain region 155 through the second contact hole 162, and the contact auxiliary member 82 is connected to the data metal piece 171a through the fourth contact hole 164. .

In this case, when the interlayer insulating layer 160 is formed of an organic material having a low dielectric constant, the pixel electrode 190 may overlap the gate line 121 and the data metal piece 171b to improve the aperture ratio of the pixel region.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, the doping regions having different concentrations may be formed by one doping process by patterning thin films having different etch ratios under one etching condition to have different widths. Therefore, the doping process may be minimized in the manufacturing process of the thin film transistor array panel, thereby improving productivity and minimizing the manufacturing cost.

1 is a layout view schematically illustrating a structure of a thin film transistor array panel according to an exemplary embodiment of the present invention.

FIG. 2 is a layout view illustrating a unit pixel structure formed in a pixel unit in a thin film transistor array panel according to an exemplary embodiment of the present invention.

3 is a cross-sectional view taken along line III-III 'of FIG. 2,

4 is a layout view of a driver of a thin film transistor array panel according to an exemplary embodiment of the present invention.

5 is a cross-sectional view taken along the line VV ′ of FIG. 4;

6A and 6B are layout views at an intermediate stage in the method of manufacturing the thin film transistor array panel according to the present invention.

FIG. 6C is a cross-sectional view taken along the line VIc-VIc′-VIc ″ of FIGS. 6A and 6B;

7A and 7B are layout views at the next stage of FIGS. 6A and 6B,

FIG. 7C is a cross-sectional view taken along the line VIIc-VIIc′-VIIc ″ of FIGS. 7A and 7B;

8 is a cross-sectional view at the next step of FIG. 7C,

9A and 9B are layout views in the next step of FIG. 8,

9C is a cross-sectional view taken along the line IXc-IXc′-IXc ″ of FIGS. 9A and 9B;

10A and 10B are layout views at the next stage of FIGS. 9A and 9B,

10C is a cross-sectional view taken along the line Xc-Xc′-Xc ″ of FIGS. 10A and 10B;

11 is a layout view of a thin film transistor array panel for a liquid crystal display according to another exemplary embodiment of the present invention.

12 is a cross-sectional view taken along the line XII-XII′-XII ″ of FIG. 11,

13A, 14A, and 16A are layout views in an intermediate step of manufacturing a thin film transistor array panel according to a second exemplary embodiment of the present invention.

FIG. 13B is a cross-sectional view taken along the line XIIIb-XIIIb′-XIIIb ″ of FIG. 13A;

FIG. 14B is a cross-sectional view taken along the line XIVb-XIVb′-XIVb ″ of FIG. 14A;

FIG. 15 is a cross sectional view at the next step of FIG. 14B;

FIG. 16A is a layout view at the next step of FIG. 15A,

16B is a cross-sectional view taken along the line XVIb-XVIb'-XVIb "of FIG. 16A.

※ Explanation of symbols on main parts of drawing ※

110: insulated substrate 121: gate line

124: gate electrode 131: sustain electrode line

133 sustain electrode 140 gate insulating film

153: source region 154: channel region

155: drain region 171: data line

173 Source electrode 175 Drain electrode

190: pixel electrode

160, 601, 602: interlayer insulating film

Claims (12)

Insulation board, A semiconductor formed on the insulating substrate and having a source region and a drain region, a channel region located between the source region and a drain region, a source region and a channel region, and a lightly doped region located between the drain region and the channel region layer, A gate insulating film covering the semiconductor layer, A metal pattern formed on the gate insulating layer and corresponding to the channel region and the lightly doped region, A gate line formed on the metal pattern and having a gate electrode partially overlapping the channel region; A first interlayer insulating film formed over the gate line, A data line formed on the first interlayer insulating layer and having a source electrode electrically connected to the source region; A drain electrode formed on the first interlayer insulating layer and electrically connected to the drain region; A second interlayer insulating film formed on the data line and the drain electrode, And a pixel electrode formed on the second interlayer insulating layer and electrically connected to the drain electrode. Insulation board, A semiconductor formed on the insulating substrate and having a source region and a drain region, a channel region located between the source region and a drain region, a source region and a channel region, and a lightly doped region located between the drain region and the channel region layer, A gate insulating film covering the semiconductor layer, A metal pattern formed on the gate insulating layer and corresponding to the channel region and the lightly doped region, A gate line formed on the metal pattern and having a gate electrode partially overlapping the channel region; A data metal piece formed between the gate lines adjacent to each other, An interlayer insulating film formed on the gate line and the data metal piece, A data connection part formed on the interlayer insulating film and electrically connecting the data metal piece intersecting the gate line and positioned between the gate line through a contact hole; And a pixel electrode formed on the interlayer insulating layer and connected to the drain region through a contact hole. The method of claim 1 or 2, The thin film transistor array panel of claim 1, further comprising a blocking layer formed on the entire surface of the substrate and positioned under the semiconductor layer. In claim 1, The metal pattern has a thickness of 80 ~ 120nm and the gate line has a thickness of 200 ~ 300nm. In claim 1, The thin film transistor array panel of which the metal pattern and the gate line have the same planar pattern. In claim 5, The boundary line of the gate line is formed inside the boundary line of the metal pattern. In claim 6, And a width of the metal pattern exposed out of the gate line is equal to a width of the lightly doped region. In claim 2, The metal pattern, the gate line, and the data metal piece have the same planar pattern, and a boundary line between the gate line and the data metal piece is formed inside the boundary line of the metal pattern. Forming a semiconductor layer on the insulating substrate, Forming a gate insulating film covering the semiconductor layer; Sequentially stacking a conductive film on the gate insulating film and a gate conductive film having an etching rate faster than that of the conductive film with respect to one etching condition; Patterning the gate conductive layer and the conductive layer by a photolithography process including the etching conditions to form a gate line and a metal pattern; Doping the semiconductor layer using the gate line and the metal pattern as a mask to form a source region, a drain region, and a lightly doped region; Forming a first interlayer insulating film to cover the gate line and the semiconductor layer; Forming a data line having a source electrode connected to the source region and a drain electrode connected to the drain region on the first interlayer insulating layer; Forming a second interlayer insulating film on the data line and the drain electrode; And forming a pixel electrode connected to the drain electrode on the second interlayer insulating layer. Forming a semiconductor layer on the insulating substrate, Forming a gate insulating film covering the semiconductor layer; Forming a conductive film on the gate insulating film and a gate conductive film having an etching rate faster than that of the conductive film, Photo-etching the gate conductive film and the conductive film to form a gate line, a data metal piece, and a metal pattern; Doping the semiconductor layer using the gate line and the metal pattern as a mask to form a source region, a drain region, and a lightly doped region; Forming an interlayer insulating film covering the gate line and the data metal piece; Forming a data connection part connected to the source region and the data metal piece and a pixel electrode connected to the drain area on the interlayer insulating layer. The method of claim 9 or 10, The conductive impurity ion is a P-type thin film transistor display panel manufacturing method. The method of claim 9 or 10, The conductive film is formed in a thickness of 80 ~ 120nm, the gate conductive film is formed in a thickness of 200 ~ 300nm manufacturing method of a thin film transistor array panel.