KR100992137B1 - Thin film transistor array panel and manufacturing method thereof - Google Patents

Abstract

The thin film transistor array panel according to the present invention is formed on an insulating substrate, an insulating substrate and is located between a source region and a drain region, a channel region between the source region and a drain region, between the source region and the channel region, and between the drain region and the channel region. A semiconductor layer having a low concentration doped region, a gate insulating layer formed on the semiconductor layer, a gate line formed on the gate insulating layer, and having a gate electrode overlapping the channel region and the low concentration doped region, and formed on the source region and the drain line, respectively. A first interlayer insulating film having first and second contact holes exposing regions, a data line having a source electrode formed on the first interlayer insulating film and connected to the source region through the first contact hole, and formed on the interlayer insulating film and having a second Drain electrode and data line connected to drain region through contact hole A second interlayer insulating film formed on the drain electrode and having a third contact hole exposing the drain electrode, and a pixel electrode formed on the second interlayer insulating film and connected to the drain electrode, wherein the source region and the drain region are connected to the channel region. Is filled.

Thin Film Transistors, LDD, Polycrystalline

Description

Thin film transistor array panel and manufacturing method thereof

1 is a layout view of a thin film transistor array panel for describing an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along the line II-II 'of FIG. 1,

3A is a layout view at an intermediate stage of manufacturing a thin film transistor array panel according to a first exemplary embodiment of the present invention;

3B is a cross-sectional view taken along the line IIIb-IIIb ′ of FIG. 3A;

4 is a cross-sectional view at the next step of FIG. 3B,

FIG. 5A is a layout view in the next step of FIG. 4,

5B is a cross-sectional view taken along the line Vb-Vb ′ of FIG. 5A;

FIG. 6A is a layout view at the next step of FIG. 5A, and FIG.

FIG. 6B is a cross-sectional view taken along the line VIb-VIb ′ of FIG. 6A;

FIG. 7A is a layout view at the next step of FIG. 6A,

FIG. 7B is a cross-sectional view taken along the line VIIb-VIIb ′ of FIG. 7A;

8 is a layout view of a thin film transistor array panel for a liquid crystal display according to a second exemplary embodiment of the present invention.                 

9 is a cross-sectional view taken along the line IX-IX'-IX "of FIG. 8,

10A is a layout view at an intermediate stage of manufacturing a thin film transistor array panel according to a second exemplary embodiment of the present invention.

FIG. 10B is a cross-sectional view taken along the line Xb-Xb'-Xb "of FIG. 10A,

11 is a sectional view at the next step of FIG. 10b,

12A is a layout view at the next step of FIG. 11,

12B is a cross-sectional view taken along the line XIIb-XIIb′-XIIb ″ of FIG. 12A, and

FIG. 13A is a layout view at the next step of FIG. 12A, and FIG.

FIG. 13B is a cross-sectional view taken along the line XIIIb-XIIIb'-XIIIb ″ of FIG. 13A.

※ Explanation of symbols on main parts of drawing ※

110: insulated substrate 121: gate line

124: gate electrode 131: sustain electrode line

133 sustain electrode 140 gate insulating film

150: semiconductor layer 153: source region

154: channel region 155: drain region

171: data line 173: source electrode

175: drain electrode 190: pixel electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor array panel and a method of manufacturing the same, and more particularly, to a thin film transistor array panel using polycrystalline silicon as a semiconductor layer and a method of manufacturing the same.

A thin film transistor (TFT) is used as a circuit board for independently driving each pixel in a liquid crystal display device, an organic electroluminescence (EL) display device, or the like. The thin film transistor array panel includes a scan signal line or a gate line for transmitting a scan signal and an image signal line or a data line for transferring an image signal, and includes a thin film transistor connected to the gate line and the data line, a pixel electrode connected to the thin film transistor, and the like. It is included.

The thin film transistor includes a semiconductor layer forming a channel and a gate electrode connected to the gate line, a source electrode connected to the data line and a drain electrode facing the source electrode with respect to the semiconductor layer.

The thin film transistor is a switching element that controls an image signal transmitted to a pixel electrode through a data line according to a scan signal transmitted through a gate line.

Since the polysilicon thin film transistor using polycrystalline silicon as a semiconductor layer has a much higher driving speed than an amorphous silicon thin film transistor, a driving circuit for driving a pixel together with the thin film transistor in the pixel region can be formed on the substrate together with the thin film transistor. have.

However, the polysilicon thin film transistor needs a low concentration doped region to prevent punch through. To form such a low concentration doped region, a metal film having an etching ratio different from that of the gate electrode is formed, or a spacer is formed on the sidewall of the gate electrode. Since it is necessary to use as a doping mask to form a low concentration doping region to form a low concentration doping region to form a photo-etching process additionally or there is a problem that the manufacturing process is complicated.

The present invention for solving the above problems provides a thin film transistor array panel and a method of manufacturing the same that can improve the reliability of the device while simplifying the process.

In order to achieve the above object, the channel thickness of the thin film transistor is formed to be thinner than the source and drain regions.

Specifically, the thin film transistor array panel according to the present invention is formed on an insulating substrate, an insulating substrate and a source region and a drain region, a channel region located between the source region and the drain region, between the source region and the channel region, the drain region and the channel region. A semiconductor layer having a lightly doped region interposed therebetween, a gate insulating film formed on the semiconductor layer, a gate line formed on the gate insulating film and having a gate electrode overlapping the channel region and the lightly doped region, and formed on the source A first interlayer insulating film having first and second contact holes exposing the region and a drain region, a data line having a source electrode formed on the first interlayer insulating film and connected to the source region through the first contact hole, and formed on the interlayer insulating film Drain and connected to the drain region through the second contact hole. And a second interlayer insulating layer formed on the data line and the drain electrode and having a third contact hole exposing the drain electrode, and a pixel electrode formed on the second interlayer insulating layer and connected to the drain electrode. It is stepped with the channel region.

Or a semiconductor formed over an insulating substrate, an insulating substrate, and having a source region and a drain region, a channel region located between the source region and a drain region, a source region and a channel region, a low concentration doping region located between the drain region and the channel region. A gate line formed on the layer, the semiconductor layer, and the gate insulating layer, the gate line having a gate electrode overlapping the channel region and the lightly doped region, and positioned at a predetermined distance apart from a neighboring gate line, in a direction perpendicular to the gate line. An interlayer insulating film formed on the extended data metal piece, the gate line and the data metal piece, and a data connection part formed on the interlayer insulating film intersecting the gate line to electrically connect the data metal piece through the contact hole, and formed through the contact hole. Drain area And a pixel electrode connected to the source electrode, wherein the source region and the drain region are stepped with the channel region.

In this case, the channel region is preferably thinner than the source region and the drain region.

According to another aspect of the present invention, there is provided a method of manufacturing a thin film transistor array panel, the method comprising: forming an amorphous silicon film on an insulating substrate, ion implanting conductive impurity ions on the amorphous silicon film to form a low concentration doped region; Crystallizing and patterning the amorphous silicon film to form a semiconductor layer, forming a photoresist pattern on the semiconductor layer, defining a channel region by removing a portion of the lightly doped region of the semiconductor layer using the photoresist pattern as a mask, the semiconductor layer Forming a gate insulating film to cover the gate insulating film; forming a gate line overlapping a portion of the channel region and the lightly doped region adjacent to the channel region on the gate insulating film; and applying a conductive impurity to a predetermined region of the polysilicon pattern using the gate line as a mask High concentration doping to form source and drain regions Defining a width of the lightly doped region, forming a first interlayer insulating film to cover the semiconductor layer, a data line having a source electrode connected to the source region on the first interlayer insulating layer, and a drain electrode connected to the drain region Forming a second interlayer insulating film on the data line and the drain electrode; and forming a pixel electrode connected to the drain electrode on the second interlayer insulating film.

Or forming an amorphous silicon film on the insulating substrate, forming a low concentration doped region by ion implanting conductive impurity ions on the amorphous silicon film, crystallizing and patterning the amorphous silicon film to form a semiconductor layer, on the semiconductor layer Forming a photoresist pattern, defining a channel region by removing a portion of the lightly doped region of the semiconductor layer using the photoresist pattern as a mask, forming a gate insulating film to cover the semiconductor layer, and forming a channel region and a channel region on the gate insulating film; Forming a gate metal and a data metal piece that are partially overlapped with the adjacent low concentration doping region and a predetermined distance from the gate line, and doping a predetermined region of the semiconductor layer with a high concentration of conductive impurities using a gate line as a mask to form a source region and a drain region And defining a width of the lightly doped region. Forming an interlayer insulating film to cover the semiconductor layer; forming a data connection part connected to the source region and the data metal piece and a pixel electrode connected to the drain region on the interlayer insulating film.

Here, in the step of defining the channel region, the semiconductor layer is preferably removed by the depth of the lightly doped region.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, area, plate, etc. is over another part, this includes not only the part directly above the other part but also another part in the middle. On the contrary, when a part is just above another part, it means that there is no other part in the middle.

Hereinafter, a thin film transistor array panel and a method of manufacturing the same according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

[First Embodiment]

1 is a layout view of a thin film transistor array panel for explaining an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line II-II ′ of FIG. 1.                     

As illustrated, a blocking film 111 made of silicon oxide or the like is formed on the transparent insulating substrate 110. The semiconductor layer 150 is formed on the blocking layer 111 and includes a source region 153, a drain region 155, and a channel region 154 that is not doped with impurities. A lightly doped drain 152 is formed between the source region 153 and the channel region 154 and the drain region 155 and the channel region 154 of the semiconductor layer.

The lightly doped region 152 prevents leakage current or punch through. In the source region 153 and the drain region 155, conductive impurities are heavily doped, and in the lightly doped region 152, the conductive impurities are less doped than the source region 153 and the drain region 155. .

In this case, the thickness of the channel region 154 is lower than that of the source region 153 and the drain region 155, and is as thin as the thickness of the lightly doped region 152. That is, there is a step between the channel region 154, the source region 153, and the drain region 155 by the height of the lightly doped region 152.

The conductive impurities may be P-type or N-type semiconductor impurities, boron (B), gallium (Ga), etc. may be used as the P-type impurities, and phosphorus (P), arsenic (As), etc. may be used as the N-type impurities. have.

A gate insulating layer 140 made of silicon nitride, silicon oxide, or the like is formed on the semiconductor layer 150. The gate line 121 is formed to extend in one direction on the gate insulating layer 140, and a portion of the gate line 121 extends to form the channel region 154 and the lightly doped region 152 of the semiconductor layer 150. Nested. The portion overlapping the channel region 154 is used as the gate electrode 124 of the thin film transistor.

In addition, the storage electrode line 131 for increasing the storage capacitance of the pixel is parallel to the gate line 121 and is formed in the same layer with the same material. A portion of the storage electrode line 131 overlapping the semiconductor layer 150 becomes the storage electrode 133, and the semiconductor layer 150 overlapping the storage electrode 133 becomes the storage electrode region 157. One end of the gate line 121 may be formed wider than the width of the gate line 121 in order to connect to an external circuit (not shown).

The first interlayer insulating layer 601 is formed on the gate insulating layer 140 including the gate line 121 and the storage electrode line 131. The first interlayer insulating layer 601 includes first and second contact holes 161 and 162 exposing the source region 153 and the drain region 155, respectively.

A data line 171 is formed on the first interlayer insulating layer 601 to cross the gate line 121 to define a pixel area. A portion or branched portion of the data line 171 is connected to the source region 153 through the first contact hole 161, and the portion 173 connected to the source region 153 is a source electrode (eg, a thin film transistor). 173). One end of the data line 171 may be formed wider than the width of the data line 171 to connect to an external circuit.

A drain electrode 175 is formed on the same layer as the data line 171 and is separated from the source electrode 173 and connected to the drain region 155 through the second contact hole 162.                     

A second interlayer insulating layer 602 is formed on the first interlayer insulating layer 601 including the drain electrode 175 and the data line 171. The second interlayer insulating layer 602 has a third contact hole 163 exposing the drain electrode 175.

The pixel electrode 190 connected to the drain electrode 175 is formed on the second interlayer insulating layer 602 through the third contact hole 163. An alignment layer 11 is formed on the pixel electrode 190.

A method of manufacturing the thin film transistor array panel according to the first embodiment of the present invention described above will be described in detail with reference to FIGS. 1 and 2 described above with reference to FIGS. 3A to 6B.

3A is a layout view at an intermediate stage of manufacturing a thin film transistor array panel according to a first exemplary embodiment of the present invention, and FIG. 3B is a cross-sectional view taken along line IIIb-IIIb 'of FIG. 3A, and at a next step of FIG. 4B. 5A is a layout view of the next step of FIG. 4, FIG. 5B is a cross-sectional view taken along the line Vb-Vb ′ of FIG. 5A, FIG. 6A is a layout view of the next step of FIG. 5A, and FIG. 6A is a cross-sectional view taken along the line VIb-VIb 'of FIG. 6A, FIG. 7A is a layout view at the next stage of FIG. 6A, and FIG. 7B is a cross-sectional view taken along the line VIIb-VIIb ′ of FIG. 7A.

First, as illustrated in FIGS. 3A and 3B, the blocking film 111 is formed by depositing silicon oxide (SiO ₂ ) or silicon nitride (SiNx) on the transparent insulating substrate 110. Subsequently, impurities such as a natural oxide film on the blocking film 111 are removed by ozone (O3) cleaning.

Next, an amorphous silicon film which is not doped with impurities is formed to a thickness of 400 to 1,200 kPa by a method such as chemical vapor deposition. A low concentration doped region 152 is formed by doping lightly with conductive impurity ions on the amorphous silicon film. For example, it is injected into the energy of 10eKV to form a thickness of 250 ~ 300Å.

Then, the amorphous silicon film is crystallized by laser annealing, furnace annealing, or sequential lateral solidification (SLS), and then patterned by photolithography using a photomask to form a semiconductor layer made of polycrystalline silicon. 150 is formed. At this time, since the ions of the lightly doped region 152 are activated, a separate activation process is not necessary.

Next, as shown in FIG. 4, a photoresist film is deposited on the semiconductor layer 150, and then exposed and developed through a photomask to form a photoresist pattern PR that exposes a predetermined region of the semiconductor layer 150. The exposed predetermined region becomes a channel region 154 (see FIG. 2) of the semiconductor layer 150.

Subsequently, the lightly doped region 152 is removed from a portion of the semiconductor layer 150 exposing the photoresist pattern as a mask to define the channel region 154.

5A and 5B, after removing the photoresist pattern PR, an insulating material such as silicon nitride or silicon oxide is deposited on the semiconductor layer 150 by chemical vapor deposition to form the gate insulating layer 140. Form. Thereafter, silver (Ag), copper (Cu), titanium (Ti), aluminum (Al), tungsten (W), or an alloy thereof is deposited on the gate insulating layer 140 to form a metal film.                     

After the photoresist is coated on the metal layer, the photoresist pattern PR is formed by a photo process using a photomask. Then, the metal film is wet or dry etched using the photoresist pattern as a mask to form the gate line 121 and the storage electrode line 131. The gate line 121 overlapping the semiconductor layer 150 is formed to overlap not only the channel region 154 but also a portion of the lightly doped region 152.

If the storage capacitor is sufficient, the storage electrode line 131 and the storage electrode 133 are not formed. Side surfaces of the gate line 121 and the storage electrode line 131 are formed to be tapered to increase adhesion to the upper layer.

Afterwards, the semiconductor layer is doped with P-type conductive impurities, for example, boron and gallium, by using the photoresist pattern PR or the gate line 121 and the storage electrode line 131 at high concentrations. And define the width of the lightly doped region. In this case, the lightly doped region 152 is positioned below the gate line 121 and is left only between the source region 153 and the channel region 154 and between the drain region 155 and the channel region 154.

In addition, the semiconductor layer 150A may be exposed to the outside of the storage electrode lines 131 and 133 because of the difference in length and width of the semiconductor layer 150 and the storage electrode lines 131 and 133. These regions are also doped, adjacent to the sustain electrode region 157 and separated from the drain region 155.

Since the lightly doped region 152 is also defined when patterning the gate electrode, a separate mask is not required to form the lightly doped region 152, thereby simplifying the process.                     

When the gate line 121 is formed of a high heat resistant and high chemical material such as titanium, the gate line 121 may be doped with impurities after removing the photoresist pattern PR.

6A and 6B, a first interlayer insulating layer 601 is formed on the entire surface of the substrate 110 and etched by a photolithography process to expose the source and drain regions 153 and 155. The contact holes 161 and 162 are formed.

The interlayer insulating layer 160 has excellent planarization characteristics, and is formed of a-Si: C: O, a-Si: O: organic material having photosensitivity, and plasma enhanced chemical vapor deposition (PECVD). Low dielectric constant insulating materials, such as F, or an inorganic material, such as silicon nitride can be formed.

Next, tungsten, titanium, aluminum, or an alloy thereof is deposited on the first interlayer insulating film 601 in a single layer or a plurality of layers to form a metal film. Subsequently, the metal layer is patterned by a photolithography process, and the data line 171 and the drain electrode 175 having the source electrode 173 connected to the source region 153 and the drain region 155 through the contact holes 161 and 162, respectively. ).

Sidewalls of the data line 171 and the drain electrode 175 may be formed to be tapered to improve adhesion to the upper layer.

As shown in FIGS. 7A and 7B, a second interlayer insulating film 602 covering the data line 171 and the drain electrode 175 is formed. Thereafter, the second interlayer insulating layer 602 is patterned by a photolithography process to form a third contact hole 163 exposing the drain electrode 175. The second interlayer insulating film 601 may also be formed of the same material as the first interlayer insulating film 160.                     

1 and 2, a transparent conductive film such as indium zinc oxide (IZO), indium tin oxide (ITO), or the like is formed on the second interlayer insulating film, and then patterned and drained through the third contact hole 163. The pixel electrode 190 connected to the electrode 175 is formed.

When the second interlayer insulating layer 602 is formed of an organic material having a low dielectric constant, the pixel electrode 190 may overlap the data line and the gate line to improve the aperture ratio of the pixel region.

 Second Embodiment

FIG. 8 is a layout view of a thin film transistor array panel for a liquid crystal display according to a second exemplary embodiment of the present invention, and FIG. 9 is a cross-sectional view taken along line IX-IX′-IX of FIG. 8.

In Embodiment 2, the data connection part 171b and the pixel electrode 190 are formed on the same layer using the same material, and the pixel electrode 190 and the data connection part 171b are formed on the source and drain regions 153 and 155 of the semiconductor layer 150. ), Since the contact holes 161 and 162 for connecting to the plurality of holes are formed at the same time, the number of masks can be reduced as compared with the first embodiment.

More specifically, as shown in FIGS. 8 and 9, the blocking layer 111 is formed on the transparent insulating substrate 110. The semiconductor layer 150 includes a source region 153, a drain region 155, and a channel region 154 formed of an intrinsic semiconductor, between which the conductive impurities are heavily doped, on the blocking layer. Is formed. Further, conductive impurities are doped at a lower concentration than the source and drain regions between the source region 153 and the channel region 154 and the drain region 155 and the channel region 154 of the semiconductor layer 150.

At this time, the thickness of the semiconductor layer of the channel region 154 has a thickness lower than that of the source region 153 and the drain region 155, and is as thin as the thickness of the lightly doped region 152. That is, there is a step between the channel region 154, the source region 153, and the drain region 155 by the height of the lightly doped region 152.

The gate insulating layer 140 is formed on the substrate 110 including the semiconductor layer 150. A gate line 121 extending in the horizontal direction is formed on the gate insulating layer 140, and a portion of the gate line 121 extends in the vertical direction to partially overlap the semiconductor layer 150, and overlaps the semiconductor layer 150. A portion of the gate line 121 is used as the gate electrode 124.

One end of the gate line 121 may be formed larger than the width of the gate line 121 to receive a scan signal from an external circuit (not shown).

In addition, the storage electrode line 131 is formed in the same layer with the same material as the gate line 121 so that the storage electrode line 131 is formed to be parallel to the gate line 121 and is positioned in parallel. A portion of the storage electrode line 131 overlapping the semiconductor layer 150 becomes the storage electrode 133, and the semiconductor layer 150 disposed under the storage electrode 133 becomes the storage electrode region 157.

The data metal piece 171a is formed at a distance from the gate line 121 and extends in a direction perpendicular to the gate line 121, and is formed on the same layer as the gate line 121. The data metal piece 171a is formed not to be connected to the gate line 121 between two adjacent gate lines 121. In addition, the data metal piece 171a may enlarge and form one end portion of the one row of data metal pieces 171a located at the outermost side in order to receive an image signal from an external circuit (not shown).

An interlayer insulating layer 160 is formed on the gate insulating layer 140 including the gate line 121 and the storage electrode line 131.

The data connection part 171b, the pixel electrode 190, and the contact auxiliary member 82 are formed on the interlayer insulating layer 160. The data connection part 171b is formed to cross the gate line 121 and the storage electrode line 131 in the vertical direction.

The data metal piece 171a is connected to the data connecting portion 171b through the third contact hole 163 formed in the interlayer insulating layer 160, and the data connecting portion 171b is connected to the source through the first contact hole 161. It is connected to the area 153. That is, the data metal pieces 171a separated by the data connection part 171b are connected across the gate line 121 and the storage electrode line 131. The pixel electrode 190 is connected to the drain region 155 through a second contact hole 162 formed over the interlayer insulating layer 160 and the gate insulating layer 140, and the contact auxiliary member 82 is interlayered. The fourth contact hole 164 formed in the insulating layer 160 is connected to one end of the gate line 121 and the data metal piece 171a, respectively.

The contact auxiliary member 82 is not essential to serve to protect adhesion between the end of the data line 171a and the external device and to protect them, and application thereof is optional. In particular, when the driving circuit is formed together with the thin film transistor in the display area, it is not formed.

An alignment layer 11 is formed on the pixel electrode 190.                     

A method of manufacturing the thin film transistor array panel according to the second embodiment of the present invention described above will be described in detail with reference to FIGS. 8 and 9 previously described with reference to FIGS. 10A to 13B.

FIG. 10A is a layout view at an intermediate stage of manufacturing a thin film transistor array panel according to a second exemplary embodiment of the present invention, and FIG. 10B is a cross-sectional view taken along the line Xb-Xb'-Xb 'of FIG. 10A, and FIG. 11 is FIG. 10B. 12A is a layout view at the next step in FIG. 11, FIG. 12B is a cross-sectional view taken along the line XIIb-XIIb′-XIIb ″ in FIG. 12A, and FIG. 13A is at a next step in FIG. 12A. 13B is a cross-sectional view taken along the line XIIIb-XIIIb'-XIIIb "of FIG. 13A.

First, as shown in FIGS. 10A and 10B, the blocking layer 111 is formed by depositing silicon oxide (SiO ₂ ) or silicon nitride (SiNx) on the transparent insulating substrate 110. Subsequently, impurities such as a natural oxide film on the blocking film 111 are removed by ozone (O3) cleaning.

Next, an amorphous silicon film which is not doped with impurities is formed to a thickness of 400 to 1,200 kPa by a method such as chemical vapor deposition. A low concentration doped region 152 is formed by doping the amorphous silicon film with low concentration of conductive impurity ions.

Then, the amorphous silicon film is crystallized by laser heat treatment, furnace heat treatment or lateral solid phase crystallization, and then patterned by a photolithography process using a photomask to form the semiconductor layer 150. At this time, since the ions of the lightly doped region 152 are activated, a separate activation process is not necessary.                     

Next, as shown in FIG. 11, a photoresist film is deposited on the semiconductor layer 150, and then exposed and developed through a photomask to form a photoresist pattern PR that exposes a predetermined region of the semiconductor layer 150. The exposed predetermined region becomes the channel region 154 of the semiconductor layer 150 later.

Thereafter, the lightly doped region 152 formed on the semiconductor layer exposed to the photoresist pattern PR is removed to define the channel region 154.

12A and 12B, after removing the photoresist pattern PR, an insulating material such as silicon nitride or silicon oxide is deposited on the semiconductor layer 150 by chemical vapor deposition to form the gate insulating layer 140. Form. Thereafter, copper (Cu), silver (Ag), titanium (Ti), aluminum (Al), tungsten (W), or an alloy thereof is deposited on the gate insulating layer 140 to form a metal film.

Thereafter, the photoresist is coated on the metal layer, and then the photoresist pattern PR is formed by a photo process using a photomask. In this case, the metal film is patterned using the photoresist pattern PR to form the gate line 121, the storage electrode line 131, and the data metal piece 171a. When the storage capacitor is sufficient, the storage electrode line 131 and the storage electrode 133 are not formed. In this case, the width of the gate line 121 overlapping the channel region of the semiconductor layer 150 is formed to be wider than that of the channel region and partially overlaps the lightly doped region 152, and defines the width of the lightly doped region. That is, the lightly doped region 152 is left only between the source region 153 and the channel region 154, and only between the drain region 155 and the channel region 154.

Afterwards, the semiconductor layer 150 is formed by doping the semiconductor layer 150 using a photoresist pattern PR with a high concentration of conductive impurities to form the source region 153 and the drain region 155. When the gate line 121 is formed of a metal having excellent chemical resistance, the conductive impurities may be heavily doped using the gate line 121 as a mask.

In addition, the semiconductor layer 150A may be exposed to the outside of the storage electrode lines 131 and 133 because of the difference in length and width of the semiconductor layer 150 and the storage electrode lines 131 and 133. These regions are also doped, adjacent to the sustain electrode region 157 and separated from the drain region 155.

As shown in FIGS. 13A and 13B, the interlayer insulating layer 160 is formed of an insulating material on the entire surface of the substrate on which the source region 153, the drain region 155, and the channel region 154 are formed. The interlayer insulating layer 160 is an organic material having excellent planarization characteristics and a photosensitive property, a low dielectric constant insulating material such as a-Si: C: O, a-Si: O: F, or inorganic material formed by plasma chemical vapor deposition. It may be formed of silicon nitride or the like.

Thereafter, the first contact hole 161 exposing the source region 153, the second contact hole 162 exposing the drain region 155, and the data metal piece 171a are exposed on the interlayer insulating layer 160. The third contact hole 163 and the fourth contact hole 164 exposing one end of the data metal piece 171a are formed.

When the interlayer insulating film is formed of an organic material having photosensitivity, the contact hole may be formed only by a photographic process.

8 and 9, a conductive layer is formed of a transparent conductive material on the interlayer insulating layer 160 including the first to fourth contact holes 161 to 164, and then patterned to form a data connection part 171b. And the pixel electrode 190 and the contact assistant member 82.

The data metal piece 171a is connected to the data connector 171b through the third contact hole 163, and the data connector 171b is connected to the source region 153 through the first contact hole 161. The pixel electrode 190 is connected to the drain region 155 through the second contact hole 162, and the contact auxiliary member 82 is connected to the data metal piece 171a through the fourth contact hole 164. .

In this case, when the interlayer insulating layer 160 is formed of an organic material having a low dielectric constant, the pixel electrode 190 may overlap the gate line and the data metal piece to improve the aperture ratio of the pixel region.

As described above, when the dopant is doped into the amorphous silicon film and the polycrystallization process is performed, the impurity can be activated without going through a separate ion activation process, thereby simplifying the process. In addition, when the gate electrode is formed, it can be easily overlapped with the low concentration doped region, so that the low concentration doped region can be formed more accurately and easily than the conventional method using a metal film or a spacer.

Although the present invention has been described with reference to one embodiment shown in the accompanying drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Could be. Accordingly, the true scope of protection of the invention should be defined only by the appended claims.

As in the present invention described above, by performing the polycrystallization process and the ion activation process together, the formation of the low concentration doped region can be facilitated.

In addition, since a separate mask is not required to define the lightly doped region, the process can be simplified, thereby reducing manufacturing costs and improving productivity.

Claims (6)

delete delete delete Forming an amorphous silicon film on the insulating substrate, Forming a lightly doped region by ion implanting conductive impurity ions on the amorphous silicon film; Crystallizing and patterning the amorphous silicon film to form a semiconductor layer, Forming a photoresist pattern on the semiconductor layer; Defining a channel region by removing the lightly doped region of the semiconductor layer using the photoresist pattern as a mask; Forming a gate insulating film to cover the semiconductor layer; Forming a gate line on the gate insulating layer, the gate line overlapping the channel region and the lightly doped region adjacent to the channel region; Doping the polycrystalline silicon pattern with a high concentration of conductive impurities in the polycrystalline silicon pattern using the gate line as a mask to form a source region and a drain region, and defining a width of the low concentration doped region; Forming a first interlayer insulating film to cover the semiconductor layer, Forming a data line having a source electrode connected to the source region and a drain electrode connected to the drain region on the first interlayer insulating layer; Forming a second interlayer insulating film on the data line and the drain electrode; And forming a pixel electrode connected to the drain electrode on the second interlayer insulating layer. Forming an amorphous silicon film on the insulating substrate, Forming a lightly doped region by ion implanting conductive impurity ions on the amorphous silicon film; Crystallizing and patterning the amorphous silicon film to form a semiconductor layer, Forming a photoresist pattern on the semiconductor layer; Defining a channel region by removing the lightly doped region of the semiconductor layer using the photoresist pattern as a mask; Forming a gate insulating film to cover the semiconductor layer; Forming a gate line overlapping the channel region and the lightly doped region adjacent to the channel region and a data metal piece spaced a predetermined distance from the gate line on the gate insulating layer; Doping the semiconductor layer with a high concentration of conductive impurities in the semiconductor layer using the gate line as a mask to form a source region and a drain region, and defining a width of the low concentration doped region; Forming an interlayer insulating film to cover the semiconductor layer; Forming a data connection part connected to the source region and the data metal piece and a pixel electrode connected to the drain area on the interlayer insulating layer. The method of claim 4 or 5, And removing the semiconductor layer by a depth of the lightly doped region in the defining of the channel region.

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