KR20060007209A - Thin film transistor array panel and manufacturing method thereof - Google Patents

Abstract

The thin film transistor array panel according to the present invention is a semiconductor having a source region and a drain region formed on an insulating substrate, an insulating substrate and doped with a high concentration of conductive impurities, and having a channel region without impurities being doped. A gate line formed on the layer, the semiconductor layer, and a gate line formed on the gate insulating layer and having a gate electrode overlapping the channel region, and first and second contact holes formed on the gate line and exposing a source region and a drain region, respectively. A data line having a source electrode formed on the first interlayer insulating film having a first interlayer insulating film and connected to the source region through the first contact hole, and a drain electrode formed on the interlayer insulating film and connected to the drain region through the second contact hole. Formed over the data line and the drain electrode, The shipment includes a second interlayer insulating film having a third contact hole, a pixel electrode formed on the second interlayer insulating film and connected to the drain electrode, and some of the silicon atoms of the semiconductor layer are bonded with nitrogen ions.

Thin Film Transistor, Threshold Voltage

Description

Thin film transistor array panel and manufacturing method thereof

1 is a layout view of a thin film transistor array panel according to a first exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view of the thin film transistor array panel of FIG. 1 taken along the line II-II ',

3A is a layout view at an intermediate stage of manufacturing a thin film transistor array panel according to an exemplary embodiment of the present invention;

3B is a cross-sectional view taken along the line IIIb-IIIb ′ of FIG. 3A;

4A is a layout view in the next step of FIG. 3A,

4B is a cross-sectional view taken along the line IVb-IVb ′ of FIG. 4A;

5 is a cross-sectional view at the next step of FIG. 4B,

FIG. 6A is a layout view at the next step of FIG. 5A, and FIG.

FIG. 6B is a cross-sectional view taken along the line VIb-VIb ′ of FIG. 6A;

FIG. 7A is a layout view at the next step of FIG. 6A,

FIG. 7B is a cross-sectional view taken along the line VIIb-VIIb ′ of FIG. 7A;

8 is a layout view of a thin film transistor array panel for a liquid crystal display according to a second exemplary embodiment of the present invention.

9 is a cross-sectional view taken along the line IX-IX'-X "of FIG. 8,                 

10A is a layout view at an intermediate stage of manufacturing a thin film transistor array panel according to a second exemplary embodiment of the present invention.

FIG. 10B is a cross-sectional view taken along the line Xb-Xb'-Xb "of FIG. 10A,

FIG. 11A is a layout view at the next step of FIG. 10A, and FIG.

FIG. 11B is a cross-sectional view taken along the line XIb-XIb′-XIb ″ of FIG. 11A;

12A is a layout view at the next step of FIG. 11A,

12B is a cross-sectional view taken along the line XIIb-XIIb′-XIIb ″ of FIG. 11A, and FIG.

FIG. 13A is a layout view at the next step of FIG. 12A, and FIG.

FIG. 13B is a cross-sectional view taken along the line XIIIb-XIIIb'-XIIIb ″ of FIG. 13A.

※ Explanation of symbols on main parts of drawing ※

110: insulated substrate 121: gate line

124: gate electrode 131: sustain electrode line

133 sustain electrode 140 gate insulating film

150: semiconductor layer 153: source region

154: channel region 155: drain region

171: data line 173: source electrode

175: drain electrode 190: pixel electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor array panel and a manufacturing method thereof, and more particularly, to a thin film transistor array panel using polycrystalline silicon as a semiconductor layer and a method of manufacturing the same.

A thin film transistor (TFT) is used as a circuit board for independently driving each pixel in a liquid crystal display device, an organic electroluminescence (EL) display device, or the like. The thin film transistor array panel includes a scan signal line or a gate line for transmitting a scan signal and an image signal line or a data line for transferring an image signal, and includes a thin film transistor connected to the gate line and the data line, a pixel electrode connected to the thin film transistor, and the like. It is included.

The thin film transistor includes a semiconductor layer forming a channel and a gate electrode connected to the gate line, a source electrode connected to the data line and a drain electrode facing the source electrode with respect to the semiconductor layer.

The thin film transistor is a switching element that controls an image signal transmitted to a pixel electrode through a data line according to a scan signal transmitted through a gate line.

In this case, the semiconductor layer may be made of amorphous silicon or polycrystalline silicon, and the thin film transistor using the polycrystalline silicon as the semiconductor layer may drive the pixel when the thin film transistor is formed in the pixel region because the driving speed is much faster than that of the amorphous silicon thin film transistor. There is an advantage that can form a driving circuit together.

The semiconductor layer of the polycrystalline silicon thin film transistor is formed by forming an amorphous silicon film and crystallizing by various heat treatment methods. However, such heat treatment causes a large number of bonds, such as RTA (rapid heat treatment), furnace heat treatment, and the like, which causes a large number of defects between grains, and SLS and ELA, etc., form protrusions on the thin film surface. These defects and protrusions have a problem of increasing the threshold voltage of the thin film transistor.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a thin film transistor array panel and a method of manufacturing the same.

A thin film transistor array panel according to the present invention for achieving the above object is formed between an insulating substrate, a source region and a drain region, a source region and a drain region doped with a high concentration of conductive impurities, and the impurities are formed The doped channel region has a semiconductor layer, a gate insulating film formed on the semiconductor layer, a gate line formed on the gate insulating film and having a gate electrode overlapping the channel region, and formed on the gate line, respectively, to expose the source region and the drain region. A first interlayer insulating film having first and second contact holes, a data line having a source electrode formed on the first interlayer insulating film and connected to the source region through the first contact hole, formed on the interlayer insulating film and having a second contact hole On the drain electrode, the data line and the drain electrode connected to the drain region A second interlayer insulating film formed on the second interlayer insulating film, the second interlayer insulating film having a third contact hole to expose the drain electrode, and a pixel electrode formed on the second interlayer insulating film, the pixel electrode being connected to the drain electrode, wherein some of the silicon atoms of the semiconductor layer are combined with nitrogen ions; Doing.                     

Or on a semiconductor layer and a semiconductor layer having a source region and a drain region formed on an insulating substrate, an insulating substrate and doped with a high concentration of conductive impurities, and having a channel region which is not doped with impurities and is located between the source region and the drain region. A gate insulating film, a gate line formed on the gate insulating film, and having a gate electrode overlapping the channel region, a data metal piece, a gate line, and a data metal piece, which are positioned at a predetermined distance apart from each other and extend in a direction perpendicular to the gate line. An interlayer insulating film formed on the interlayer insulating film formed on the interlayer insulating film and intersecting the gate line to electrically connect the data metal piece through the contact hole; and a pixel electrode formed on the interlayer insulating film and connected to the drain region through the contact hole. , Peninsula Some of the silicon atoms of the layers are combined with the nitrogen ion.

The semiconductor device may further include a blocking film formed on the entire surface of the substrate and formed under the semiconductor layer.

The semiconductor device may further include a low concentration doped region formed between the drain region and the channel region between the source region and the channel region and doped with a low concentration of the second conductivity type impurities.

In addition, it is preferable that nitrogen ion of a semiconductor layer is contained in the ratio of 1/100-1 / 1,000 of a silicon atom volume.

According to another aspect of the present invention, a method of manufacturing a thin film transistor array panel includes forming an amorphous silicon film using a mixed gas containing nitrogen gas on an insulating substrate, and crystallizing and patterning the amorphous silicon film to form a polysilicon layer. Forming a gate insulating film on the polycrystalline silicon layer, forming a gate line overlapping a portion of the polycrystalline silicon layer on the gate insulating film, and doping a high concentration of conductive impurities in a predetermined region of the polycrystalline silicon layer using the gate line as a mask Forming a semiconductor layer having a source region, a channel region, and a drain region, forming a first interlayer insulating layer to cover the semiconductor layer, a data line and a drain having a source electrode connected to the source region on the first interlayer insulating layer Forming a drain electrode connected to the region, the data line and the drain Forming a second interlayer insulating film on the electrode, and forming a pixel electrode connected to the drain electrode on the second interlayer insulating film.

Or forming an amorphous silicon film using a mixed gas containing nitrogen gas on the insulating substrate, crystallizing and patterning the amorphous silicon film to form a polycrystalline silicon layer, forming a gate insulating film on the polycrystalline silicon layer, a gate insulating film Forming a gate line and a data metal piece in which a portion of the polycrystalline silicon layer overlaps with each other, and a semiconductor having a source region, a channel region, and a drain region by doping a predetermined amount of conductive impurities in a predetermined region of the polysilicon layer with the gate line as a mask Forming a layer, forming an interlayer insulating film to cover the semiconductor layer, and forming a data line having a source electrode connected to the source region and a pixel electrode connected to the drain region on the interlayer insulating layer.

The method may further include forming a blocking film on the insulating substrate.

The mixed gas may further include H ₂ or He ₂ gas and SiH ₄ gas.

In addition, nitrogen gas is preferable to use any one of _{N 2 O, N 2, NF} 3.

In addition, the nitrogen gas is preferably formed by injecting at a ratio of 1/100 to 1/1000 Sccm of the SiH ₄ gas.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, area, plate, etc. is over another part, this includes not only the part directly above the other part but also another part in the middle. On the contrary, when a part is just above another part, it means that there is no other part in the middle.

Hereinafter, a thin film transistor array panel and a method of manufacturing the same according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

[First Embodiment]

FIG. 1 is a layout view of a display area of a thin film transistor array panel for explaining an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line II-II ′ of the thin film transistor array panel of FIG. 1.                     

As shown in the drawing, a blocking layer 111 is formed on the transparent insulating substrate 110 in the thin film transistor array panel according to the exemplary embodiment of the present invention.

The semiconductor layer 150 including the source region 153, the drain region 155, and the channel region 154 disposed therebetween is formed on the blocking layer 111. A lightly doped drain 152 is formed between the source region 153 and the channel region 154 and between the drain region 155 and the channel region 154. At this time, the semiconductor layer 150 contains nitrogen ions at a ratio of 1/100 to 1/1000 of the volume of silicon atoms.

The lightly doped region 152 prevents leakage current or punch through. The source region 153 and the drain region 155 are heavily doped with N-type or P-type conductive ions, and the low-concentration doped region 152 has a low concentration of the same conductivity type ions as the source and drain regions 153 and 155. Doped with. In addition, the channel region 154 is an intrinsic semiconductor region containing no conductive impurity ions.

A gate insulating layer 140 made of silicon oxide or the like is formed on the semiconductor layer 150. In addition, a gate line 121 extending in one direction is formed on the gate insulating layer 140, and a portion of the gate line 121 extends to overlap the channel region 154 of the semiconductor layer 150. The portion overlapping the channel region 154 may be used as the gate electrode 124 of the thin film transistor, and may also overlap the lightly doped region 152.

In addition, the storage electrode line 131 for increasing the storage capacitance of the pixel is parallel to the gate line 121 and is formed in the same layer with the same material. A portion of the storage electrode line 131 overlapping the semiconductor layer 150 becomes the storage electrode 133, and the semiconductor layer 150 overlapping the storage electrode 133 becomes the storage electrode region 157.

One end of the gate line 121 preferably has a width wider than the width of the gate line 121 in order to connect with an external gate driving circuit, and in the case where the gate driving circuit is directly provided on the substrate 110. An end portion of the gate line 121 is electrically connected to an output terminal of the gate driving circuit.

The first interlayer insulating layer 601 is formed on the gate insulating layer 140 on which the gate line 121 and the storage electrode line 131 are formed. The first interlayer insulating layer 601 includes first and second contact holes 161 and 162 exposing the source region 153 and the drain region 155, respectively.

A data line 171 is formed on the first interlayer insulating layer 601 to cross the gate line 121 to define a pixel area. A portion or branched portion of the data line 171 is connected to the source region 153 through the first contact hole 161, and the portion 173 connected to the source region 153 is a source electrode (eg, a thin film transistor). 173).

One end of the data line 171 preferably has a width wider than the width of the data line 171 in order to connect with an external data driving circuit, and when the data driving circuit is directly provided on the substrate 110. An end portion of the data line 171 is electrically connected to an output terminal of the data driving circuit.

A drain electrode 175 is formed on the same layer as the data line 171 and is separated from the source electrode 173 and connected to the drain region 155 through the second contact hole 162.

A second interlayer insulating layer 602 is formed on the first interlayer insulating layer 601 including the drain electrode 175 and the data line 171. The second interlayer insulating layer 602 has a third contact hole 163 exposing the drain electrode 175.

The pixel electrode 190 connected to the drain electrode 175 is formed on the second interlayer insulating layer 602 through the third contact hole 163.

A method of manufacturing a thin film transistor array panel according to an exemplary embodiment of the present invention described above will be described in detail with reference to FIGS. 1 and 2 described above with reference to FIGS. 3A through 6B.

FIG. 3A is a layout view in an intermediate step of manufacturing a thin film transistor array panel according to an exemplary embodiment of the present invention, FIG. 3B is a cross-sectional view taken along line IIIb-IIIb 'of FIG. 3A, and FIG. 4A is a next step in FIG. 3A. 4B is a cross-sectional view taken along the line IVb-IVb 'of FIG. 4A, FIG. 5 is a cross-sectional view at the next step of FIG. 4B, FIG. 6A is a layout view at the next step of FIG. 5A, and FIG. 6B is a view 6A is a cross-sectional view taken along the line VIb-VIb 'of FIG. 6A, FIG. 7A is a layout view of the next step of FIG. 6A, and FIG. 7B is a cross-sectional view taken along the line VIIb-VIIb ′ of FIG. 7A.

First, as illustrated in FIGS. 3A and 3B, the blocking film 111 is formed by depositing silicon oxide (SiO ₂ ) or silicon nitride (SiNx) in a single layer or a plurality of layers on the transparent insulating substrate 110.

Then, an amorphous silicon film is formed on the blocking film 111 by chemical vapor deposition (CVD), sputtering, or the like. Here, the amorphous silicon film is formed by reacting SiH ₄ gas with hydrogen or helium gas, wherein a small amount of nitrogen gas such as N ₂ , N ₂ O, NF _3, or the like is injected. It is preferable to inject at a ratio of 1/100 to 1/1000 Sccm of the SiH ₄ gas.

In this case, the injected nitrogen gas is charged with nitrogen ions (N−) to exist inside or on the surface of the amorphous silicon film and incorporate at a ratio of 1/100 to 1 / 1,000 of silicon atoms. E.g. When the number of silicon atoms is 10E23, the nitrogen ion contains 10E19.

Thereafter, the amorphous silicon film is crystallized by laser annealing, furnace annealing, or sequential side crystallization (SLS), and then patterned by photolithography to form a polycrystalline silicon layer 150A. At this time, nitrogen ions contained in the amorphous silicon film are bonded to the bonding loss of the silicon.

Since silicon atoms bonded to nitrogen ions no longer bond with other carriers, they do not form defects or protrusions on the surface between the grains due to the bonding loss of silicon and bonding with other carriers during crystallization.

Then, an insulating material such as silicon nitride or silicon oxide is deposited on the polycrystalline silicon layer 150A by the chemical vapor deposition method to form the gate insulating layer 140.

As shown in FIGS. 4A and 4B, a metal film is formed by depositing titanium (Ti), aluminum (Al), tungsten (W), or an alloy thereof in a single layer or a plurality of layers on the gate insulating layer 140.                     

Thereafter, the photoresist is coated on the metal layer, and then the photoresist pattern PR is formed by a photo process using a photomask. In this case, the metal film is patterned using the photoresist pattern as a mask to form the gate line 121 and the storage electrode line 131. When the storage capacitor is sufficient, the storage electrode line 131 and the storage electrode 133 are not formed. Here, the metal film is over-etched to form a width of the gate line 121 and the storage electrode line 131 smaller than that of the photosensitive film pattern PR.

Side surfaces of the gate line 121 and the storage electrode line 131 are formed to be tapered to increase adhesion to the upper layer.

Afterwards, the source and drain regions 153 and 155 are formed by doping N-type or P-type impurity ions to the polycrystalline silicon layer 150A at high concentration using the photoresist pattern PR as a mask. It is preferable to use P and As for N type impurity ions, and to use B and Ga as P type impurity ions.

Next, as shown in FIG. 5, after the photoresist pattern PR is removed, the N-type or P-type impurity ions are lightly doped into the polycrystalline silicon layer 150A using the gate line 121 and the storage electrode line 131 as a mask. The semiconductor layer 150 having the lightly doped region 152 is completed.

The polysilicon layer 150A positioned between the source region 153 and the drain region 155 becomes the channel region 154 that is not doped with impurities.

As described above, the lightly doped region 152 may be formed by using a metal film having different etching ratios in addition to the photoresist pattern, or by forming a spacer or the like on the sidewall of the gate line.

6A and 6B, a first interlayer insulating layer 601 is formed on the entire surface of the substrate 110 and etched by a photolithography process to expose the source and drain regions 153 and 155. The contact holes 161 and 162 are formed.

The interlayer insulating layer 160 has excellent planarization characteristics, and is formed of a-Si: C: O, a-Si: O: organic material having photosensitivity, and plasma enhanced chemical vapor deposition (PECVD). Low dielectric constant insulating materials, such as F, or an inorganic material, such as silicon nitride can be formed.

Next, tungsten, titanium, aluminum, or an alloy thereof is deposited on the first interlayer insulating film in a single layer or a plurality of layers to form a metal film. Subsequently, the metal film is patterned by a photolithography process to form a data line 171 and a drain electrode 175 having source electrodes 173 connected to the source and drain regions, respectively, through the contact holes 161 and 162.

Sidewalls of the data line 171 and the drain electrode 175 may be formed to be tapered to improve adhesion to the upper layer.

As shown in FIGS. 7A and 7B, a second interlayer insulating layer 602 covering the data line 171 and the drain electrode 175 is formed. Thereafter, the second interlayer insulating layer 602 is patterned by a photolithography process to form a third contact hole 163 exposing the drain electrode 175.

The second interlayer insulating film 602 may also be formed of the same material as the first interlayer insulating film 601.

1 and 2, a transparent conductive film such as indium zinc oxide (IZO), indium tin oxide (ITO), or the like is formed on the second interlayer insulating film, and then patterned and drained through the third contact hole 163. The pixel electrode 190 connected to the electrode 175 is formed.

When the second interlayer insulating layer 602 is formed of an organic material having a low dielectric constant, the pixel electrode 190 may overlap the data line and the gate line to improve the aperture ratio of the pixel region.

As described above, nitrogen ions are injected to exist on the surface or inside of the amorphous silicon film, and then nitrogen ions are bonded to the bond loss of the silicon atom when the amorphous silicon film is crystallized by heat treatment.

This reduces the probability that other carriers are trapped in the bonding loss of silicon so that defects or protrusions on the grains do not increase, thereby preventing the threshold voltage from increasing.

Second Embodiment

8 is a layout view of a thin film transistor array panel for a liquid crystal display according to a second exemplary embodiment of the present invention, and FIG. 9 is a cross-sectional view taken along line IX-IX′-IX ″ of FIG. 8.

In Embodiment 2, the data connection part 171b and the pixel electrode 190 are formed on the same layer using the same material, and the pixel electrode 190 and the data connection part 171b are formed on the source and drain regions 153 and 155 of the semiconductor layer 150. ), Since the contact holes 161 and 162 for connecting to the plurality of holes are simultaneously formed, the number of masks can be reduced as compared with the first embodiment.

More specifically, as shown in FIGS. 8 and 9, the blocking layer 111 is formed on the transparent insulating substrate 110, and the source region 153, the drain region 155, and the channel region 154 are formed on the transparent insulating substrate 110. ) And the lightly doped region 152 is formed. In addition, nitrogen ions are included in the semiconductor layer 150 at a ratio of 1/100 to 1 / 1,000 of the silicon atom volume.

The gate insulating layer 140 is formed on the substrate 110 including the semiconductor layer 150. Gate lines 121 and 124 long in the horizontal direction are formed on the gate insulating layer 140, and a portion of the gate lines 121 and 124 extend in the vertical direction to partially overlap the semiconductor layer 150. Portions of the gate lines 121 and 124 overlapping the 150 are used as the gate electrode 124.

One end 125 of the gate line 121 may be formed to be wider than the width of the gate lines 121 and 124 to receive a scan signal from an external circuit (not shown).

Further, the storage electrode lines 131 and 133 are formed in the same layer with the same material as the gate lines 121 and 124 so that the storage electrode lines 131 and 133 are formed to be parallel to the gate lines 121 and 124 and are positioned in parallel.

A portion of the storage electrode lines 131 and 133 overlapping the semiconductor layer 150 becomes the storage electrode 133, and the semiconductor layer 150 disposed under the storage electrode 133 becomes the storage electrode region 157.

In addition, the data metal piece 171a is formed on the same layer as the gate lines 121 and 124 and is formed to be separated from the gate lines 121 and 124 by a predetermined distance and extends in a direction perpendicular to the gate lines 121 and 124. .

The data metal piece 171a is formed not to be connected to the gate lines 121 and 124 between two adjacent gate lines 121 and 124. In addition, the data metal piece 171a can enlarge and form one end of the data metal piece 171a in the outermost row in order to receive an image signal from an external circuit (not shown).

An interlayer insulating layer 160 is formed on the gate insulating layer 140 including the gate lines 121 and 124 and the storage electrode lines 131 and 133.

The data connection part 171b, the pixel electrode 190, and the contact auxiliary member 82 are formed on the interlayer insulating layer 160. The data connection part 171b is formed to cross the gate lines 121 and 124 and the storage electrode lines 131 and 133 in the vertical direction.

The data metal piece 171a is connected to the data connecting portion 171b through the third contact hole 163 formed in the interlayer insulating layer 160, and the data connecting portion 171b is connected to the source through the first contact hole 161. It is connected to the area 153.

That is, the data metal pieces 171a separated by the data connection part 171b are connected across the gate lines 121 and 124 and the storage electrode lines 131 and 133. The pixel electrode 190 is connected to the drain region 155 through a second contact hole 162 formed over the interlayer insulating layer 160 and the gate insulating layer 140, and the contact auxiliary member 82 is interlayered. The fourth contact hole 164 formed in the insulating layer 160 is connected to one end of the gate lines 121 and 124 and the data metal piece 171a, respectively.

The contact auxiliary member 82 is connected to the end of the data line through the contact hole 162. The contact assistant 82 is not essential to serve to protect adhesion between the end portion of the data line 171 and an external device and to protect them, and application thereof is optional. In particular, the driving circuit is not formed when the thin film transistor of the display area is formed.

A method of manufacturing the thin film transistor array panel according to the second embodiment of the present invention described above will be described in detail with reference to FIGS. 8 and 9 previously described with reference to FIGS. 10A to 13B.

FIG. 10A is a layout view at an intermediate stage of manufacturing a thin film transistor array panel according to a second exemplary embodiment of the present invention, and FIG. 10B is a cross-sectional view taken along the line Xb-Xb'-Xb 'of FIG. 10A, and FIG. FIG. 11B is a cross-sectional view taken along the line XIb-XIb′-XIb ″ in FIG. 11A, FIG. 12A is a layout in the next step of FIG. 11A, and FIG. 12B is the XIIb-XIIb in FIG. 11A. 13A is a layout view of the next step of FIG. 12A, and FIG. 13B is a cross-sectional view taken along the line XIIIb-XIIIb'-XIIIb "of FIG. 13A.

As shown in FIGS. 10A and 10B, the blocking film 111 is formed by depositing silicon oxide (SiO ₂ ) or silicon nitride (SiNx) in a single layer or a plurality of layers on the transparent insulating substrate 110.

Then, an amorphous silicon film is formed on the blocking film 111 by chemical vapor deposition (CVD), sputtering, or the like. Here, the amorphous silicon film is formed by reacting SiH ₄ gas with hydrogen or helium gas, wherein a small amount of nitrogen gas such as N ₂ , N ₂ O, NF _3, or the like is injected. Preferably, it is preferable to inject at a ratio of 1/100 to 1 / 1,000 Sccm of the SiH 4 gas.

In this case, the injected nitrogen gas is charged with nitrogen ions to exist inside or on the surface of the amorphous silicon film and incorporate at a ratio of 1/100 to 1 / 1,000 of the silicon atoms.

The amorphous silicon film is crystallized by laser annealing, furnace annealing, sequential side crystallization (SLS), and then patterned to form a polycrystalline silicon layer 150A.

At this time, nitrogen ions contained in the amorphous silicon film are bonded to the bonding loss of the silicon. Some of the silicon of the amorphous silicon film has a large number of bonding hands that do not bond with any carrier.

Silicon atoms bound to nitrogen ions no longer bind to other carriers, and thus do not form defects or protrusions on the surface due to the bonding loss of silicon and the grains bonded to other carriers during crystallization.

Next, an insulating material such as silicon nitride or silicon oxide is deposited on the polysilicon layer 150A by chemical vapor deposition to form a gate insulating layer 140.

As shown in FIGS. 11A and 11B, a metal film is formed by depositing titanium, aluminum, tungsten, or an alloy thereof in a single layer or a plurality of layers on the gate insulating layer 140.

Thereafter, the photoresist is coated on the metal layer, and then the photoresist pattern PR is formed by a photo process using a photomask. In this case, the metal film is patterned using the photoresist pattern PR to form the gate lines 121 and 124, the storage electrode lines 131 and 133, and the data metal piece 171a. When the storage capacitor is sufficient, the storage electrode line 131 and the storage electrode 133 are not formed. Here, the metal film is over-etched to form a width of the gate line 121 and the storage electrode line 131 smaller than that of the photosensitive film pattern PR.

Afterwards, the source and drain regions 153 and 155 are formed by doping N-type or P-type impurity ions to the polycrystalline silicon layer 150A at high concentration using the photoresist pattern PR as a mask.

Next, as shown in FIG. 12, after removing the photoresist pattern PR, the semiconductor layer 150 is doped with low concentration of the same impurity ions as the source and drain regions 153 and 155 using the gate lines 121 and 124 as a mask. The semiconductor layer 150 including the lightly doped region 152 is completed.

In addition, the semiconductor layer 150A may be exposed to the outside of the storage electrode lines 131 and 133 because of the difference in length and width of the semiconductor layer 150 and the storage electrode lines 131 and 133. These regions are also doped, adjacent to the sustain electrode region 157 and separated from the drain region 155.

The channel region 154 is an intrinsic semiconductor that is not doped with polycrystalline silicon layer impurities located between the source region 153 and the drain region 155.

As described above, the lightly doped region 152 may be formed by using metal layers having different etching ratios in addition to the photoresist pattern, or by forming spacers or the like on sidewalls of the gate lines.

As shown in FIGS. 13A and 13B, the interlayer insulating layer 160 is formed of an insulating material on the entire surface of the substrate on which the source region 153, the drain region 155, and the channel region 154 are formed. The interlayer insulating layer 160 is an organic material having excellent planarization characteristics and a photosensitive property, a low dielectric constant insulating material such as a-Si: C: O, a-Si: O: F, or inorganic material formed by plasma chemical vapor deposition. It may be formed of silicon nitride or the like.

Thereafter, the first contact hole 161 exposing the source region 153, the second contact hole 162 exposing the drain region 155, and the data metal piece 171a are exposed on the interlayer insulating layer 160. The fourth contact hole 164 exposing one end portion of the third contact hole 163, the gate lines 121 and 124, and the data metal piece 171a is formed.

When the interlayer insulating film is formed of an organic material having photosensitivity, the contact hole may be formed only by a photographic process.

8 and 9, a conductive layer is formed of a transparent conductive material on the interlayer insulating layer 160 including the first to fourth contact holes 161 to 164, and then patterned to form a data connection part 171b. And the pixel electrode 190 and the contact assistant member 82.

The data metal piece 171a is connected to the data connector 171b through the third contact hole 163, and the data connector 171b is connected to the source region 153 through the first contact hole 161. The pixel electrode 190 is connected to the drain region 155 through the second contact hole 162, and the contact auxiliary member 82 is connected to the data metal piece 171a through the fourth contact hole 164. .

In this case, when the interlayer insulating layer 160 is formed of an organic material having a low dielectric constant, the pixel electrode 190 may overlap the gate line and the data metal piece to improve the aperture ratio of the pixel region.

Although the present invention has been described with reference to one embodiment shown in the accompanying drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Could be. Accordingly, the true scope of protection of the invention should be defined only by the appended claims.

As described above, when nitrogen ions are combined with the bonding loss of silicon atoms to protect the semiconductor layer, the threshold voltage of the semiconductor layer does not increase, thereby providing a high quality thin film transistor array panel.

Claims (11)

Insulation board, A semiconductor layer having a source region and a drain region formed on the insulating substrate and doped with a high concentration of conductive impurities, and having a channel region disposed between the source region and the drain region and not doped with impurities; A gate insulating film formed on the semiconductor layer, A gate line formed on the gate insulating layer and having a gate electrode overlapping the channel region; A first interlayer insulating layer formed on the gate line and having first and second contact holes exposing source and drain regions, respectively; A data line formed on the first interlayer insulating layer and having a source electrode connected to the source region through the first contact hole; A drain electrode formed on the interlayer insulating layer and connected to the drain region through the second contact hole; A second interlayer insulating layer formed on the data line and the drain electrode and having a third contact hole exposing the drain electrode; A pixel electrode formed on the second interlayer insulating layer and connected to the drain electrode; A thin film transistor array panel in which some of the silicon atoms of the semiconductor layer are bonded to nitrogen ions. Insulation board, A semiconductor layer having a source region and a drain region formed on the insulating substrate and doped with a high concentration of conductive impurities, and having a channel region disposed between the source region and the drain region and not doped with impurities; A gate insulating film formed on the semiconductor layer, A gate line formed on the gate insulating layer and having a gate electrode overlapping the channel region; A data metal piece positioned a predetermined distance apart from the neighboring gate lines and extending in a direction perpendicular to the gate line; An interlayer insulating film formed on the gate line and the data metal piece, A data connection part formed on the interlayer insulating film and crossing the gate line to electrically connect the data metal piece through a contact hole; A pixel electrode formed on the interlayer insulating layer and connected to the drain region through a contact hole; And a portion of the silicon atoms of the semiconductor layer are bonded to nitrogen ions. The method of claim 1 or 2, The thin film transistor array panel of claim 1, further comprising a blocking layer formed on an entire surface of the substrate and formed under the semiconductor layer. The method of claim 1 or 2, And a lightly doped region formed between the source region and the channel region between the drain region and the channel region, and lightly doped with a second conductivity type impurity. The method of claim 1 or 2, And the nitrogen ions of the semiconductor layer are contained at a ratio of 1/100 to 1 / 1,000 of the silicon atom volume. Forming an amorphous silicon film on the insulating substrate using a mixed gas containing nitrogen gas, Crystallizing and patterning the amorphous silicon film to form a polycrystalline silicon layer, Forming a gate insulating film on the polycrystalline silicon layer, Forming a gate line overlying the polysilicon layer on the gate insulating layer, Forming a semiconductor layer having a source region, a channel region, and a drain region by doping a predetermined amount of conductive impurities in a predetermined region of the polysilicon layer with the gate line as a mask; Forming a first interlayer insulating film to cover the semiconductor layer, Forming a data line having a source electrode connected to the source region and a drain electrode connected to the drain region on the first interlayer insulating layer; Forming a second interlayer insulating film on the data line and the drain electrode; And forming a pixel electrode connected to the drain electrode on the second interlayer insulating layer. Forming an amorphous silicon film on the insulating substrate using a mixed gas containing nitrogen gas, Crystallizing and patterning the amorphous silicon film to form a polycrystalline silicon layer, Forming a gate insulating film on the polycrystalline silicon layer, Forming a gate line and a data metal piece on which the portion of the polycrystalline silicon layer overlaps with the gate insulating film, Forming a semiconductor layer having a source region, a channel region, and a drain region by doping a predetermined amount of conductive impurities in a predetermined region of the polysilicon layer using the gate line as a mask; Forming an interlayer insulating film to cover the semiconductor layer; Forming a data line having a source electrode connected to the source region and a pixel electrode connected to the drain region on the interlayer insulating layer. The method of claim 6 or 7, The method of claim 1, further comprising forming a blocking layer on the insulating substrate. In claim 6 or 7, The mixed gas further comprises a H ₂ or He ₂ gas and a SiH ₄ gas. In claim 6 or 7, The nitrogen gas is a manufacturing method of a thin film transistor array panel using any one of N ₂ O, N ₂ , NF ₃ . In claim 9, The nitrogen gas is formed by injecting the SiH ₄ gas at a ratio of 1/100 to 1 / 1,000 Sccm.

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