KR101090244B1 - Opticmask for crystalization and manufacturing method of thin film transistor array panel using the same, thin film transistor array panel - Google Patents

Abstract

In the photomask for crystallization according to the present invention, in the photomask for crystallizing the amorphous silicon, the photomask is arranged at regular intervals and has a blocking portion for locally blocking the laser beam, the blocking portion has a rhombus shape.

Thin Film Transistors, Polycrystalline, SLS

Description

Optical mask for crystallization and manufacturing method of thin film transistor array panel using the same, thin film transistor array panel

1 is a layout view of a thin film transistor array panel for describing an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along the line II-II 'of FIG. 1,

3A, 6A, 8A, and 9A are layout views in an intermediate step of manufacturing a thin film transistor array panel according to a first exemplary embodiment of the present invention.

3B is a cross-sectional view taken along the line IIIb-IIIb ′ of FIG. 3A;

4 is a view showing the movement of the optical mask for explaining the crystallization method according to the present invention,

5 is a view showing a crystal pattern formed after crystallization according to the present invention,

FIG. 6B is a cross-sectional view taken along the line VIb-VIb ′ of FIG. 6A;

7 is a cross-sectional view at the next step of FIG. 6B,

FIG. 8B is a cross-sectional view taken along the line VIIIb-VIIIb ′ of FIG. 8A;

FIG. 9B is a cross-sectional view taken along the line IXb-IXb ′ of FIG. 9A;                 

10 is a layout view of a thin film transistor array panel for a liquid crystal display according to a second exemplary embodiment of the present invention.

FIG. 11 is a cross-sectional view taken along the line XI-XI′-XI ″ of FIG. 10.

12A, 13A, and 15A are layout views in an intermediate step of manufacturing a thin film transistor array panel according to a second exemplary embodiment of the present invention.

12B is a cross-sectional view taken along the line XIIb-XIIb′-XIIb ″ of FIG. 12A, and

13B is a cross-sectional view taken along the line XIIIb-XIIIb'-XIIIb "of 13a,

14 is a sectional view at the next step of FIG. 13B,

15B is a cross-sectional view taken along the line XVb-XVb'-XVb "of FIG. 15A.

※ Explanation of symbols on main parts of drawing ※

110: insulated substrate 121: gate line

124: gate electrode 131: sustain electrode line

133 sustain electrode 140 gate insulating film

150: semiconductor layer 153: source region

154: channel region 155: drain region

171: data line 173: source electrode

175: drain electrode 190: pixel electrode

The present invention relates to a crystal photomask for crystallizing amorphous silicon with polycrystalline silicon, a thin film transistor array panel using the same, and a method of manufacturing the same.

Generally, silicon may be divided into amorphous silicon and crystalline silicon according to the crystal state. Amorphous silicon can be deposited at a low temperature to form a thin film, and is mainly used in semiconductor layers of switching elements of display devices that use glass having a low melting point as a substrate.

However, the amorphous silicon thin film has difficulty in large area of the display device due to problems such as low field effect mobility. Therefore, there is a demand for the application of polycrystalline silicon having high field effect mobility, high frequency operating characteristics, and low leakage current electrical characteristics.

Methods of forming such polycrystalline silicon include ELA (eximer laser anneal, ELA), furnace annealing (chamber annal), and recently, sequential lateral which produces polycrystalline silicon by inducing lateral growth of silicon crystals with a laser. solidification, hereinafter referred to as SLS) technology.

The SLS technology takes advantage of the fact that silicon particles grow at the interface between liquid silicon and solid silicon in a direction perpendicular to the interface, and shift the size of the laser beam energy and the range of irradiation of the laser beam to the optical system and the mask. It is appropriately used to crystallize the amorphous silicon by lateral growth of the silicon particles by a predetermined length.

However, the electrical properties of the thin film using polycrystalline silicon are greatly influenced by the size and uniformity of the grains. That is, as the size and uniformity of the particles increase, the field effect mobility also increases. Therefore, it is important to form large and uniform crystals with particles.

SUMMARY OF THE INVENTION The present invention provides a thin film transistor array panel having a crystallization photomask, a uniform crystal using the same, and a method of manufacturing the same.

Crystallization optical mask according to the present invention for achieving the above object in the optical mask for crystallizing the amorphous silicon, the optical mask is arranged at regular intervals and has a blocking portion for locally blocking the laser beam, the blocking portion rhombus shape Has

At this time, the obtuse angle of the rhombus is preferably 90 to 170 degrees. In the photomask, neighboring rhombuses are staggered.
According to another aspect of the present invention, there is provided a method of manufacturing a thin film transistor array panel, including forming a blocking film on an insulating substrate, forming an amorphous silicon film on the blocking film, and irradiating a laser beam through an optical mask to the amorphous silicon film. Forming a polycrystalline silicon film, patterning the polycrystalline silicon film to form a semiconductor layer of the thin film transistor, forming a gate insulating film to cover the semiconductor layer, and forming a gate line partially overlapping the semiconductor layer on the gate insulating film Forming a source region and a drain region by highly doping conductive type impurities in a predetermined region of the semiconductor layer; forming a first interlayer insulating layer to cover the gate line and the semiconductor layer; A data line having a source electrode connected thereto and a node connected to a drain region Forming a lane electrode, forming a second interlayer insulating film on the data line and the drain electrode, and forming a pixel electrode connected to the drain electrode on the second interlayer insulating film, wherein the photomasks are arranged at regular intervals And a blocking portion that locally blocks the laser beam, and the blocking portion has a rhombus shape.

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Or forming a blocking film on the insulating substrate, forming an amorphous silicon film on the blocking film, irradiating a laser beam through the photomask on the amorphous silicon film to form a polycrystalline silicon film, and patterning the polycrystalline silicon film to form a semiconductor layer. Forming a gate insulating film to cover the semiconductor layer, forming a gate line and a data metal piece partially overlapping the semiconductor layer on the gate insulating film, doping a predetermined region of the semiconductor layer with a high concentration of a conductive impurity in the source region, Forming a drain region, forming an interlayer insulating film to cover the semiconductor layer, forming a data connection portion connected to the source region and the data metal piece on the interlayer insulating film, and forming a pixel electrode connected to the drain region, the photomask Are arranged at regular intervals and locally With parts of block to block, block portion has a rhombus shape.

The method may further include forming a lightly doped region by doping the semiconductor layer at a lower concentration than the source and drain regions.

The conductive impurity is preferably a P-type or an N-type semiconductor ion.                     

In addition, it is preferable that the obtuse angle of a rhombus is 90-170 degree, and it is preferable that adjacent rhombuses are staggered.
In accordance with another aspect of the present invention, a thin film transistor array panel includes an insulating substrate, a gate line formed on the insulating substrate, a data line crossing the gate line, a thin film transistor connected to the gate line and the data line, and a thin film transistor. The semiconductor layer of the thin film transistor includes a pixel electrode connected to each other, and the semiconductor layer of the thin film transistor is formed in a region surrounded by the first grain having a rhombus shape, the second grain perpendicular to each side of the first grain, the first grain and the second grain. It has a plurality of third grains.

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Or a semiconductor layer formed on an insulating substrate, an insulating substrate, and having a source region and a drain region doped with conductive impurities, and a channel region not doped with impurities, a gate insulating layer formed on the semiconductor layer, and a gate insulating layer formed on the channel. It is formed on the interlayer insulating film and the interlayer insulating film formed on the data metal piece, the gate line and the data metal piece extending in a direction perpendicular to the gate line and positioned at a predetermined distance between the gate line overlapping the region and the neighboring gate line. A data connection part electrically connecting the data metal piece through the contact hole to intersect the gate line, and including a pixel electrode formed on the interlayer insulating layer and connected to the drain region through the contact hole, and the semiconductor layer includes a first diamond, 1 second grain perpendicular to each side of the grain Has a plurality of crystal grains formed in the third region is defined by a lip, and the second crystal grains.

Here, the third crystal grains are formed in a rhombus shape and larger than the first crystal grains, and the third crystal grains are single crystals.

Moreover, it is preferable that the vertex of a 3rd crystal grain contact | connects the vertex of a 1st crystal grain.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, area, plate, etc. is over another part, this includes not only the part directly above the other part but also another part in the middle. On the contrary, when a part is just above another part, it means that there is no other part in the middle.

Hereinafter, a thin film transistor array panel and a method of manufacturing the same according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

[First Embodiment]

1 is a layout view of a thin film transistor array panel for explaining an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line II-II ′ of FIG. 1.

As illustrated, a blocking film 111 made of silicon oxide or the like is formed on the transparent insulating substrate 110. The semiconductor layer 150 includes a source region 153 doped with an impurity doped, a drain region 155, and a channel region 154 formed of an intrinsic semiconductor on the blocking layer 111. Is formed. A lightly doped drain 152 is formed between the source region 153 and the channel region 154 and the drain region 155 and the channel region 154 of the semiconductor layer 150.

The lightly doped region 152 prevents leakage current or punch through. In the source region 153 and the drain region 155, conductive impurities are heavily doped, and in the lightly doped region 152, the conductive impurities are less doped than the source region 153 and the drain region 155. .

The conductive impurity is a P-type or N-type impurity, and boron (B) and gallium (Ga) are used as the P-type impurity, and phosphorus (P), arsenic (As), etc. are used as the N-type impurity. This can be used.                     

The semiconductor layer 150 includes a plurality of first grains having a rhombus shape, second grains perpendicular to each side of the first grains, and third grains formed in a region defined by the second grains. This will be described in detail later with the manufacturing method of the thin film transistor array panel.

A gate insulating layer 140 made of silicon nitride, silicon oxide, or the like is formed on the semiconductor layer 150. In addition, a gate line 121 extending in one direction is formed on the gate insulating layer 140, and a portion of the gate line 121 extends to overlap the channel region 154 of the semiconductor layer 150. The lightly doped region 152 may be formed to overlap (not shown) the gate line 121. The portion overlapping the channel region 154 is used as the gate electrode 124 of the thin film transistor.

In addition, the storage electrode line 131 for increasing the storage capacitance of the pixel is parallel to the gate line 121 and is formed in the same layer with the same material. A portion of the storage electrode line 131 overlapping the semiconductor layer 150 becomes the storage electrode 133, and the semiconductor layer 150 overlapping the storage electrode 133 becomes the storage electrode region 157. One end of the gate line 121 may be formed wider than the width of the gate line 121 in order to connect to an external circuit (not shown).

The first interlayer insulating layer 601 is formed on the gate insulating layer 140 including the gate line 121 and the storage electrode line 131. The first interlayer insulating layer 601 includes first and second contact holes 161 and 162 exposing the source region 153 and the drain region 155, respectively.

A data line 171 is formed on the first interlayer insulating layer 601 to cross the gate line 121 to define a pixel area. A portion or branched portion of the data line 171 is connected to the source region 153 through the first contact hole 161, and the portion 173 connected to the source region 153 is a source electrode (eg, a thin film transistor). 173). One end of the data line 171 may be formed wider than the width of the data line 171 to connect to an external circuit.

A drain electrode 175 is formed on the same layer as the data line 171 and is separated from the source electrode 173 and connected to the drain region 155 through the second contact hole 162.

A second interlayer insulating layer 602 is formed on the first interlayer insulating layer 601 including the drain electrode 175 and the data line 171. The second interlayer insulating layer 602 has a third contact hole 163 exposing the drain electrode 175.

The pixel electrode 190 connected to the drain electrode 175 is formed on the second interlayer insulating layer 602 through the third contact hole 163. An alignment layer 11 is formed on the pixel electrode 190, and the alignment layer 11 is rubbed to determine a horizontal direction of the liquid crystal.

A method of manufacturing the thin film transistor array panel according to the first embodiment of the present invention described above will be described in detail with reference to FIGS. 1 and 2 previously described with reference to FIGS. 3A to 9B.

3A, 6A, 8A, and 9A are layout views in an intermediate step of manufacturing a thin film transistor array panel according to a first exemplary embodiment of the present invention, and FIG. 3B is a cross-sectional view taken along line IIIb-IIIb 'of FIG. 3A. 4 is a view showing the movement of the photomask for explaining the crystallization method according to the present invention, Figure 5 is a view showing a crystal pattern formed after crystallization according to the present invention, Figure 6b is a VIb- of FIG. 7B is a cross-sectional view taken along the line VIb ', FIG. 7 is a cross-sectional view taken along the line of FIG. 6B, FIG. 8B is a cross-sectional view taken along the line VIIIb-VIIIb' of FIG. 8A, and FIG. 9B is a line IXb-IXb 'of FIG. 9A. The cross section is cut along the side.

First, as shown in FIGS. 3A and 3B, the blocking layer 111 is formed on the transparent insulating substrate 110. In this case, glass, quartz, sapphire, or the like may be used as the transparent insulating substrate 110, and the blocking layer is formed by depositing silicon oxide (SiO ₂ ) or silicon nitride (SiNx) to a thickness of about 1,000 GPa. Subsequently, impurities such as a native oxide film on the blocking film 111 are removed by cleaning.

Next, an amorphous silicon film which is not doped with impurities is formed to a thickness of 400 to 1,200 kPa by a method such as chemical vapor deposition.

Then, the amorphous silicon film is polycrystallized using the SLS method to form a polycrystalline silicon film. The polycrystalline silicon film 501 is patterned by a photolithography process using a photomask to form a semiconductor layer 150 made of polycrystalline silicon.

A method of crystallization by the SLS method with reference to Figure 4 in more detail as follows.

First, the photomask MP having a predetermined pattern is aligned on the amorphous silicon film 10. Here, the photomask MP has a first portion A through which light is transmitted and a second portion B through which light is blocked. In this case, the second portion B in which light is blocked is formed in a rhombus shape, and the obtuse angle of the rhombus has an angle of 90 to 170. The rhombus is arranged at regular intervals. That is, the rhombuses are arranged in rows at regular intervals, and the rhombuses of neighboring rows are staggered from each other.

Then, the laser beam is irradiated onto the amorphous silicon film 10 through the first portion A of the photomask MP. The amorphous silicon of the portion A irradiated with the laser turns into a liquid phase, and the amorphous silicon of the portion B not irradiated with the laser remains in a solid state.

Therefore, crystallization proceeds at the interface between the liquid phase and the solid phase. The crystal grains grow vertically with respect to the boundary surface of the solid phase, and the grains grow vertically at the portion corresponding to the boundary line of the second part (B). In addition, at the vertex of the second part B, crystallization is performed on one single crystal 20 so that the size of the crystal grains is larger than that of the other portions B and 30.

When the size of the amorphous silicon film 10 is larger than the photomask MP, the whole of the amorphous silicon film 10 is crystallized by moving vertically or horizontally by the width W or the length L of the photomask MP. . In this case, the second part B may be crystallized by the heat transferred from the first part A, or may be crystallized after the liquid crystallization using a mask through which light is transmitted to the second part B. .

As the crystallization proceeds in this manner, as shown in FIG. 5, the first crystal grains B formed in the second portion B and the second crystal grains perpendicular to each side of the first grain grains B have a shape ( 30), a pattern is formed in which the third crystal grains 20 formed in the region defined by the second crystal grains 30 are arranged at regular intervals.

Here, the third crystal grain 20 is a rhombic single crystal formed larger than the first crystal grain B. At this time, the vertex of the third grain 20 is in contact with the vertex of the first grain.

Thereafter, an insulating material such as silicon nitride or silicon oxide is deposited on the semiconductor layer 150 to form a gate insulating layer 140.

6A and 6B, a single layer or a plurality of layers of silver (Ag), copper (Cu), titanium (Ti), aluminum (Al), tungsten (W) or alloys thereof are formed on the gate insulating layer 140. Vapor deposition to form a metal film.

After the photoresist is coated on the metal layer, the photoresist pattern PR is formed by a photo process using a photomask. The gate layer 121 and the storage electrode line 131 are formed by wet or dry etching the metal layer by an etching process. At this time, the metal film is over-etched to form a width of the gate line 121 and the storage electrode line 131 smaller than that of the photosensitive film pattern PR.

Side surfaces of the gate line 121 and the storage electrode line 131 are formed to be tapered to increase adhesion to the upper layer. If the storage capacitor is sufficient, the storage electrode line 131 is not formed.

Thereafter, the semiconductor layer 150 is doped with a high concentration of conductive impurities using the photoresist pattern PR as a mask to form source and drain regions 153 and 155.

Next, as shown in FIG. 7, after the photoresist pattern PR is removed, the semiconductor layer 150 is lightly doped with a conductive dopant in a low concentration doped region 152 using the gate line 121 and the storage electrode line 131 as a mask. The semiconductor layer 150 having () is completed. When the gate line 121 is not formed of a high heat resistant and high chemical material such as titanium, an impurity may be doped after forming the photoresist pattern PR to reduce damage to the wiring.

The lightly doped region 152 may be formed by using metal layers having different etching ratios in addition to the photoresist pattern PR as described above, or by forming spacers or the like on sidewalls of the gate line 121.

In addition, the semiconductor layer 150A may be exposed to the outside of the storage electrode lines 131 and 133 because of the difference in length and width of the semiconductor layer 150 and the storage electrode lines 131 and 133. These regions are also doped, adjacent to the sustain electrode region 157 and separated from the drain region 155.

Subsequently, as shown in FIGS. 8A and 8B, a first interlayer insulating film 601 is formed on the entire surface of the substrate 110 and etched by a photolithography process to expose the source and drain regions 153 and 155. The contact holes 161 and 162 are formed.

The interlayer insulating layer 160 has excellent planarization characteristics, and is formed of a-Si: C: O, a-Si: O: organic material having photosensitivity, and plasma enhanced chemical vapor deposition (PECVD). Low dielectric constant insulating materials, such as F, or an inorganic material, such as silicon nitride can be formed.

Next, tungsten, titanium, aluminum, or an alloy thereof is deposited on the first interlayer insulating film 601 in a single layer or a plurality of layers to form a metal film. Subsequently, the metal layer is patterned by a photolithography process, and the data line 171 and the drain electrode 175 having the source electrode 173 connected to the source region 153 and the drain region 155 through the contact holes 161 and 162, respectively. ).

Sidewalls of the data line 171 and the drain electrode 175 may be formed to be tapered to improve adhesion to the upper layer.

As shown in FIGS. 9A and 9B, a second interlayer insulating film 602 covering the data line 171 and the drain electrode 175 is formed. Thereafter, the second interlayer insulating layer 602 is patterned by a photolithography process to form a third contact hole 163 exposing the drain electrode 175. The second interlayer insulating film 602 may also be formed of the same material as the first interlayer insulating film 601.

1 and 2, a transparent conductive film such as indium zinc oxide (IZO), indium tin oxide (ITO), or the like is formed on the second interlayer insulating film, and then patterned and drained through the third contact hole 163. The pixel electrode 190 connected to the electrode 175 is formed. When the second interlayer insulating layer 602 is formed of an organic material having a low dielectric constant, the pixel electrode 190 may overlap the data line and the gate line to improve the aperture ratio of the pixel region. Then, the alignment layer 11 covering the pixel electrode 190 is formed and then rubbed.

 Second Embodiment

FIG. 10 is a layout view of a thin film transistor array panel for a liquid crystal display according to a second exemplary embodiment of the present invention, and FIG. 11 is a cross-sectional view taken along the line XI-XI′-XI ″ of FIG. 10.

In Embodiment 2, the data connection part 171b and the pixel electrode 190 are formed on the same layer using the same material, and the pixel electrode 190 and the data connection part 171b are formed on the source and drain regions 153, Since the contact holes 161 and 162 for connecting to the respective 155 are formed at the same time, the number of masks can be reduced as compared with the first embodiment.

More specifically, as shown in FIGS. 10 and 11, the blocking layer 111 is formed on the transparent insulating substrate 110. A semiconductor layer including a source region 153, a drain region 155, and a channel region 154 formed of an intrinsic semiconductor between the conductive layer and the dopant having a high concentration of conductive impurities on the blocking layer 111. 150 is formed. Further, conductive impurities are doped at a lower concentration than the source and drain regions between the source region 153 and the channel region 154 and the drain region 155 and the channel region 154 of the semiconductor layer 150.

The semiconductor layer 150 has the same crystal pattern as that of the first embodiment. That is, a plurality of third crystal grains formed in the region defined by the first crystal grains having a rhombus shape, the second crystal grains perpendicular to the sides of the first crystal grains, and the second crystal grains are formed.

The gate insulating layer 140 is formed on the substrate 110 including the semiconductor layer 150. A gate line 121 extending in the horizontal direction is formed on the gate insulating layer 140, and a portion of the gate line 121 extends in the vertical direction to partially overlap the semiconductor layer 150, and overlaps the semiconductor layer 150. A portion of the gate line 121 is used as the gate electrode 124.

One end of the gate line 121 may be formed larger than the width of the gate line 121 to receive a scan signal from an external circuit (not shown).

In addition, the storage electrode line 131 is formed in the same layer with the same material as the gate line 121 so that the storage electrode line 131 is formed to be parallel to the gate line 121 and is positioned in parallel. A portion of the storage electrode line 131 overlapping the semiconductor layer 150 becomes the storage electrode 133, and the semiconductor layer 150 disposed under the storage electrode 133 becomes the storage electrode region 157.

The data metal piece 171a is formed at a distance from the gate line 121 and extends in a direction perpendicular to the gate line 121, and is formed on the same layer as the gate line 121. The data metal piece 171a is formed not to be connected to the gate line 121 between two adjacent gate lines 121. In addition, the data metal piece 171a may enlarge and form one end of the data metal piece 171a in the outermost row in order to receive an image signal from an external circuit (not shown).

An interlayer insulating layer 160 is formed on the gate insulating layer 140 including the gate line 121 and the storage electrode line 131.

The data connection part 171b, the pixel electrode 190, and the contact auxiliary member 82 are formed on the interlayer insulating layer 160. The data connection part 171b is formed to cross the gate line 121 and the storage electrode line 131 in the vertical direction.

The data metal piece 171a is connected to the data connecting portion 171b through the third contact hole 163 formed in the interlayer insulating layer 160, and the data connecting portion 171b is connected to the source through the first contact hole 161. It is connected to the area 153. That is, the data metal pieces 171a separated by the data connection part 171b are connected across the gate line 121 and the storage electrode line 131. The pixel electrode 190 is connected to the drain region 155 through a second contact hole 162 formed over the interlayer insulating layer 160 and the gate insulating layer 140, and the contact auxiliary member 82 is interlayered. The fourth contact hole 164 formed in the insulating layer 160 is connected to one end of the gate line 121 and the data metal piece 171a, respectively.

The contact auxiliary member 82 is not essential to serve to protect adhesion between the end of the data line 171a and the external device and to protect them, and application thereof is optional. In particular, when the driving circuit is formed together with the thin film transistor in the display area, it is not formed.

An alignment layer 11 is formed on the pixel electrode 190, and the alignment layer 11 is rubbed to determine a horizontal direction of the liquid crystal.

A method of manufacturing the thin film transistor array panel according to the second embodiment of the present invention described above will be described in detail with reference to FIGS. 10 and 11 together with FIGS. 12A to 15B.

12A, 13A, and 15A are layout views in an intermediate step of manufacturing a thin film transistor array panel according to a second exemplary embodiment of the present invention, and FIG. 12B is a cross-sectional view taken along the line XIIb-XIIb′-XIIb ″ of FIG. 12A. FIG. 13B is a cross-sectional view taken along the line XIIIb-XIIIb'-XIIIb "of 13A, FIG. 14 is a cross-sectional view at the next step of FIG. 13B, and FIG. 15B is taken along the line XVb-XVb'-XVb" of FIG. 15A It is a cross section.

First, as shown in FIGS. 12A and 12B, the blocking layer 111 is formed on the transparent insulating substrate 110. In this case, glass, quartz, sapphire, or the like may be used as the transparent insulating substrate 110, and the blocking layer is formed by depositing silicon oxide (SiO ₂ ) or silicon nitride (SiNx) to a thickness of about 1,000 GPa. Subsequently, impurities such as a native oxide film on the blocking film 111 are removed by cleaning.

Next, an amorphous silicon film which is not doped with impurities is formed to a thickness of 400 to 1,200 kPa by a method such as chemical vapor deposition.

Then, the amorphous silicon film is polycrystallized using the SLS method to form a polycrystalline silicon film. The crystallization method is the same as that of FIGS. 4 and 5 of the first embodiment.

The polycrystalline silicon film 501 is patterned by a photolithography process using a photomask to form a semiconductor layer 150 made of polycrystalline silicon. Therefore, the semiconductor layer 150 has the same crystal pattern as in the first embodiment.

The gate insulating layer 140 is formed by depositing an insulating material such as silicon nitride or silicon oxide on the semiconductor layer 150 by chemical vapor deposition.

13A and 13B, a single layer of copper (Cu), silver (Ag), titanium (Ti), aluminum (Al), tungsten (W), or an alloy thereof is formed on the gate insulating layer 140. It deposits in multiple layers, and forms a metal film.

After the photoresist is coated on the metal layer, the photoresist pattern PR is formed by a photo process using a photomask. The metal film is wet or dry etched by the etching process to form the gate line 121, the storage electrode line 131, and the data metal piece 171a. At this time, the metal film is overetched to form a width smaller than that of the photoresist pattern PR.

Sides of the gate line 121, the storage electrode line 131, and the data metal piece 171a are formed to be tapered to increase adhesion to the upper layer. If the storage capacitor is sufficient, the storage electrode line 131 is not formed.

Thereafter, the semiconductor layer 150 is doped with a high concentration of conductive impurities using the photoresist pattern PR as a mask to form source and drain regions 153 and 155.

Next, as shown in FIG. 14, after the photoresist pattern PR is removed, the semiconductor layer 150 is lightly doped with a conductive dopant in a low concentration doping region 152 using the gate line 121 and the storage electrode line 131 as a mask. The semiconductor layer 150 having () is completed. When the gate line 121 is not formed of a high heat resistant and high chemical material such as titanium, an impurity may be doped after forming the photoresist pattern PR to reduce damage to the wiring.

The lightly doped region 152 may be formed by using metal layers having different etching ratios in addition to the photoresist pattern PR as described above, or by forming spacers or the like on sidewalls of the gate line 121.

In addition, the semiconductor layer 150A may be exposed to the outside of the storage electrode lines 131 and 133 because of the difference in length and width of the semiconductor layer 150 and the storage electrode lines 131 and 133. These regions are also doped, adjacent to the sustain electrode region 157 and separated from the drain region 155.

As shown in FIGS. 15A and 15B, an interlayer insulating layer 160 is formed of an insulating material on the entire surface of the substrate on which the source region 153, the drain region 155, and the channel region 154 are formed. The interlayer insulating layer 160 is an organic material having excellent planarization characteristics and a photosensitive property, a low dielectric constant insulating material such as a-Si: C: O, a-Si: O: F, or inorganic material formed by plasma chemical vapor deposition. It may be formed of silicon nitride or the like.

Thereafter, the first contact hole 161 exposing the source region 153, the second contact hole 162 exposing the drain region 155, and the data metal piece 171a are exposed on the interlayer insulating layer 160. The third contact hole 163 and the fourth contact hole 164 exposing one end of the data metal piece 171a are formed.

When the interlayer insulating film is formed of an organic material having photosensitivity, the contact hole may be formed only by a photographic process.

As shown in FIGS. 10 and 11, a conductive layer is formed of a transparent conductive material on the interlayer insulating layer 160 including the first to fourth contact holes 161 to 164, and then patterned to form a data connection part 171b. And the pixel electrode 190 and the contact assistant member 82.

The data metal piece 171a is connected to the data connector 171b through the third contact hole 163, and the data connector 171b is connected to the source region 153 through the first contact hole 161. The pixel electrode 190 is connected to the drain region 155 through the second contact hole 162, and the contact auxiliary member 82 is connected to the data metal piece 171a through the fourth contact hole 164. .

In this case, when the interlayer insulating layer 160 is formed of an organic material having a low dielectric constant, the pixel electrode 190 may overlap the gate line 121 and the data metal piece 171b to improve the aperture ratio of the pixel region.

Then, the alignment layer 11 covering the pixel electrode 190 is formed and then rubbed.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, when the amorphous silicon film is crystallized using a photomask having a rhombus pattern, a polycrystalline silicon film having a large crystal size can be formed. Therefore, the field mobility can be maximized to provide a high quality thin film transistor array panel.

Claims (15)

In the photomask for crystallizing amorphous silicon, The optical mask has a light transmitting portion and a light blocking portion, the light blocking portion is a crystallization optical mask comprising at least one rhombus shape. In claim 1, The obtuse angle of the rhombus is a photomask for crystallization is 90 ~ 170 degrees. In claim 1, The rhombus neighboring in the photomask is arranged to form a matrix, Rhombus located in two adjacent columns is a crystallization photomask located in different rows. Forming a blocking film on the insulating substrate, Forming an amorphous silicon film on the blocking film, Irradiating a laser beam through the photomask on the amorphous silicon film to form a polycrystalline silicon film, Patterning the polycrystalline silicon film to form a semiconductor layer of a thin film transistor, Forming a gate insulating film to cover the semiconductor layer; Forming a gate line partially overlapping the semiconductor layer on the gate insulating layer; Forming a source region and a drain region by highly doping conductive type impurities in a predetermined region of the semiconductor layer, Forming a first interlayer insulating film to cover the gate line and the semiconductor layer; Forming a data line having a source electrode connected to the source region and a drain electrode connected to the drain region on the first interlayer insulating layer; Forming a second interlayer insulating film on the data line and the drain electrode; Forming a pixel electrode connected to the drain electrode on the second interlayer insulating film, The photomask has a light transmitting portion and a light blocking portion, wherein the light blocking portion has at least one rhombus shape. Forming a blocking film on the insulating substrate, Forming an amorphous silicon film on the blocking film, Irradiating a laser beam through the photomask on the amorphous silicon film to form a polycrystalline silicon film, Patterning the polycrystalline silicon film to form a semiconductor layer of a thin film transistor, Forming a gate insulating film to cover the semiconductor layer; Forming a gate line and a data metal piece on which the semiconductor layer partially overlaps with the gate insulating film; Forming a source region and a drain region by highly doping conductive type impurities in a predetermined region of the semiconductor layer, Forming an interlayer insulating film to cover the semiconductor layer; Forming a data connection part connected to the source region and the data metal piece and a pixel electrode connected to the drain area on the interlayer insulating film; The photomask has a light transmitting portion and a light blocking portion, wherein the light blocking portion has at least one rhombus shape. The method of claim 4 or 5, The semiconductor layer further includes a channel region overlapping the gate electrode, And doping the semiconductor layer at a lower concentration than the source and drain regions to form a lightly doped region between the source region and the channel region and between the drain region and the channel region. The manufacturing method of a display panel. The method of claim 4 or 5, And the conductive impurity is a p-type or n-type semiconductor ion. The method of claim 4 or 5, The obtuse angle of the rhombus is a manufacturing method of a thin film transistor array panel of 90 to 170 degrees. The method of claim 4 or 5, The method of manufacturing a thin film transistor array panel in which neighboring rhombuses are staggered. Insulation board, A gate line formed on the insulating substrate, A data line intersecting the gate line, A thin film transistor connected to the gate line and the data line, A pixel electrode connected to the thin film transistor Including, The semiconductor layer of the thin film transistor includes polycrystalline silicon crystallized using the photomask of claim 1, The semiconductor layer has a plurality of thin film transistors having a rhombus shaped first crystal grain, a second crystal grain perpendicular to each side of the first crystal grain, and a third crystal grain formed in an area surrounded by the first crystal grain and the second crystal grain. Display panel. delete In claim 10, And the third crystal grains have a rhombus shape and are formed larger than the first crystal grains. In claim 10, The third crystal grain is a single crystal thin film transistor array panel. The method of claim 12, The vertex of the third grain is in contact with the vertex of the first grain. delete

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