KR20050053146A - Method of crystallization and manufacturing method of thin film transistor array panel using the same - Google Patents

Abstract

A method of manufacturing a thin film transistor array panel according to the present invention includes the steps of forming a blocking film on an insulating substrate, forming an amorphous silicon film on the blocking film, applying a current to the amorphous silicon film to crystallize the amorphous silicon film to form a polycrystalline silicon film, polycrystalline Patterning a silicon film to form a semiconductor layer, forming a gate insulating film to cover the semiconductor layer, forming a gate line overlapping a portion of the semiconductor layer on the gate insulating film, and applying a conductive impurity to a predetermined region of the semiconductor layer Doping at a high concentration to form a source region and a drain region, forming a first interlayer insulating film to cover the gate line and the semiconductor layer, and a data line and a drain region having a source electrode connected to the source region on the first interlayer insulating film Forming a drain electrode connected to the data line; And a step, forming a pixel electrode connected to the drain electrode on the second interlayer insulating film forming the second interlayer insulating film on the electrode.

Description

Crystallization method and manufacturing method of thin film transistor array panel using same {Method of crystallization and manufacturing method of thin film transistor array panel using the same}

The present invention relates to a polycrystallization method for crystallizing amorphous silicon and a method for manufacturing a thin film transistor array panel using the same.

Generally, silicon may be divided into amorphous silicon and crystalline silicon according to the crystal state. Amorphous silicon can be deposited at a low temperature to form a thin film, and is mainly used in semiconductor layers of switching elements of display devices that use glass having a low melting point as a substrate.

However, the amorphous silicon thin film has difficulty in large area of the display device due to problems such as low field effect mobility. Therefore, there is a need for the application of polycrystalline silicon having high field effect mobility, high frequency operating characteristics, and low leakage current electrical characteristics.

The electrical properties of thin films using polycrystalline silicon are greatly influenced by the size and uniformity of the grains. That is, as the size and uniformity of the particles increase, the field effect mobility also increases. Methods of forming such polycrystalline silicon include ELA (eximer laser anneal, ELA), furnace annealing (chamber annal), and recently, sequential lateral which produces polycrystalline silicon by inducing lateral growth of silicon crystals with a laser. solidification, hereinafter referred to as SLS) technology.

The SLS technology takes advantage of the fact that silicon particles grow at the interface between liquid silicon and solid silicon in a direction perpendicular to the interface, and shift the size of the laser beam energy and the range of irradiation of the laser beam to the optical system and the mask. It is appropriately used to crystallize the amorphous silicon by lateral growth of the silicon particles by a predetermined length.

In addition, ELA technology uses an excimer laser as a light source to irradiate an amorphous silicon film with laser light to crystallize the polysilicon while moving the irradiation area of the laser light little by little.

That is, the laser beam is aligned and irradiated so that a part of the irradiation area is overlapped with several irradiations, and the crystallization process is performed while irradiating an arbitrary portion several times.

The crystallization method using such laser equipment is expensive in laser equipment. Therefore, there is a problem that the production cost increases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems and provides a crystallization method and a method of manufacturing a thin film transistor array panel capable of crystallizing amorphous silicon at low cost.

The crystallization method according to the present invention for achieving the above object is to crystallize the amorphous silicon film using Joule heat.

Specifically, the crystallization method includes forming an amorphous silicon film on an insulating substrate, and crystallizing the amorphous silicon film using a Joule heat method.

Here, the Joule heat method includes melting the amorphous silicon film using Joule heat, and cooling the amorphous silicon film.

In this case, the melting step is preferably made by applying a current to the amorphous silicon film to generate Joule heat.

According to another aspect of the present invention, there is provided a method of manufacturing a thin film transistor array panel, the method including forming a blocking film on an insulating substrate, forming an amorphous silicon film on the blocking film, and applying an electric current to the amorphous silicon film to crystallize the amorphous silicon film. Forming a polycrystalline silicon film, patterning the polycrystalline silicon film to form a semiconductor layer, forming a gate insulating film to cover the semiconductor layer, forming a gate line partially overlapping the semiconductor layer on the gate insulating film, and a semiconductor layer Forming a source region and a drain region by doping a predetermined concentration of the conductive impurities in a high concentration; forming a first interlayer insulating film to cover the gate line and the semiconductor layer; a source connected to the source region on the first interlayer insulating film A data line having an electrode and a drain electrode connected to the drain region Forming a second interlayer insulating film on the data line and the drain electrode; and forming a pixel electrode connected to the drain electrode on the second interlayer insulating film.

Or forming a blocking film on the insulating substrate, forming an amorphous silicon film on the blocking film, applying a current to a predetermined region of the amorphous silicon film to crystallize the amorphous silicon film to form a polycrystalline silicon film, and patterning the polycrystalline silicon film to form a semiconductor layer. Forming a gate insulating film so as to cover the semiconductor layer, forming a gate line and a data metal piece overlapping a portion of the semiconductor layer on the gate insulating film, and doping a predetermined amount of conductive impurities in a predetermined region of the semiconductor layer Forming a region, a drain region, forming an interlayer insulating film to cover the semiconductor layer, forming a data connection part connected to the source region and the data metal piece, and forming a pixel electrode connected to the drain region on the interlayer insulating film.

The method may further include forming a lightly doped region by doping the semiconductor layer at a lower concentration than the source and drain regions.

The conductive impurity is preferably a P-type or an N-type semiconductor ion.

In addition, the step of applying the current is preferably performed repeatedly at regular intervals with respect to the amorphous silicon film.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, area, plate, etc. is over another part, this includes not only the part directly above the other part but also another part in the middle. On the contrary, when a part is just above another part, it means that there is no other part in the middle.

Hereinafter, a thin film transistor array panel and a method of manufacturing the same according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

[First Embodiment]

1 is a layout view of a thin film transistor array panel for explaining an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line II-II ′ of FIG. 1.

As illustrated, a blocking film 111 made of silicon oxide or the like is formed on the transparent insulating substrate 110. The semiconductor layer 150 is formed on the blocking layer 111 and includes a source region 153 and a drain region 155 doped with impurities and a channel region 154 formed of an intrinsic semiconductor. Is formed. A lightly doped drain 152 is formed between the source region 153 and the channel region 154 and the drain region 155 and the channel region 154 of the semiconductor layer 150.

The lightly doped region 152 prevents leakage current or punch through. In the source region 153 and the drain region 155, conductive impurities are heavily doped, and in the lightly doped region 152, the conductive impurities are less doped than the source region 153 and the drain region 155. .

The conductive impurity is a P-type or N-type impurity, and boron (B) and gallium (Ga) are used as the P-type impurity, and phosphorus (P), arsenic (As), etc. are used as the N-type impurity. This can be used.

A gate insulating layer 140 made of silicon nitride, silicon oxide, or the like is formed on the semiconductor layer 150. In addition, a gate line 121 extending in one direction is formed on the gate insulating layer 140, and a portion of the gate line 121 extends to overlap the channel region 154 of the semiconductor layer 150. The lightly doped region 152 may be formed to overlap (not shown) the gate line 121. The portion overlapping the channel region 154 is used as the gate electrode 124 of the thin film transistor.

In addition, the storage electrode line 131 for increasing the storage capacitance of the pixel is parallel to the gate line 121 and is formed in the same layer with the same material. A portion of the storage electrode line 131 overlapping the semiconductor layer 150 becomes the storage electrode 133, and the semiconductor layer 150 overlapping the storage electrode 133 becomes the storage electrode region 157. One end of the gate line 121 may be formed wider than the width of the gate line 121 in order to connect to an external circuit (not shown).

The first interlayer insulating layer 601 is formed on the gate insulating layer 140 including the gate line 121 and the storage electrode line 131. The first interlayer insulating layer 601 includes first and second contact holes 161 and 162 exposing the source region 153 and the drain region 155, respectively.

A data line 171 is formed on the first interlayer insulating layer 601 to cross the gate line 121 and define a pixel area. A portion or branched portion of the data line 171 is connected to the source region 153 through the first contact hole 161, and the portion 173 connected to the source region 153 is a source electrode (eg, a thin film transistor). 173). One end of the data line 171 may be formed wider than the width of the data line 171 to connect to an external circuit.

A drain electrode 175 is formed on the same layer as the data line 171 and is separated from the source electrode 173 and connected to the drain region 155 through the second contact hole 162.

A second interlayer insulating layer 602 is formed on the first interlayer insulating layer 601 including the drain electrode 175 and the data line 171. The second interlayer insulating layer 602 has a third contact hole 163 exposing the drain electrode 175.

The pixel electrode 190 connected to the drain electrode 175 is formed on the second interlayer insulating layer 602 through the third contact hole 163. An alignment layer 11 is formed on the pixel electrode 190, and the alignment layer 11 is rubbed.

A method of manufacturing the thin film transistor array panel according to the first embodiment of the present invention described above will be described in detail with reference to FIGS. 1 and 2 described above with reference to FIGS. 3 to 7B.

3 is a cross-sectional view at an intermediate stage of manufacturing a thin film transistor array panel according to a first exemplary embodiment of the present invention, FIG. 4A is a layout view at a next stage of FIG. 3, and FIG. 4B is a line IVb-IVb ′ of FIG. 4A. FIG. 5 is a cross-sectional view taken along the line of FIG. 4B, FIG. 6A is a layout view at the next step of FIG. 5, FIG. 6B is a cross-sectional view taken along the line VIb-VIb ′ of FIG. 6A, and FIG. 7A Is a layout view in the next step of FIG. 6A, and FIG. 7B is a cross-sectional view taken along the line VIIb-VIIb ′ of FIG. 7A.

First, as shown in FIG. 3, the blocking layer 111 is formed on the transparent insulating substrate 110. In this case, glass, quartz, sapphire, or the like may be used as the transparent insulating substrate 110, and the blocking layer is formed by depositing silicon oxide (SiO ₂ ) or silicon nitride (SiNx) to a thickness of about 1,000 GPa. Subsequently, impurities such as a native oxide film on the blocking film 111 are removed by cleaning.

Next, an amorphous silicon film which is not doped with impurities is formed to a thickness of 400 to 1,200 kPa by a method such as chemical vapor deposition. Then, the amorphous silicon film is polycrystallized using joule heating. The row of rows satisfies Equation 1, which is proportional to the width L of the predetermined portion, the time t, and the square of the current I, and inversely proportional to the length W of the predetermined portion.

Therefore, when a constant current flows through a predetermined region of the amorphous silicon film, the amorphous silicon film is melted by the Joule heat generated in this portion. Thereafter, when the current no longer flows, the temperature of the amorphous silicon film is lowered to form the polycrystalline silicon film 501 by crystallizing the liquid amorphous silicon.

The amorphous silicon film has a resistance value of 2.3ⅹ1E5 (ohm / cm) and melts at a temperature of 1,415 ° C. Therefore, it is possible to find the required row using Equation 1.

As such, the process of flowing a constant current through the amorphous silicon film may be repeated at uniform intervals for the entire amorphous silicon film. In addition, in the case of having a plurality of tips (Ti) 10 or bars for flowing a current, the entire amorphous silicon film can be crystallized at once.

Next, as shown in FIGS. 4A and 4B, the polycrystalline silicon film 501 is patterned by a photolithography process using a photomask to form a semiconductor layer 150 made of polycrystalline silicon.

An insulating material such as silicon nitride or silicon oxide is deposited on the semiconductor layer 150 by chemical vapor deposition to form a gate insulating layer 140. Thereafter, silver (Ag), copper (Cu), titanium (Ti), aluminum (Al), tungsten (W), or an alloy thereof is deposited on the gate insulating layer 140 to form a metal film.

After the photoresist is coated on the metal layer, the photoresist layer is patterned by a photo process using a photomask to form the photoresist pattern PR. The gate layer 121 and the storage electrode line 131 are formed by wet or dry etching the metal layer by an etching process. At this time, the metal film is over-etched to form a width of the gate line 121 and the storage electrode line 131 smaller than that of the photoresist pattern PR.

Side surfaces of the gate line 121 and the storage electrode line 131 are formed to be tapered to increase adhesion to the upper layer. If the storage capacitor is sufficient, the storage electrode line 131 is not formed.

Thereafter, the semiconductor layer 150 is doped with a high concentration of conductive impurities using the photoresist pattern PR as a mask to form source and drain regions 153 and 155.

Next, as shown in FIG. 5, after the photoresist pattern PR is removed, the semiconductor layer 150 is lightly doped with a conductive dopant in a low concentration doping region 152 using the gate line 121 and the storage electrode line 131 as a mask. The semiconductor layer 150 having () is completed. When the gate line 121 is not formed of a high heat resistant and high chemical material such as titanium, an impurity may be doped after forming the photoresist pattern PR to reduce damage to the wiring.

The lightly doped region 152 may be formed by using metal layers having different etching ratios in addition to the photoresist pattern PR as described above, or by forming spacers or the like on sidewalls of the gate line 121.

In addition, the semiconductor layer 150A may be exposed to the outside of the storage electrode lines 131 and 133 because of the difference in length and width of the semiconductor layer 150 and the storage electrode lines 131 and 133. These regions are also doped, adjacent to the sustain electrode region 157 and separated from the drain region 155.

6A and 6B, a first interlayer insulating layer 601 is formed on the entire surface of the substrate 110 and etched by a photolithography process to expose the source and drain regions 153 and 155. The contact holes 161 and 162 are formed.

The first interlayer insulating film 601 has excellent planarization characteristics and is formed of an organic material having photosensitivity, a-Si: C: O, a-Si: formed by plasma enhanced chemical vapor deposition (PECVD). Low dielectric constant insulating materials, such as O: F, or silicon nitride which is an inorganic material, etc. can be formed.

Next, tungsten, titanium, aluminum, or an alloy thereof is deposited on the first interlayer insulating film 601 in a single layer or a plurality of layers to form a metal film. Subsequently, the metal layer is patterned by a photolithography process, and the data line 171 and the drain electrode 175 having the source electrode 173 connected to the source region 153 and the drain region 155 through the contact holes 161 and 162, respectively. ).

Sidewalls of the data line 171 and the drain electrode 175 may be formed to be tapered to improve adhesion to the upper layer.

As shown in FIGS. 7A and 7B, a second interlayer insulating film 602 covering the data line 171 and the drain electrode 175 is formed. Thereafter, the second interlayer insulating layer 602 is patterned by a photolithography process to form a third contact hole 163 exposing the drain electrode 175. The second interlayer insulating film 601 may also be formed of the same material as the first interlayer insulating film 160.

1 and 2, a transparent conductive film such as indium zinc oxide (IZO), indium tin oxide (ITO), or the like is formed on the second interlayer insulating film, and then patterned and drained through the third contact hole 163. The pixel electrode 190 connected to the electrode 175 is formed. Then, the alignment layer 11 covering the pixel electrode 190 is formed and then rubbed.

When the second interlayer insulating layer 602 is formed of an organic material having a low dielectric constant, the pixel electrode 190 may overlap the data line and the gate line to improve the aperture ratio of the pixel region.

 Second Embodiment

8 is a layout view of a thin film transistor array panel for a liquid crystal display according to a second exemplary embodiment of the present invention, and FIG. 9 is a cross-sectional view taken along line IX-IX′-IX ″ of FIG. 8.

In Embodiment 2, the data connection part 171b and the pixel electrode 190 are formed on the same layer using the same material, and the pixel electrode 190 and the data connection part 171b are formed on the source and drain regions 153 and 155 of the semiconductor layer 150. ), Since the contact holes 161 and 162 for connecting to the plurality of holes are simultaneously formed, the number of masks can be reduced as compared with the first embodiment.

More specifically, as shown in FIGS. 8 and 9, the blocking layer 111 is formed on the transparent insulating substrate 110. A semiconductor layer including a source region 153, a drain region 155, and a channel region 154 formed of an intrinsic semiconductor between the conductive layer and the dopant having a high concentration of conductive impurities on the blocking layer 111. 150 is formed. Further, conductive impurities are doped at a lower concentration than the source and drain regions between the source region 153 and the channel region 154 and the drain region 155 and the channel region 154 of the semiconductor layer 150.

The gate insulating layer 140 is formed on the substrate 110 including the semiconductor layer 150. A gate line 121 extending in the horizontal direction is formed on the gate insulating layer 140, and a portion of the gate line 121 extends in the vertical direction to partially overlap the semiconductor layer 150, and overlaps the semiconductor layer 150. A portion of the gate line 121 is used as the gate electrode 124.

One end of the gate line 121 may be formed larger than the width of the gate line 121 to receive a scan signal from an external circuit (not shown).

In addition, the storage electrode line 131 is formed in the same layer with the same material as the gate line 121 so that the storage electrode line 131 is formed to be parallel to the gate line 121 and is positioned in parallel. A portion of the storage electrode line 131 overlapping the semiconductor layer 150 becomes the storage electrode 133, and the semiconductor layer 150 disposed under the storage electrode 133 becomes the storage electrode region 157.

The data metal piece 171a is formed at a distance from the gate line 121 and extends in a direction perpendicular to the gate line 121, and is formed on the same layer as the gate line 121. The data metal piece 171a is positioned between two adjacent gate lines 121 and is not connected to the gate line 121. In addition, the data metal piece 171a may enlarge and form one end of the data metal piece 171a in the outermost row in order to receive an image signal from an external circuit (not shown).

An interlayer insulating layer 160 is formed on the gate insulating layer 140 including the gate line 121 and the storage electrode line 131.

The data connection part 171b, the pixel electrode 190, and the contact auxiliary member 82 are formed on the interlayer insulating layer 160. The data connection part 171b is formed to cross the gate line 121 and the storage electrode line 131 in the vertical direction.

The data metal piece 171a is connected to the data connecting portion 171b through the third contact hole 163 formed in the interlayer insulating layer 160, and the data connecting portion 171b is connected to the source through the first contact hole 161. It is connected to the area 153. That is, the data metal pieces 171a separated by the data connection part 171b are connected across the gate line 121 and the storage electrode line 131. The pixel electrode 190 is connected to the drain region 155 through a second contact hole 162 formed over the interlayer insulating layer 160 and the gate insulating layer 140, and the contact auxiliary member 82 is interlayered. The fourth contact hole 164 formed in the insulating layer 160 is connected to one end of the gate line 121 and the data metal piece 171a, respectively.

The contact auxiliary member 82 is not essential to serve to protect adhesion between the end of the data line 171a and the external device and to protect them, and application thereof is optional. In particular, when the driving circuit is formed together with the thin film transistor in the display area, it is not formed.

A method of manufacturing the TFT panel according to the second embodiment of the present invention described above will be described in detail with reference to FIGS. 8 and 9 described above with reference to FIGS. 10 to 13B.

FIG. 10 is a cross-sectional view at an intermediate stage of manufacturing a thin film transistor array panel according to a second exemplary embodiment of the present invention, FIG. 11A is a layout view at a next stage of FIG. 10, and FIG. 11B is XIb-XIb′-XIb of FIG. 11A. 12 is a layout view at the next step in FIG. 11B, FIG. 13A is a layout view at the next step in FIG. 12, and FIG. 13B is along the line XIIIb-XIIIb'-XIIIb in FIG. 13A ". It is a cut section.

First, as shown in FIG. 10, the blocking layer 111 is formed on the transparent insulating substrate 110. In this case, glass, quartz, sapphire, or the like may be used as the transparent insulating substrate 110, and the blocking layer 111 is formed by depositing silicon oxide (SiO ₂ ) or silicon nitride (SiNx) to a thickness of about 1,000 GPa. . Subsequently, impurities such as a native oxide film on the blocking film 111 are removed by cleaning.

Next, an amorphous silicon film which is not doped with impurities is formed to a thickness of 400 to 1,200 kPa by a method such as chemical vapor deposition.

Then, the amorphous silicon film is crystallized by Joule heat to form a polycrystalline silicon film. The method of crystallizing the amorphous silicon film using Joule rows is the same as in the first embodiment.

11A and 11B, the polycrystalline silicon film is patterned by a photolithography process using a photomask to form a semiconductor layer 150 made of polycrystalline silicon.

The gate insulating layer 140 is formed by depositing an insulating material such as silicon nitride or silicon oxide on the semiconductor layer 150 by chemical vapor deposition. Thereafter, copper (Cu), silver (Ag), titanium (Ti), aluminum (Al), tungsten (W), or an alloy thereof is deposited on the gate insulating layer 140 to form a metal film.

After the photoresist is coated on the metal layer, the photoresist pattern PR is formed by a photo process using a photomask. The metal film is wet or dry etched by the etching process to form the gate line 121, the storage electrode line 131, and the data metal piece 171a. At this time, the metal film is over-etched to form a width of the gate line 121 and the storage electrode line 131 smaller than that of the photoresist pattern PR.

Side surfaces of the gate line 121, the storage electrode line 131, and the data metal piece 171a are formed to be tapered to increase adhesion to the upper layer. If the storage capacitor is sufficient, the storage electrode line 131 is not formed.

Thereafter, the semiconductor layer 150 is doped with a high concentration of conductive impurities using the photoresist pattern PR as a mask to form source and drain regions 153 and 155.

Next, as shown in FIG. 12, after the photoresist pattern PR is removed, the semiconductor layer 150 is lightly doped with a conductive dopant in a low concentration doping region 152 using the gate line 121 and the storage electrode line 131 as a mask. The semiconductor layer 150 having () is completed. When the gate line 121 is not formed of a high heat resistant and high chemical material such as titanium, an impurity may be doped after forming the photoresist pattern PR to reduce damage to the wiring.

The lightly doped region 152 may be formed by using metal layers having different etching ratios in addition to the photoresist pattern PR as described above, or by forming spacers or the like on sidewalls of the gate line 121.

In addition, the semiconductor layer 150A may be exposed to the outside of the storage electrode lines 131 and 133 because of the difference in length and width of the semiconductor layer 150 and the storage electrode lines 131 and 133. These regions are also doped, adjacent to the sustain electrode region 157 and separated from the drain region 155.

As shown in FIGS. 13A and 13B, the interlayer insulating layer 160 is formed of an insulating material on the entire surface of the substrate on which the source region 153, the drain region 155, and the channel region 154 are formed. The interlayer insulating layer 160 is an organic material having excellent planarization characteristics and a photosensitive property, a low dielectric constant insulating material such as a-Si: C: O, a-Si: O: F, or inorganic material formed by plasma chemical vapor deposition. It may be formed of silicon nitride or the like.

Thereafter, the first contact hole 161 exposing the source region 153, the second contact hole 162 exposing the drain region 155, and the data metal piece 171a are exposed on the interlayer insulating layer 160. The third contact hole 163 and the fourth contact hole 164 exposing one end of the data metal piece 171a are formed.

When the interlayer insulating film is formed of an organic material having photosensitivity, the contact hole may be formed only by a photographic process.

8 and 9, a conductive layer is formed of a transparent conductive material on the interlayer insulating layer 160 including the first to fourth contact holes 161 to 164, and then patterned to form a data connection part 171b. And the pixel electrode 190 and the contact assistant member 82.

The data metal piece 171a is connected to the data connector 171b through the third contact hole 163, and the data connector 171b is connected to the source region 153 through the first contact hole 161. The pixel electrode 190 is connected to the drain region 155 through the second contact hole 162, and the contact auxiliary member 82 is connected to the data metal piece 171a through the fourth contact hole 164. .

In this case, when the interlayer insulating layer 160 is formed of an organic material having a low dielectric constant, the pixel electrode 190 may overlap the gate line 121 and the data metal piece 171b to improve the aperture ratio of the pixel region.

After that, the alignment layer 11 is formed on the pixel electrode 190 and then rubbed.

Although the present invention has been described with reference to one embodiment shown in the accompanying drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Could be. Accordingly, the true scope of protection of the invention should be defined only by the appended claims.

Using the joule heat as in the present invention described above it is possible to crystallize the amorphous silicon without using expensive laser equipment can reduce the production cost.

1 is a layout view of a thin film transistor array panel for describing an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along the line II-II 'of FIG. 1,

3 is a cross-sectional view at an intermediate stage of manufacturing a thin film transistor array panel according to a first exemplary embodiment of the present invention.

4A is a layout view in the next step of FIG. 3,

4B is a cross-sectional view taken along the line IVb-IVb ′ of FIG. 4A;

5 is a cross-sectional view at the next step of FIG. 4B,

FIG. 6A is a layout view in the next step of FIG. 5;

FIG. 6B is a cross-sectional view taken along the line VIb-VIb ′ of FIG. 6A;

FIG. 7A is a layout view at the next step of FIG. 6A,

FIG. 7B is a cross-sectional view taken along the line VIIb-VIIb ′ of FIG. 7A;

8 is a layout view of a thin film transistor array panel for a liquid crystal display according to a second exemplary embodiment of the present invention.

9 is a cross-sectional view taken along the line IX-IX'-IX "of FIG. 8,

10 is a cross-sectional view at an intermediate stage of manufacturing a thin film transistor array panel according to a second exemplary embodiment of the present invention.

FIG. 11A is a layout view at the next step of FIG. 10;

FIG. 11B is a cross-sectional view taken along the line XIb-XIb′-XIb ″ of FIG. 11A;

12 is a layout view in the next step of FIG. 11B,

13A is a layout view at the next step of FIG. 12,

FIG. 13B is a cross-sectional view taken along the line XIIIb-XIIIb'-XIIIb ″ of FIG. 13A.

※ Explanation of symbols on main parts of drawing ※

110: insulated substrate 121: gate line

124: gate electrode 131: sustain electrode line

133 sustain electrode 140 gate insulating film

150: semiconductor layer 153: source region

154: channel region 155: drain region

171: data line 173: source electrode

175: drain electrode 190: pixel electrode

Claims (8)

Forming an amorphous silicon film on the insulating substrate, And crystallizing the amorphous silicon film using a Joule heat method. In claim 1, In the Joule heat method, melting the amorphous silicon film using Joule heat, Cooling the amorphous silicon film. In claim 2, The melting step is a crystallization method of generating a joule heat by applying a current to the amorphous silicon film. Forming a blocking film on the insulating substrate, Forming an amorphous silicon film on the blocking film, Applying a current to the amorphous silicon film to crystallize the amorphous silicon film to form a polycrystalline silicon film, Patterning the polycrystalline silicon film to form a semiconductor layer, Forming a gate insulating film to cover the semiconductor layer; Forming a gate line partially overlapping the semiconductor layer on the gate insulating layer; Forming a source region and a drain region by highly doping conductive type impurities in a predetermined region of the semiconductor layer, Forming a first interlayer insulating film to cover the gate line and the semiconductor layer; Forming a data line having a source electrode connected to the source region and a drain electrode connected to the drain region on the first interlayer insulating layer; Forming a second interlayer insulating film on the data line and the drain electrode; And forming a pixel electrode connected to the drain electrode on the second interlayer insulating layer. Forming a blocking film on the insulating substrate, Forming an amorphous silicon film on the blocking film, Applying a current to a predetermined region of the amorphous silicon film to crystallize the amorphous silicon film to form a polycrystalline silicon film, Patterning the polycrystalline silicon film to form a semiconductor layer, Forming a gate insulating film to cover the semiconductor layer; Forming a gate line and a data metal piece on which the semiconductor layer partially overlaps with the gate insulating film; Forming a source region and a drain region by highly doping conductive type impurities in a predetermined region of the semiconductor layer, Forming an interlayer insulating film to cover the semiconductor layer; Forming a data connection part connected to the source region and the data metal piece and a pixel electrode connected to the drain area on the interlayer insulating layer. The method of claim 4 or 5, And doping a conductive dopant at a lower concentration than the source and drain regions to form a low concentration doped region in the semiconductor layer. The method of claim 4 or 5, And the conductive impurity is a p-type or n-type semiconductor ion. The method of claim 4 or 5, The applying of the current is performed repeatedly at regular intervals with respect to the amorphous silicon film.