KR100343307B1 - A method for manufacturing a thin film transistor - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor and a method of manufacturing the same. The amorphous silicon layer 12 and the first gate insulating film 15 are successively deposited by the plasma CVD method on the insulating substrate 11 to form the first gate insulating film 15. ) Is processed together with the amorphous silicon layer 12 into an island shape, the second gate insulating film 16 and the metal wiring layer are deposited on the first gate insulating film 15, and the metal wiring layer is etched to form the gate electrode 17. After that, the second gate insulating film 16 and the first gate insulating film 15 are etched to pattern the gate insulating film, and the gate electrode 17 is used as a mask on the exposed portion of the amorphous silicon layer by the preceding process. Doping and laser irradiation are performed to polycrystallize this portion to form the source region 13 and the drain region 14 to reduce the resistance of the gate electrode wiring and to make the ohmic connection between the active layer and the source and drain electrodes. , Less mask number required in the manufacturing process, characterized in that the productivity is providing superior thin-film transistor and a method of manufacturing the same.

Description

Manufacturing method of thin film transistor {A METHOD FOR MANUFACTURING A THIN FILM TRANSISTOR}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a thin film transistor (TFT) used in a switching element of a liquid crystal display device and the like and a manufacturing method thereof. The present invention also relates to a structure of a thin film transistor array and an active matrix liquid crystal display device using the thin film transistor having the above structure.

BACKGROUND ART Active matrix liquid crystal display devices using twisted nematic liquid crystal (TN) liquid crystals have excellent characteristics such as large capacity and high density, and are widely used in television image displays and graphic displays.

In such an active matrix liquid crystal display device, in order to realize high contrast display without cross talk, a method of driving and controlling each pixel using a semiconductor switching element is employed. As the semiconductor switching element, a thin film transistor (TFT) in which a semiconductor active layer (channel, source, and drain regions) is formed of amorphous silicon on a glass substrate is used because of its transmissive display and relatively large area. .

As the structure of such an amorphous silicon TFT, an inverted staggered TFT in which a gate electrode is disposed below an amorphous silicon layer serving as an active layer, or a forward staggered TFT in which a gate electrode is disposed above an amorphous silicon layer is generally known.

Among these, the reverse staggered TFT is easy to obtain good transistor characteristics, but it is not easy to reduce the resistance of the gate electrode wirings (scanning lines) because the gate electrode is arranged under the amorphous silicon layer. When the TFT is applied to an active matrix liquid crystal display device, the lowest resistance among the components of the TFT is required to be gate electrode wiring, and this problem becomes serious as the LCD (liguid crystal device) is enlarged. In addition, in terms of productivity, in the case of the reverse staggered structure, since there are usually six or more photo masks, cost reduction is not easy.

On the other hand, in the forward staggered TFT, the gate electrode is disposed above the amorphous silicon layer (top gate type), and the source and drain electrodes are arranged in the amorphous silicon layer. The net staggered TFT can ultimately reduce the number of photomasks by two and is advantageous for productivity and manufacturing cost. In addition, since it is a top gate type, it is possible to use Al (aluminum) as a material of the gate electrode wiring, and to thicken easily.

However, this forward stagger structure also has the same problem as discussed below. First, it is difficult to make an ohmic contact between n ⁺ a-Si (n ⁺ amorphous silicon) formed on the source and drain electrodes and a-Si of the active layer, and it is not possible to obtain a sufficient ON current for the TFT. Though ideas such as performing a plasma treatment of PH _{3 on} the surface of the ITO before forming a-Si by using ITO (Indium Tin Oxide) on the source and drain electrodes have been proposed, the contamination of P on the subsequently formed a-Si layer is proposed. It is adversely affected by. In addition, since the overlap between the source and drain electrodes and the gate electrode becomes large, the parasitic capacitance between the gate and the source and between the gate and the drain becomes large.

U.S. Patent No. 4,727,044 discloses a method of manufacturing a top gate type TFT as follows. That is, an amorphous silicon layer is formed on the glass substrate, and a gate electrode is formed on the amorphous silicon layer through the gate insulating film. Next, using the gate electrode as a mask, ion doping and laser irradiation are performed on the amorphous silicon layer corresponding to the source and drain regions to crystallize the amorphous silicon layer of the region. The amorphous silicon layer of the portion masked by the gate electrode constitutes a channel. When the co-planar TFT employed in single crystal silicon (LSI), which is a type of top gate TFT, is manufactured using this process, the following process continues. The gate electrode and the source / drain regions are covered with an insulating protective film, and then contact holes are formed in the insulating protective film, and then source and drain electrodes are formed.

However, the TFT structure described in US Patent No. 4,727,044 as described above has a problem as discussed below.

First, when the application of the liquid crystal display device is considered, it is necessary to process the amorphous silicon layer into islands and to separate the semiconductor layer between adjacent TFTs. In this case, although the amorphous silicon layer is processed into an island shape before the gate insulating film is formed, it is difficult to clean the interface (channel interface) between the amorphous silicon layer and the gate insulating film, thereby obtaining a TFT having excellent mobility and reliability. Can not.

In addition, when ion doping an amorphous silicon layer corresponding to a source / drain region, an ion doping is performed to the amorphous silicon layer below the gate insulating film, so that a significantly high acceleration voltage is required. In addition, in the manufacturing process of single crystal silicon (LSI), ion implantation is usually performed through a gate insulating film. The ion implantation through the gate insulating film is attributable to the thin film thickness of the gate insulating film being 50 nm or less. On the other hand, the TFT used in the liquid crystal display device generally uses the interlayer insulating film between the scanning line and the signal line as a gate insulating film for process reduction, and the gate insulating film is used in view of ensuring insulation or reducing the capacitance at the intersection of the scanning line and the signal line. A thickness of about 200 to 500 nm is used. At this thickness, even if the acceleration voltage of ion doping is 100 kV, since ions do not reach the amorphous silicon layer, ion doping through the gate insulating film is practically impossible.

Crystallinity of the Amorphous Silicon Layer by Laser Irradiation The laser irradiation through the gate insulating film is likely to cause ablation in which the amorphous silicon is scattered due to the release of gas such as hydrogen from the amorphous silicon layer. In addition to the ablation, laser light interference by the insulating film on the amorphous silicon layer occurs, so that there is a problem that the intensity of the laser light incident on the amorphous silicon layer changes in response to the mismatch in the film thickness of the insulating film.

As described above, it is difficult to stably crystallize the amorphous silicon layer by laser irradiation through the gate insulating film.

The present invention has been made in view of the above circumstances, and an object of the present invention is to obtain a TFT in which the interface between the channel and the gate insulation is clean and exhibits good characteristics. An object of the present invention is to easily realize the low resistance of the gate electrode wiring (scanning line), to ensure the ohmic connection between the semiconductor active layer, the source electrode and the drain electrode, and to reduce the number of masks required in the manufacturing process. It is to provide a method and a structure for manufacturing a thin film transistor having excellent productivity.

1 is a cross-sectional view showing an example of the structure of a thin film transistor based on the present invention;

2 is a cross-sectional view showing another example of the structure of a thin film transistor based on the present invention;

3 is a cross-sectional view showing another example of the structure of a thin film transistor based on the present invention;

4A is a plan view showing an example of a structure of a thin film transistor array based on the present invention;

4B is a cross-sectional view of the A-A section of the thin film transistor array of FIG. 4A;

5A is a plan view showing another example of the structure of a thin film transistor array based on the present invention;

5B is a cross-sectional view of the A-A section of the thin film transistor array of FIG. 5A;

6A is a plan view showing another example of the structure of a thin film transistor array based on the present invention;

FIG. 6B is a sectional view taken along the line B-B of the thin film transistor array of FIG. 6A;

7 is a plan view showing another example of the structure of a thin film transistor array based on the present invention;

8 is a cross-sectional view showing another example of a thin film transistor structure according to the present invention;

9 is a cross-sectional view showing another example of a thin film transistor structure based on the present invention;

10 is a cross-sectional view of a liquid crystal display device using a thin film transistor according to the present invention;

11 is a sectional view showing another example of a thin film transistor structure based on the present invention;

12 is a cross-sectional view showing another example of a thin film transistor structure according to the present invention.

* Explanation of symbols for main parts of the drawings

11; Glass substrate 12: channel area

13 source region 14 drain region

15: first gate insulating film 16: second gate insulating film

17: gate electrode 18: source electrode

19: drain electrode 21, 31: insulating protective film

22, 32: pixel electrode 41: signal line

42: scanning line 43: first contact hole

51: lower capacitor electrode 53: second contact hole

56 shield electrode 61, 63 light blocking layer

62: insulating film 71, 77: polarizing filter

72, 74: alignment film 73: liquid crystal

75: counter electrode 76: glass substrate

Manufacturing Method of Thin Film Transistor

The manufacturing method of the thin film transistor based on this invention is the following process,

Depositing an amorphous silicon layer on the insulating substrate;

Depositing a first gate insulating film in a continuous process of depositing the amorphous silicon layer;

Patterning the amorphous silicon layer in an island shape together with a first gate insulating film;

Depositing a second gate insulating film on the first gate insulating film patterned in an island shape;

Depositing a metal conductor layer on the second gate insulating film;

Patterning the conductor layer to form a gate electrode; and

And doping the amorphous silicon layer with impurity ions using a gate electrode as a mask.

According to the manufacturing method of the thin film transistor of the present invention, the gate insulating film is composed of two layers of the insulating film of the first gate insulating film and the second gate, and the amorphous silicon layer, which is a semiconductor layer, is processed in an island shape simultaneously with the first gate insulating film, The whole is covered with the 2nd gate insulating film. By adopting such a process, the patterning process is not interposed between the deposition of the amorphous silicon layer and the deposition of the first gate insulating film, so that the amorphous silicon layer and the first gate insulating film are kept in a vacuum state in the same reaction chamber and continuously. As a result, it is possible to deposit by the plasma CVD (Chemical Vapor Deposition) method. As a result, it is easy to obtain a clean interface (channel interface) between the amorphous silicon layer and the gate insulating film, and a TFT having excellent characteristics in mobility, reliability, and the like can be manufactured.

In addition, since the amorphous silicon layer is processed in an island shape before forming the gate electrode, when forming the TFT array, the semiconductor layers are completely separated from each other between adjacent TFTs, so that no field TFT is formed.

The source and drain regions formed by using a gate electrode as a mask in a self-aligning manner are n + a-Si (n-type amorphous silicon) formed by conventional CVD because doping elements are sufficiently activated by polycrystallization by laser irradiation. Compared with, the electrical resistance is small. For this reason, sufficient ohmic contact can be ensured between a source region, a source electrode, and a drain region, and a drain electrode, respectively. As a result, it is possible to simultaneously realize improvement of TFT characteristics and reduction of parasitic capacitance in a TFT having a top gate structure using amorphous silicon as an active layer.

At least the second gate insulating film is removed by etching using the gate electrode as a mask before the step of doping the impurity ions. This enables ion doping of the amorphous silicon layer even at a low acceleration voltage.

Preferably, prior to the step of doping the impurity ions, the second gate insulating film and the first gate insulating film are removed by etching using the gate electrode as a mask to expose the surface of the amorphous silicon layer. If an insulating film is present on the amorphous silicon layer, the amorphous silicon layer is likely to cause ablation during laser irradiation. Therefore, it is preferable to expose the surface of the amorphous silicon layer before ion doping.

When silicon nitride is used as the gate insulating film, the same resist pattern as the etching of the gate electrode is used for the etching. At this time, when side etching is performed on the gate electrode, shorting is likely to occur between the gate electrode and the source / drain region, or the gate electrode which is formed into a shade shape causes shading during ion doping and laser irradiation to degrade TFT characteristics. There is this. Therefore, it is necessary to prevent side etching. In addition, it is necessary to employ an etching method having a high selectivity in order to leave the amorphous silicon layer on the lower layer side. As a method of satisfying both of these conditions, a reactive ion etching method using a mixed gas containing at least C, H and F, such as a mixed gas of CHF ₃ and O ₂ or a mixed gas of CF ₄ and H ₂ , is effective. Do.

Placement of Source and Drain Electrodes

In the manufacturing method of the thin film transistor based on this invention, a source electrode and a drain electrode can be arrange | positioned both the lower side and the upper side of a source region and a drain region, respectively.

In the former case, namely, when the source electrode is disposed between the source region and the insulating substrate and the drain electrode is similarly disposed between the drain region and the insulating substrate, the manufacturing process of the thin film transistor is as follows. Prior to the deposition of the amorphous silicon layer, the source electrode and the drain electrode are formed so that their spacing is wider than the width of the gate electrode formed in a subsequent step. After deposition of the amorphous silicon layer, the amorphous silicon layer is polycrystallized by ion doping and laser irradiation using the gate electrode as a mask. As a result, the channel length is determined in a self-aligning manner with respect to the gate electrode, and the source electrode is connected to the low resistance source region and the drain electrode is connected to the drain region.

In this case, it is particularly important to expose the surface of the amorphous silicon layer by etching the gate insulating film in the same pattern as the gate electrode before ion doping. The reason is that in order to connect the source electrode and the drain electrode to the bottom surface of the low-resistance polycrystalline silicon layer, it is necessary to deeply insert impurities during ion doping of the amorphous silicon layer.

As the material of the source electrode and the drain electrode, it is necessary to be a high melting point material that is low resistance and can withstand high temperatures during laser irradiation. In this respect, the MoW alloy and the MoTa alloy are preferred because they are materials that satisfy both requirements. In particular, MoW alloy is more preferable because of lower resistance than MoTa alloy.

In the latter case, that is, when the source electrode and the drain electrode are disposed above the drain region and the source region, the manufacturing process of the thin film transistor is as follows. After patterning the gate electrode, the second gate insulating film, and the first gate insulating film as in the case of the former, the amorphous silicon layer corresponding to the source region and the drain region is used as a mask and doped with impurity ions. After depositing a metal thin film on the above region, the amorphous silicon layer is heat treated and the metal thin film is removed by etching again. As a result, the surface of the amorphous silicon layer is metal silicided to form source and drain regions.

This manufacturing method aims to reduce the resistance of the region by forming metal silicide on the surface of the amorphous silicon layer in a region doped with impurity ions. Also in this case, it is possible to form a self-aligning TFT without degrading the current driving capability of the TFT, and sufficient ohmic contact is realized at the connection portions between the source region, the source electrode, the drain region, and the drain electrode, respectively. Therefore, the improvement of the TFT characteristic and the reduction of parasitic capacitance which were the subject of the conventional TFT of the top gate structure which used amorphous silicon as an active layer can be achieved simultaneously. As the metal forming the silicide, Mo, Ti or W is suitable.

Placement of Light Shields

Preferably, in the thin film transistor, a light shielding film made of an amorphous silicon carbide layer is disposed below the thin film transistor. In this case, an insulating film is further disposed between the insulating substrate and the amorphous silicon layer to arrange a light shielding film between the insulating substrate and the insulating film, or a light shielding film is directly disposed between the insulating substrate and the amorphous silicon layer. can do.

The idea of using an amorphous silicon film as a conventional light shielding film is known. However, since the amorphous silicon film has a low electrical resistance and is particularly conductive by light irradiation, there is an influence on the TFT characteristics such that the threshold voltage shifts due to a back gate effect caused by the light shielding film charge. In this invention, since the silicon carbide film (SiCx) is used as the light shielding layer, a light shielding film having a high photoresist of at least two stages and a high resistance can be obtained as compared with the amorphous silicon film. Since the silicon carbide film has a wider band gap than the amorphous silicon film, the light shielding ability is slightly inferior. However, by adjusting the content of C, a suitable film can be obtained.

Preferably, the semiconductor film forming the active layer is composed of two layers, the upper layer portion is made of amorphous silicon and the lower layer portion is made of SiCx, and the lower layer SiCx is used as the light shielding film. If the light shielding film is formed in this way, even if light is irradiated to the light shielding film, the life of the photo-generating carrier is short, so that it is possible to suppress the leakage current of the TFT to a problem-free level, thereby obtaining a TFT having excellent light resistance.

Structure of thin film transistor

An array substrate using the thin film transistor of the present invention as a switching element has the following configuration:

Insulating substrates;

An amorphous silicon layer formed in an island shape and two-dimensionally arranged on the insulating substrate, each amorphous silicon layer having a channel region and a source region and a drain region formed on both sides of the channel region;

A first gate insulating layer (plural) formed on the amorphous silicon layer to cover a channel region (plural):

A second insulating film (plural) formed on the first gate insulating film (plural);

A gate electrode (plural) formed on the second gate insulating film (plural);

A source electrode (plural) connected to the source region (plural);

A drain electrode (plural) connected to the drain region (plural);

Pixel electrodes (plural) arranged two-dimensionally on the insulating substrate, each pixel electrode being electrically connected to each source electrode;

A signal line (plural) formed integrally with the drain electrode (plural), and the signal line is arranged between the pixel electrodes (plural) adjacent to each other;

Scan lines (plural) formed integrally with the gate electrodes (plural), which are intersected with the signal lines (plural), are arranged on the upper layer side of the signal lines (plural) through the second gate insulating film (plural).

Further, in the thin film transistor array substrate, it is possible to arrange the source electrode and the drain electrode on both the lower side and the upper side of the source region and the drain region, respectively. In addition, it is possible to arrange the pixel electrodes on both the upper and lower layers of the source electrode and the drain electrode.

When the pixel electrode is disposed on the upper side of the source electrode and the drain electrode, an insulating protective film is deposited so as to cover the signal line (plural) and the scanning line (plural), and the pixel electrode (plural) is disposed on the insulating protective film. The pixel electrode (plural) is electrically connected to the source electrode (plural) through the first contact hole (plural) formed in the insulating protective film.

The thin film transistor array having the above structure is manufactured, for example, by the following procedure.

Arrange the signal lines on the insulating substrate. The drain electrode is integrally formed with the signal line in the same process as the signal line on the insulating substrate, and at the same time, the source electrode is formed on the insulating substrate. A thin film transistor having the above structure is formed on the drain electrode and the source electrode thus formed. In addition, the scan line is formed integrally with the gate electrode in the same process as the gate electrode. The second gate insulating film is also used as the interlayer insulating film between the scan line and the signal line. Next, an insulating protective film is deposited to cover the upper surfaces of the insulating substrate, the thin film transistor, the signal line, and the scan line. A first contact hole is formed in the insulating protective layer to expose a portion of the source electrode. A pixel electrode is formed in the upper surface of the insulating protective film and in a region corresponding to the upper portion of each region (pixel region) which is divided into a signal line and a scanning line. The pixel electrode is connected to the source electrode through the first contact hole.

In the case of the thin film transistor array having the structure in which such pixel electrodes are arranged on the upper layer side of the thin film transistor, it is possible to take a large aperture ratio of the LCD.

In the case of the structure in which the pixel electrode is disposed on the upper side of the source electrode and the drain electrode, the thin film transistor array is preferably configured as follows. That is, the lower capacitance electrode is formed on the insulating substrate in the same process as the signal line, and the pixel electrode is connected to the lower capacitance electrode through the second contact hole formed in the insulating protective film, and the storage capacitor is configured between the lower capacitance electrode and the scan line. do. In the above structure, the lower capacitor electrode is connected to the source electrode through the pixel electrode. In this way, by connecting both electrodes as a pixel electrode which is a transparent conductive thin film, the aperture ratio of the LCD can be made large.

In the case where the pixel electrode is disposed above the source electrode and the drain electrode, the thin film transistor array is preferably configured as follows. That is, the signal line is formed so that the edge portion of the pixel electrode overlaps the signal line through the insulating protective film, and the signal line functions as a black matrix. This eliminates the necessity of taking the margin of mask matching accuracy as compared with the case where the conventional black matrix is separately provided, so that the aperture ratio of the LCD can be made larger.

However, in the case where such a structure is simply used, the coupling capacitance of both may be excessive due to the overlap between the pixel electrode and the signal line. This coupling capacitance causes problems such as crosstalk to the LCD display. To solve this problem, a thin film transistor array is constructed as follows. That is, the shield electrode is disposed over the signal line through the second gate insulating film. The shield electrode can be formed integrally with the scan line in the same process as the scan line. The pixel electrode is formed such that its edge portion overlaps the shield electrode through the insulating protective film. As a result, the shield electrode functions as a black matrix and an auxiliary capacitance is formed between the shield electrode and the pixel electrode.

By interposing the shield electrode between the pixel electrode and the signal line in this way, the electric field is shielded and the potential variation of the signal line is prevented from affecting the pixel potential. In the thin film transistor having the above structure, the shield electrode can be used as the storage capacitor line formed in the same process as the scan line (and thus the gate electrode) or the scan line of the adjacent pixel, and the shield structure can be made without increasing the special process. Can be. The formation of the black matrix structure is preferably performed by overlapping the edge of the pixel electrode with the shield electrode, and in this case, it is preferable that the edge of the pixel electrode does not overlap the signal line from the viewpoint of yield.

In the case where the pixel electrode is made of ITO, the insulating protective film is preferably made of silicon oxide or silicon oxynitride.

In particular, when the edge of the pixel electrode made of ITO overlaps the signal line or when the edge of the pixel electrode made of ITO overlaps the shield electrode, the use of dry etching is preferable because high processing precision is required for the etching of ITO. Do. As a dry etching method of ITO, reactive ion etching using, for example, hydrogen iodide (HI) gas, hydrogen bromide (HBr) gas, and hydrogen chloride (HCI) gas is known, but when silicon nitride is used as the base, the most selective Even with good HI gas, the etching selectivity is only about 3, and the silicon nitride film is reduced. By using silicon oxide or silicon oxynitride as the base and using HI as the etching gas at the same time, a selectivity of about 10 can be obtained, and the film reduction of the protective film can be suppressed to an uninterrupted level, allowing dry etching of ITO. .

The thin film transistor array in which the pixel electrode is disposed below the source electrode and the drain electrode is manufactured by, for example, the procedure shown below.

First, a transparent conductive thin film (for example, ITO) is deposited on an insulating substrate, and then a metal thin film is deposited thereon. The metal thin film and the transparent conductive thin film are patterned at the same time to simultaneously form a signal line stacked on the transparent conductive thin film, a drain electrode integrated with the signal line, and a pixel electrode covered with the metal thin film. Next, a thin film transistor and a scanning line having the above structure are formed on these. After the insulating protective film is deposited thereon, the insulating protective film of the pixel electrode region is removed by etching, and the metal thin film of the region is etched and removed to form a source electrode. According to the above process, the number of patterning processes required to form the thin film transistor array can be reduced by one.

In addition, the simultaneous processing of the pixel electrode and the signal line is also possible as an inverted staggered TFT having a bottom gate structure and a conventional forward staggered TFT, but the inverse staggered TFT has a contact portion in the source / drain region n +. It is difficult to obtain good contact characteristics in such a system because ITO is connected to the a-Si layer. On the other hand, in the conventional forward staggered TFT, if the source / drain electrode surface is a metal film as described above, the fleece of PH ₃ is achieved. The effect of hemp treatment is small and it is also difficult to obtain good contact properties. On the other hand, in the thin film transistor having the structure of the present invention, since polycrystalline silicon formed by laser irradiation is used as a contact layer between the source electrode and the drain electrode, good contact can be easily obtained, and simultaneous processing between the pixel electrode and the signal line is achieved. Can be put to practical use.

EMBODIMENT OF THE INVENTION Hereinafter, various embodiment of this invention is described based on drawing.

(Example 1)

1 and 2 are sectional views showing an example of the structure of a thin film transistor based on the present invention. The manufacturing method and structure of this thin film transistor will be described below.

The amorphous silicon layer 12 having a thickness of 0.1 탆 was deposited on one main surface of the insulating substrate made of glass (1737 manufactured by Corning Corporation) 11 by plasma CVD, and continuously plasma was maintained in the same reaction chamber in a vacuum state. The silicon nitride layer 15 (first gate insulating film) having a thickness of 0.05 mu m is deposited by the CVD method. Next, the amorphous silicon layer 12 is patterned in an island shape by photolithography with the silicon nitride layer 15 on the upper side thereof. A silicon nitride layer 16 (second gate insulating film) having a thickness of 0.35 mu m is deposited as if covering these upper portions. On the silicon nitride layer 16, Al having a thickness of 0.3 mu m and Mo having a thickness of 0.1 mu m are sequentially stacked and patterned by photolithography to form a gate electrode 17.

Next, the silicon nitride films 16 and 15 are etched using the same resist patterning used for etching the gate electrode 17 to complete the gate insulating film. At the same time, the amorphous silicon layers 13 and 14 corresponding to portions not covered with the gate electrode 17 are exposed. After exfoliation of the resist pattern, phosphorus (P) is doped into the amorphous silicon layers 13 and 14 using the gate electrode 17 as a mask. This ion doping is carried out by a method in which the ion species generated by plasma decomposition of the PH ₃ gas diluted by 5% with H ₂ is accelerated by an electric field and placed in an amorphous silicon layer without mass separation. In addition, if the mass separation is not performed in this manner, the processing of the large-area substrate becomes easy.

Next, examine the XeCl excimer laser from the top. In addition, other excimer lasers, such as ArF, KrF, and XeF, a YAG laser, an Ar laser, etc. can also be used for laser irradiation. Since the gate electrode 17 is used as a mask, only the amorphous silicon layer of the exposed portion, that is, the portion doped with P, is crystallized, whereby P is activated to change into low-resistance N-type polycrystalline silicon. As a result, the source region 13 and the drain region 14 are formed so as to self-align with the gate electrode. As described above, a thin film transistor based on the present invention is produced.

In addition, the distribution of the thicknesses of the first gate insulating film 15 and the second gate insulating film 16 constituting the gate insulating film has an appropriate range. First, the lower limit of the first gate insulating film is about 5 nm in terms of TFT characteristics. In consideration of the step of patterning in an island shape at the same time as the amorphous silicon layer, too thick is difficult to control the shape, so the upper limit is preferably about the film thickness of the amorphous silicon layer. On the other hand, since the thickness of the second gate insulating film needs to cover the upper portion of the amorphous silicon layer and the first gate insulating film processed into island shapes, the thickness of the second gate insulating film is preferably equal to or greater than the total film thickness of the amorphous silicon layer and the first gate insulating film. .

In addition, when etching the second gate insulating film 16 and the first gate insulating film 15 after patterning the gate electrode 17, the first gate insulating film 15 must be completely provided if the matching with the subsequent process is achieved. There is no need to remove it. That is, as shown in FIG. 2, you may etch so that a part of 1st gate insulating film 15 may remain.

As described above, by using Al in which a barrier metal is laminated on the gate electrode 17, the resistance of the gate electrode wiring (scanning line) can be reduced, and a large LCD can be manufactured. One purpose of stacking a barrier metal (Mo in this example) on top of Al is to block the injection of hydrogen into the channel region in a subsequent ion doping process. Injecting hydrogen into the amorphous silicon layer in the channel portion causes deterioration of TFT characteristics. Another object is to prevent the occurrence of hillock in Al in thermal processes such as laser irradiation or insulating protective film deposition. Therefore, as the material of the barrier metal, W and Ta having high melting point and high density besides Mo are suitable. W is most suitable because of its maximum melting point and density. The thickness of the barrier metal is suitably in the range of 0.03 to 0.2 占 퐉 in consideration of heat resistance, ion block performance, and shape controllability during lamination film processing.

As for the ion doping and laser irradiation procedures, the activation rate of the ions increases when the laser irradiation is performed after ion doping as in the above embodiment, whereas the ion silicon is subjected to the ion irradiation after the laser irradiation. Fluctuations are unlikely to occur. Therefore, the latter may be preferable in consideration of the process window in mass production, but in the latter case, it is necessary to adjust the acceleration voltage and the dose so that the polycrystallized source and drain regions do not recrystallize by ion doping.

Example 2

3 is a cross-sectional view showing an example in which a source electrode and a drain electrode are connected to a thin film transistor having the above structure. In this example, the source electrode 18 and the drain electrode 19 are disposed below the source region 13 and the drain region 14, respectively.

The structure shown in FIG. 3 is manufactured as follows. On one main surface of the glass substrate 11, first, a Mo-W alloy is deposited and patterned by photolithography to form a source electrode 18 and a drain electrode 19. The gap between the two electrodes is formed to be wider than the width (gate length) of the gate electrode 17 formed in the subsequent step, and smaller than the width of the island-shaped amorphous silicon layer formed in the subsequent step. On this, a thin film transistor is formed in accordance with the above-described manufacturing method. Using the gate electrode 17 as a mask, ion doping and laser irradiation are performed on the amorphous silicon layer to form the source region 13 and the drain region 14 of the thin film transistor. At this time, a low resistance polycrystalline silicon layer constituting the source region 13 and the drain region 14 is connected to the source electrode 18 and the drain electrode 19 arranged on the lower side.

As described above, in the case of the structure in which the source electrode 18 and the drain electrode 19 are disposed on the lower layer side of the source region 13 and the drain region 14, a dopant (P in this example) is formed of an amorphous silicon layer. Since it is necessary to insert deeply in the film thickness direction of (12), 50-80 kV is suitable as an acceleration voltage at the time of ion doping.

Example 3

4A and 4B show an example of the structure of a thin film transistor array using the thin film transistor (FIG. 3) of the present invention as a switching element. 4A is a plan view, and FIG. 4B is a sectional view taken along the line A-A. In this example, the pixel electrode 32 is disposed in the layer on the lower side than the thin film transistor.

ITO is deposited on one main surface of the glass substrate 11, and a Mo-W alloy layer is deposited on the upper surface thereof, and then patterned by photolithography to form the drain electrode 19 and the signal line 41 integral with the drain electrode. And a pixel electrode 32. Further, the drain electrode 19 and the signal line 41 are formed on the ITO layer, and the upper surface of the pixel electrode 32 is covered with the Mo-W alloy layer in this step. A thin film transistor is formed thereon according to the above-described manufacturing method (Example 2). The scan line 42 is formed integrally with the gate electrode 17 at the same time as the gate electrode 17. Next, the entire surface is covered with an insulating protective film 31 (for example, silicon nitride) and patterned by photolithography so that the insulating protective film on the upper surface of the pixel electrode 32 is rimmed and the source electrode 18. Remove the top of). Next, the Mo-W film on the pixel electrode 32 is removed by etching with the edge portion 18a and the source electrode 18 removed.

As described above, the thin film transistor array shown in FIGS. 4A and 4B is obtained. In the above process, the number of masks of photolithography is four in total.

(Example 4)

5A and 5B show another example of the structure of a thin film transistor array using the thin film transistor (FIG. 3) of the present invention as a switching element. FIG. 5A is a plan view and FIG. 5B is a sectional view taken along the line A-A. In this example, the pixel electrode 22 is disposed above the thin film transistor.

First, a thin film transistor is formed on one main surface of the glass substrate 11 according to the above-described manufacturing method (Example 2). In addition, the signal line 41 is formed integrally with the drain electrode at the same time as the drain electrode 19, and the scan line 42 is formed integrally with the gate electrode at the same time as the gate electrode 17. Next, the entire surface is covered with an insulating protective film 21 made of silicon nitride and patterned by photolithography to provide a contact hole 43 (first contact hole), thereby partially removing the surface of the source electrode 18 of the thin film transistor. Expose After ITO is deposited thereon by sputtering, it is patterned and the pixel electrode 22 is formed. The pixel electrode 22 is connected to the source electrode 18 through a contact hole 43 provided in the insulating protective film 21.

Since the TFT array having the above structure is arranged in different layers through the second gate insulating film 16 or the insulating protective film 21, the signal line 41, the scanning line 42, and the pixel electrode 22 are mutually arranged. The probability of shorting becomes small, so that the distance between the signal line 41 and the pixel electrode 22 and the distance between the scanning line 42 and the pixel electrode 22 can be made small. Therefore, it is possible to manufacture LCD with a large aperture ratio with good yield.

In the manufacturing process, the number of masks of photolithography is five in total.

(Example 5)

6A and 6B show another example of the structure of a thin film transistor array using the thin film transistor (FIG. 3) of the present invention as a switching element. 6A is a plan view and FIG. 6B is a sectional view taken along the line B-B. Also in this example, the pixel electrode 22 is disposed in the layer on the upper side than the thin film transistor.

In this example, the lower capacitor electrode 51 is disposed below the scan line 42 so that the scan line 42 faces through the second gate insulating film 16. Other structures are the same as those of the TFT array shown in FIG.

6A and 6B, the lower capacitance electrode 51 forming the auxiliary capacitance is formed in the same process as the signal line 41, the drain electrode 19, and the source electrode 18. In addition, the scanning lines 42 of adjacent pixels also function as upper capacitor electrodes.

In the insulating protective film 21 covering the thin film transistor, two openings are formed in each pixel, that is, the first contact hole 43 and the second contact hole 53. The source electrode 18 and the pixel electrode 22 are connected through the first contact hole 43, and the pixel electrode 22 and the lower capacitor electrode 51 are connected through the second contact hole 53.

In addition, the edge portion of the pixel electrode 22 is disposed so as to overlap the signal line 41 through the insulating protective film 21, so that the signal line 41 functions as a black matrix. By adopting such a structure, it is unnecessary to provide a dedicated black matrix on the signal line side, and it becomes possible to make the effective portion of the boundary of the signal line 41 an effective display area, thereby increasing the aperture ratio of the LCD.

(Example 6)

7 shows another example (top view) of the structure of a thin film transistor array using the thin film transistor (FIG. 3) of the present invention as a switching element.

In this example, the shield electrode 56 is disposed to face the signal line 41 on the upper side of the signal line 41 through the second gate insulating film 16 (FIG. 6B).

The shield electrode 56 is arranged such that the edge portion of the pixel electrode 22 overlaps the shield electrode 56 via the insulating protective film 21 (FIG. 6B). The shield electrode 56 is formed integrally with the scan line simultaneously with the scan line 42. Other structures are the same as those of the TFT array shown in Figs. 6A and 6B.

In this example, the shield electrode 56 functions not only as an upper capacitance electrode for forming the storage capacitor but also as a black matrix because the shield electrode 56 is disposed so as to overlap the edge portion of the pixel electrode 22. It is functioning. In addition, the shield electrode 56 has an electric field shielding effect, and prevents the potential variation of the signal line 41 from affecting the pixel electrode 22. Therefore, the shield electrode 56 has a coupling effect between the signal line 41 and the pixel electrode 22. It is possible to prevent the deterioration of display performance resulting from the LCD with a high aperture ratio.

In this example, the insulating protective film 21 is made of silicon oxide, and the pixel electrode 22 is formed by dry etching of ITO using HI.

(Example 7)

8 shows an example in which a light blocking layer is provided on the lower layer side of the thin film transistor (FIG. 3) of the present invention.

In this example, the light blocking layer 61 is disposed on the glass substrate 11, an insulating film 62 is formed thereon, and the thin film is formed on the light blocking layer 61 through the insulating film 62. The transistor is arranged.

The light blocking layer 61 is made of amorphous silicon carbide (SiCx), and is deposited by a plasma CVD method similarly to an amorphous silicon layer. As a source gas, it is common to use a mixed gas of SiH ₄ , CH ₄ , H ₂ . The C / Si composition ratio in SiCx is controlled by adjusting the flow rates of CH ₄ and SiH ₄ .

Even when a small amount of C is added, the photoconductivity of the SiCx layer is inferior, so that the bandgap of SiCx is adjusted to be 0.05 to 0.20 eV higher than that of amorphous silicon. Specifically, when the band gap of amorphous silicon is 1.75 eV, the band gap of SiCx may be about 1.80 to 1.95 eV. In addition, C / Si composition ratio in SiCx is about 1-10 at%. SiCx is processed into island shapes to block the light leakage path of the thin film transistor, and is covered thereon with an insulating film made of, for example, silicon nitride or silicon oxide.

(Example 8)

9 shows another example in which a light blocking layer is provided in the thin film transistor (FIG. 3) of the present invention.

In this example, a light blocking layer 63 made of amorphous silicon carbide (SiCx) is formed on the glass substrate 11, and a thin film transistor is directly formed thereon. That is, the semiconductor active layer has a two-layer structure of SiCx and amorphous silicon, and the lower layer functions as a light blocking layer 63, and the channel region 12 and the source region 13 of the thin film transistor are disposed on the amorphous silicon layer on the upper layer side. And a drain region 14 are formed.

Preferably, these layers are deposited by plasma CVD continuously while maintaining the vacuum in order to obtain a clean interface between the SiCx layer and the amorphous silicon layer. Specifically, the SiCx layer and the amorphous silicon layer are continuously deposited only by switching the source gas (for example, on / off of CH ₄ gas) while maintaining the plasma discharge. The composition of SiCx is the same as in the example (Example 7) shown above.

In the structure in which the amorphous silicon layer is laminated on the SiCx layer 63 as described above, the thinner the amorphous silicon layer, the lower the light leakage current of the TFT. However, if the thickness is too thin, the mobility of the TFT decreases due to the bending of the band in the defect level of the SiCx layer. Therefore, the film thickness of the amorphous silicon layer is 10 nm or more and 50 nm or less, preferably 15 nm or more and 30 nm or less.

(Example 9)

10 is a cross-sectional view of a transmission light type liquid crystal display device using the thin film transistor (FIG. 3) of the present invention.

The counter substrate is composed of a glass substrate 76, a counter electrode 75, an alignment film 74, a polarization filter 77, and the like. On the inner surface side of the glass substrate 76, a counter electrode 75 made of ITO is formed, and the surface of the counter electrode 75 is covered with an alignment film 74 made of a low temperature cure polyimide, and the glass substrate 76 The polarization filter 77 is attached to the outer surface side.

On the other hand, the array substrate is a thin film transistor array (consisting of the glass substrate 11, the gate electrode 17, the source electrode 18, the drain electrode 19, the pixel electrode 22, etc.) of the present invention, the alignment film 72 ) And a polarization filter 71 or the like. The surface of the pixel electrode 22 is covered with an alignment film 72 made of low temperature cure polyimide, and a polarizing filter 71 is attached to the outer surface side of the glass substrate 11.

The array substrate and the opposing substrate are arranged to face each other, and the liquid crystal 73 is enclosed therebetween. Further, the alignment films 72 and 74 are subjected to an alignment process so that the alignment directions are perpendicular to each other.

As the insulating protective film 21 disposed below the pixel electrode 22, a transparent organic insulating film is used. As described above, since the coupling capacitance between the signal line 41 (Fig. 5A) and the pixel electrode 22 degrades the display characteristics of the liquid crystal display element, it is necessary to reduce the coupling capacitance small. Therefore, it is preferable to apply a transparent organic insulating film having a dielectric constant of 4 or less to a thickness of 1 µm or more. Specifically, an acrylic resin, a polyimide resin, a benzocycloheptene resin, or the like can be used, and if it is photosensitive like a photoresist, processing is easy. Further, in order to improve the protective function of the TFT, an inorganic insulating film such as silicon nitride is further laminated on this organic insulating film.

It is also possible to color this organic protective film to form a color filter.

In this case, it is possible to have a function of a color filter on the array substrate side, which is advantageous when manufacturing a high aperture ratio LCD at low cost.

Example 10

11 is a cross-sectional view showing another example of the structure of a thin film transistor based on the present invention.

An amorphous silicon layer (amorphous silicon layer) 12 having a thickness of 0.1 탆 was deposited on one main surface of an insulating substrate made of quartz glass (1737 manufactured by Corning Corporation) 11 by plasma CVD, and vacuum was maintained in the same reaction chamber. While maintaining, the silicon nitride layer 15 (first gate insulating film) having a thickness of 0.05 µm was deposited continuously by plasma CVD. Amorphous silicon 12 is patterned in an island shape by photolithography with the silicon nitride layer 15 thereon. Next, a silicon nitride layer 16 (second insulating film) having a thickness of 0.35 mu m is deposited so as to cover these. A gate electrode 17 is formed by patterning by photolithography by sequentially laminating 0.3 μm thick Al and 0.1 μm thick Mo on the silicon nitride layer 16.

Next, the silicon nitride films 16 and 15 are etched using the same resist patterning used for etching the gate electrode 17 to form a gate insulating film, and at the same time not covered with the gate electrode 17. The corresponding amorphous silicon layers 85 and 86 are exposed. After exfoliation of the resist pattern, P is doped into the amorphous silicon layer using the gate electrode 17 as a mask.

Next, Mo is sputtered on the exposed amorphous silicon layer and heat-treated at 250 ° C. to form Mo silicide on the interface between the amorphous silicon layer and the Mo layer. Thereafter, when the Mo layer is removed by wet etching, Mo silicide remains on the surface layer portion of the amorphous silicon layer. As a result, the source region 85 and the drain region 86 are formed so as to self-align with the gate electrode. As described above, the thin film transistor of the present invention is produced.

(Example 11)

12 is a cross-sectional view showing an example in which the source electrode 88 and the drain electrode 89 are connected to the thin film transistor having the structure (Fig. 11).

The connection between the source electrode 88 and the drain electrode 89 is performed simultaneously with the formation of the source region 85 and the drain region 86 in the last step of the process of forming the thin film transistor on the glass substrate 11. That is, Mo silicide is formed on the interface between the amorphous silicon layer and the Mo layer by sputtering Mo on the exposed amorphous silicon layer and heat treatment at 250 ° C. Next, the Mo layer is patterned by wet etching to form the source electrode 88 and the drain electrode 89. Further, the gap between the two electrodes is formed to be wider than the width of the gate electrode 17 already formed and narrower than the island 12 of amorphous silicon. As a result, the source region 85 and the drain region 86 are formed so as to self-align with the gate electrode 17, and the source electrode 88 and the drain electrode 89 are formed.

The manufacturing method aims at reducing the resistance of the region by forming Mo silicide on the surface of the region doped with impurity ions in the amorphous silicon layer. In this case, it is possible to form a self-aligning TFT without degrading the current driving capability of the TFT, and at the connection portion of the source region 85 and the source electrode 88 and the drain region 86 and the drain electrode 89. Sufficient ohmic contact is realized in each case. As the metal forming the silicide, Ti or W is suitable in addition to Mo.

In the structure and manufacturing method of the thin film transistor of the present invention, the gate insulating film is composed of two layers of the first and second gate insulating films. A first gate insulating film is deposited on the amorphous silicon layer, which is a semiconductor active layer, and the amorphous silicon layer is processed into islands simultaneously with the first gate insulating film, and then the whole is covered with the second gate insulating film. By adopting such a process, the patterning process is not interposed between the deposition of the amorphous silicon layer and the deposition of the first gate insulating film (gate insulating film), so that the amorphous silicon layer and the first gate insulating film are kept in the vacuum in the same reaction chamber. It is possible to deposit continuously by the plasma CVD method. As a result, it is easy to obtain a clean interface between the amorphous silicon layer and the gate insulating film, and the mobility, reliability, and the like of the thin film transistor can be improved.

In addition, the source and drain regions formed in a self-aligning manner using the gate electrode as a mask are n + a-Si (n-type amorphous) formed by conventional CVD because doping elements are sufficiently activated by polycrystallization by laser irradiation. Compared with silicon), the electrical resistance is low, and sufficient ohmic contact can be formed between the source and drain regions and the source and drain electrodes, respectively.

As a result, the improvement of TFT characteristic and the reduction of parasitic capacitance which were the subject in the TFT of the top gate structure which used the conventional amorphous silicon for the active layer can be achieved simultaneously.

In addition, by etching the gate insulating film in the same pattern as the gate electrode in advance before ion doping, exposing the surface of the amorphous silicon layer, ion doping into the amorphous silicon layer is possible even at a low acceleration voltage.

In addition, since the surface of the amorphous silicon layer is exposed before the impurity ion doping, it is possible to prevent the amorphous silicon layer from causing ablation during laser irradiation after ion doping.

According to the manufacturing method of the thin film transistor of the present invention, the number of masks used in the manufacturing process is four to five when no light blocking layer is provided, and five to six when the light blocking layer is provided. The thin film transistor can be manufactured with fewer steps.

As described above, it is possible to manufacture a large LCD at low cost by the manufacturing method of the thin film transistor of the present invention.

In addition, the manufacturing method and structure of the thin film transistor of the present invention are not limited to an active matrix liquid crystal display device, but can be applied to an amorphous silicon adhesion sensor or the like.

Claims (1)

Depositing a semiconductor layer on a substrate, Forming a first gate insulating film in succession with depositing the semiconductor layer; Patterning the semiconductor layer in an island shape together with the first gate insulating film, Depositing a second gate insulating film on the first gate insulating film by covering an end portion of the island patterned semiconductor layer; Forming a gate electrode on the second gate insulating film, Removing the second gate insulating film and the first gate insulating film in a region not covered with the gate electrode and exposing the semiconductor layer; Doping impurity ions in the exposed region of the semiconductor layer, and And irradiating a laser to an exposed region of the semiconductor layer doped with the impurity ions.

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