KR20050068539A - Thin film transistor array panel, manufacturing method thereof, and liquid crystal display including the same - Google Patents

Abstract

An insulating substrate, a gate line formed on the insulating substrate, a gate insulating film pattern formed on the insulating substrate and overlapping with the gate line, a semiconductor pattern formed on the gate insulating film pattern in the same pattern as the gate insulating film pattern, and on the semiconductor pattern Formed in the pixel region formed by the intersection of the gate line and the data line, the data line including the data line, the source electrode and the drain electrode, and having the same pattern as the semiconductor pattern except for the channel portion. A thin film transistor array panel covering a pixel electrode and a data line and including an auxiliary data line formed of the same material as the pixel electrode.

Description

A thin film transistor array panel, a method of manufacturing the same, and a liquid crystal display including the same {THIN FILM TRANSISTOR ARRAY PANEL, MANUFACTURING METHOD THEREOF, AND LIQUID CRYSTAL DISPLAY INCLUDING THE SAME}

The present invention relates to a thin film transistor array panel, a method of manufacturing the same, and a liquid crystal display including the same.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two display panels on which a field generating electrode is formed and a liquid crystal layer interposed therebetween. It is a display device which controls the transmittance | permeability of the light which passes through a liquid crystal layer by rearranging.

Among the liquid crystal display devices, a field generating electrode is provided in each of two display panels. Among them, a liquid crystal display device having a structure in which a plurality of pixel electrodes are arranged in a matrix form on one display panel and one common electrode covering the entire display panel on the other display panel is mainstream. The display of an image in this liquid crystal display device is performed by applying a separate voltage to each pixel electrode. To this end, a thin film transistor, which is a three-terminal element for switching a voltage applied to a pixel electrode, is connected to each pixel electrode, and a gate line for transmitting a signal for controlling the thin film transistor and a data line for transmitting a voltage to be applied to the pixel electrode are provided. Install on the display panel.

Such a liquid crystal display panel has a layered structure in which a plurality of conductive layers and an insulating layer are stacked. The gate line, the data line, and the pixel electrode are made of different conductive layers (hereinafter referred to as gate conductors, data conductors, and pixel conductors, respectively) and separated into insulating layers, which are generally arranged in order from the bottom.

The thin film transistor array panel is manufactured through a film formation and photolithography process of a thin film over several layers, and the photolithography number of times represents a number of manufacturing processes. Therefore, how much stable the device is formed through the small number of photolithography processes is an important factor in determining the manufacturing cost.

SUMMARY OF THE INVENTION The present invention provides a thin film transistor array panel in which a conventional four mask or five mask process is simplified to a three mask process by forming column spacers in a channel portion of a thin film transistor array panel, a method of manufacturing the same, and a liquid crystal display including the same. will be.

The thin film transistor array panel according to the present invention includes an insulating substrate, a gate line formed on the insulating substrate, a gate insulating film pattern formed on the insulating substrate and overlapping with the gate line, and the gate insulating film pattern on the gate insulating film pattern. A semiconductor pattern formed in the same pattern as that of the semiconductor pattern, a data line including a data line, a source electrode, and a drain electrode formed on the semiconductor pattern and formed in the same pattern as the semiconductor pattern except for the channel portion; It is preferable to include a pixel electrode formed in the pixel region formed by crossing and covering the drain electrode, and an auxiliary data line covering the data line and made of the same material as the pixel electrode.

In addition, a column spacer is preferably formed on the auxiliary data line and the pixel electrode.

The display device may further include a gate contact assistant member and a data contact assistant member respectively connecting the ends of the gate line and the data line to an external circuit. A gate contact assistant member is formed on an end portion of the gate line. It is preferable that a data contact assistance member is formed on the portion.

In addition, the method of manufacturing a thin film transistor array panel according to the present invention includes the steps of forming a gate line on an insulating substrate, laminating a gate insulating film, a semiconductor layer and a data metal layer covering the gate line, the data metal layer, a semiconductor layer and a gate insulating film Patterning together to form a data metal pattern, a semiconductor pattern, and a gate insulating layer pattern, forming a pixel electrode and an auxiliary data line on the data metal pattern and the insulating substrate, and being exposed between the pixel electrode and the auxiliary data line. Etching the data metal pattern to form a data line including a data line, a source electrode, and a drain electrode, exposing a semiconductor layer between the source electrode and the drain electrode, and forming a column on the auxiliary data line and the pixel electrode. Forming a spacer Is recommended.

In addition, the column spacer preferably covers an exposed semiconductor layer between the source electrode and the drain electrode.

The gate insulating layer pattern may be formed by etching the gate insulating layer using the data metal pattern and the semiconductor pattern as an etch stop layer after forming the data metal pattern and the semiconductor pattern.

In addition, the liquid crystal display according to the present invention includes a first insulating film, a gate line formed on the first substrate, a gate insulating film pattern formed on the first substrate and overlapping with the gate line, and the gate insulating film pattern. A semiconductor pattern formed on the same pattern as the gate insulating layer pattern, a data line formed on the semiconductor pattern and including a data line, a source electrode, and a drain electrode formed on the same pattern as the semiconductor pattern except for a channel portion; A pixel electrode formed on the first substrate, the pixel region formed by the intersection of the gate line and the data line, covering the drain electrode, and covering the data line, and formed of the same material as the pixel electrode; A first indication comprising an auxiliary data line A second display panel disposed on the second substrate and spaced apart from the first substrate by a predetermined distance; a second display panel including a common electrode formed on the second substrate; and a liquid crystal layer formed between the first display panel and the second display panel. It is preferable to include.

In addition, a column spacer is preferably formed on the auxiliary data line and the pixel electrode.

Then, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

Hereinafter, a thin film transistor array panel and a method of manufacturing the same according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

First, a thin film transistor array panel according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1, 2A, and 2B.

1 is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention, and FIGS. 2A and 2B are cross-sectional views of the thin film transistor array panel of FIG. 1 taken along lines IIa-IIa 'and IIb-IIb', respectively.

1 to 2B, a plurality of gate lines 121 and a plurality of storage electrode lines 131 are formed on the insulating substrate 110.

The gate line 121 and the storage electrode line 131 mainly extend in the horizontal direction and are separated from each other. The gate line 121 transmits a gate signal, and a portion of each gate line 121 protrudes up or down to form a plurality of gate electrodes 124. The storage electrode line 131 receives a predetermined voltage such as a common voltage, and includes the storage electrode 137 formed by an extension extending upward or downward. One end portion 129 of the gate line 121 may be formed wider than the width of the gate line 121 to connect to an external circuit.

The gate line 121 and the storage electrode line 131 include a conductive film formed of a silver-based metal such as silver (Ag) or a silver alloy having a low resistivity, or an aluminum-based metal such as aluminum (Al) or an aluminum alloy. In addition to conductive films, chromium (Cr), titanium (Ti), tantalum (Ta), molybdenum (Mo) and alloys thereof with good physical, chemical and electrical contact properties with other materials, in particular ITO or IZO [see: Molybdenum-Tungsten (MoW) alloy] may have a multilayer film structure including another conductive film. An example of the combination of the lower layer and the upper layer is chromium / aluminum-neodymium (Nd) alloy.

Sides of the gate line 121 and the storage electrode line 131 are inclined, and the inclination angle is in a range of about 30-80 ° with respect to the surface of the substrate 110.

A gate insulating layer pattern 140 including silicon nitride (SiNx) is formed on the insulating substrate 110 on which the gate line 121 and the storage electrode line 131 are formed. The gate insulating layer pattern 140 is formed in substantially the same pattern except for portions corresponding to the data lines 171, 173, and 175 and the channel unit 154 which will be described later.

A plurality of linear semiconductor patterns 151 made of hydrogenated amorphous silicon (amorphous silicon is abbreviated a-Si) and the like are formed on the gate insulating layer pattern 140. The linear semiconductor pattern 151 is the same as the gate insulating layer pattern 140, and mainly extends in the vertical direction, except for the exposed portion 154 where the thin film transistor is located, the data line 171, the drain electrode 175, and the lower portion thereof. Has substantially the same planar shape as the ohmic contacts 161 and 165. However, the semiconductor pattern 151 may be formed between the source electrode 173 and the drain electrode 175 in addition to the portion of the data line 171 and the drain electrode 175 below the ohmic contacts 161 and 165. Has a portion exposed to them.

A plurality of linear and island ohmic contacts 161 and 165 formed of a material such as n + hydrogenated amorphous silicon in which silicide or n-type impurities are heavily doped is formed on the semiconductor pattern 151. It is. The linear contact member 161 has a plurality of protrusions 163, and an exposed portion 154 of the semiconductor pattern 151 is positioned between the protrusion 163 and the island contact member 165.

Side surfaces of the semiconductor pattern 151 and the ohmic contacts 161 and 165 are also inclined, and the inclination angle is 30-80 °.

Data lines including a plurality of data lines 171 and a plurality of drain electrodes 175 are formed on the ohmic contacts 161 and 165, respectively. The data lines 171, 173, and 175 are formed in the same pattern as the semiconductor pattern 151 except for the channel portion 154.

The data line 171 mainly extends in the vertical direction to cross the gate line 121 and transmit a data voltage. A plurality of branches extending from the data line 171 toward the drain electrode 175 forms a source electrode 173. The pair of source electrode 173 and the drain electrode 175 are separated from each other and positioned opposite to the gate electrode 124. The gate electrode 123, the source electrode 173, and the drain electrode 175 form a thin film transistor (TFT) together with the exposed portion 154 of the semiconductor 151, and a channel of the thin film transistor It is formed in the exposed portion 154 between the source electrode 173 and the drain electrode 175. One end portion 179 of the data line 171 may be formed wider than the width of the data line 171 to connect to an external circuit.

The data line 171 and the drain electrode 175 may also include a conductive film made of a silver metal or an aluminum metal. In addition to the conductive film, chromium (Cr), titanium (Ti), tantalum (Ta), and molybdenum (Mo) may be used. ) And other conductive films made of alloys thereof. Sides of the data line 171 and the drain electrode 175 are also inclined, and the inclination angle is in the range of about 30-80 ° with respect to the horizontal plane.

A plurality of pixel electrodes 190 made of ITO or IZO are formed on the pixel area defined by the gate line 121 and the data line 171 intersecting with each other.

The auxiliary data lines 191 are formed on the data lines 171, 173, and 175 in the same pattern. The auxiliary data line 191 may be formed of the same material as that of the pixel electrode 190. Therefore, the auxiliary data lines 191 on the source electrode 173 and the drain electrode 175 are separated by a predetermined interval.

In addition, the auxiliary gate line 192 is formed on the data metal pattern 176 that matches the gate line 121 formed to prevent the gate line 121 from being exposed when the entire surface of the gate insulating layer 140 is etched. .

A plurality of contact assistants 81 and 82 are formed on one end 129 of the gate line and one end 179 of the data line.

The thin film transistor array panel including the transparent pixel electrode 190 is used in a transmissive liquid crystal display device.

The pixel electrode 190 is physically and electrically connected to the drain electrode 175 to receive a data voltage from the drain electrode 175.

The pixel electrode 190 to which the data voltage is applied rearranges the liquid crystal molecules of the liquid crystal layer between the two electrodes by generating an electric field together with the common electrode 270 (see FIG. 9) of the upper panel.

In addition, the pixel electrode 190 and the common electrode 270 form a capacitor (hereinafter, referred to as a liquid crystal capacitor) to maintain the applied voltage even after the thin film transistor is turned off. Another capacitor is connected in parallel with the liquid crystal capacitor and is called a storage electrode. The storage capacitor is made of the overlap of the pixel electrode 190 and the storage electrode line 131 and the overlap of the pixel electrode 190 and the neighboring gate line 121 (which is referred to as a prior gate line). In order to increase the capacitance of the capacitor, that is, the storage capacitance, the storage electrode 137 which extends the storage electrode line 131 is placed to increase the overlap area. The storage electrode 177 is formed of the same material as the data wires 171, 173, and 175 overlapping the storage electrode 137 under the pixel electrode 190, and thus, between the pixel electrode 190 and the storage electrode line 131. You can also close the street.

The contact assisting member 82 is not essential to serve to protect adhesiveness between the end portion 179 of the data line 171 and an external device and to protect them, and application thereof is optional.

The gate contact auxiliary member 81 is formed directly on the end portion 129 of the gate line, and the data contact auxiliary member 82 is formed directly on the end portion 179 of the data line. The gate contact auxiliary member 81 is in direct contact with each other, and the end 179 of the data line and the data contact auxiliary member 82 are in direct contact with each other.

The contact auxiliary member 81 is required when a gate driving circuit (not shown) for supplying a signal to the gate line 121 is mounted on a display panel or a flexible circuit board (not shown) in the form of a chip. On the other hand, when the gate driving circuit is made of a thin film transistor or the like directly on the substrate 110, the contact auxiliary member 81 is not necessary.

A column spacer 320 made of an organic insulating material is formed on the pixel electrode 190 and the auxiliary data line 191. The column spacer 320 is formed to maintain a cell gap of the liquid crystal display.

The column spacer 320 protects the exposed portion 154 of the semiconductor layer by covering the exposed portion 154 of the semiconductor layer between the source electrode 173 and the drain electrode 175.

A method of manufacturing a thin film transistor array panel according to an exemplary embodiment of the present invention illustrated in FIGS. 1 to 2B will be described in detail with reference to FIGS. 3 to 8B.

First, as shown in FIGS. 3 to 4B, a metal such as chromium, molybdenum, aluminum, silver, or an alloy thereof is deposited on the transparent insulating substrate 110 by sputtering to form a single layer or a plurality of gate metal layers. do. Thereafter, the metal film is dry or wet etched by a photolithography process to form gate lines 121, 124, and 129 and sustain electrode lines 131 and 137 on the substrate 110. Sidewalls of these 121, 124, 129, 131, 137 are formed to be tapered during etching, and the tapered shape allows the layers formed thereon to be in close contact with each other.

Subsequently, as shown in FIGS. 5 to 6B, an insulating material such as silicon nitride covering the gate lines 121, 124, and 129 and the storage electrode lines 131 and 137 is deposited to form a gate insulating layer 140. In addition, an amorphous silicon without an impurity doped and an amorphous silicon doped with an impurity are deposited on the gate insulating layer 140 to form a semiconductor layer in which an amorphous silicon film not doped with an impurity and an amorphous silicon film doped with an impurity are sequentially stacked. The amorphous silicon film not doped with impurities is formed of hydrogenated amorphous silicon, and the like, and the amorphous silicon film doped with impurity is formed of amorphous silicon or silicide doped with a high concentration of n-type impurities such as phosphorus (P).

A metal such as aluminum, silver, chromium, molybdenum, or an alloy thereof is deposited on the amorphous silicon film doped with impurities successively by sputtering to form a single layer or a plurality of data metal layers.

Then, a photosensitive material is coated on the data metal layer to form a photoresist film, followed by exposure and development to form a photoresist pattern, followed by patterning the data metal layer and the semiconductor layer together to form the data metal pattern 171, 176, 177, and 179 and the semiconductor pattern ( 151 and 161 are formed.

The data metal pattern 176 is formed on a portion of the gate line 121 to prevent the gate line 121 from being exposed when the entire surface of the gate insulating layer 140 is etched.

The gate insulating layer 140 is etched entirely using the data metal patterns 171, 176, 177, and 179 and the semiconductor patterns 151 and 161 as etch stop layers to form a gate insulating layer pattern. In this case, one end portion 129 of the gate line 121 is exposed.

7 to 8B, a transparent conductive material such as ITO or IZO is deposited on the insulating substrate 110 to form the pixel electrode 190 connected to the drain electrode 175. That is, the pixel electrode 190 is formed in the pixel area defined by the gate line 121 and the data line 171 crossing each other.

An auxiliary data line 191 having a pattern substantially the same as that of the data metal pattern 171 is formed on the data metal pattern 171 extending in the vertical direction. That is, the auxiliary data line 191 is formed in the same manner except for a portion corresponding to the data metal pattern 171 and the channel portion 154 of the semiconductor pattern, which are formed to extend in the vertical direction.

The auxiliary data line 191 in which the portion corresponding to the channel portion 154 of the semiconductor pattern is etched exposes the data metal pattern 171 below.

At the same time, a contact auxiliary member 82 connected to one end 179 of the data line and a contact auxiliary member 81 connected to one end 129 of the gate line are formed.

In addition, the auxiliary gate line 192 may be formed on the data metal pattern 176 that matches the gate line 121 formed to prevent the gate line 121 from being exposed when the entire surface of the gate insulating layer 140 is etched. have.

The exposed data metal pattern 171 and the ohmic contact layer 161 are etched to expose the channel portion 154 of the semiconductor pattern.

The etching process for exposing the channel portion 154 of the semiconductor layer may be simultaneously performed while exposing the data metal pattern 171 corresponding to the channel portion 154 of the semiconductor pattern.

The linear ohmic contact 161 and the island-type ohmic contact 165 including the protrusion 163 and forming the data line 171 and the drain electrode 175 including the source electrode 173 by the above process. And a linear semiconductor 151 including an exposed portion 154.

The data wires 171, 173, and 175 may also be formed in a tapered form like the gate lines 121, 124, and 129 to increase adhesion to the upper layer.

Next, as shown in FIGS. 1 and 2B, an organic layer is stacked on the pixel electrode 190 and the auxiliary data line 191 so as to cover the channel portion 154 of the exposed semiconductor layer, and is exposed and developed to form a column. The spacer 320 is formed at a predetermined position on the auxiliary data line 191 and the pixel electrode 190.

 As described above, the photolithography process may be shortened by omitting the conventional passivation layer forming process and forming the column spacer 320 formed on the color filter display panel to protect the channel portion of the semiconductor layer.

FIG. 9 illustrates a liquid crystal display in which a color filter display panel on which a common electrode 270, a color filter 230, and a black matrix 220 are formed is attached to the thin film transistor array panel illustrated in FIGS. 1 to 2B.

As illustrated in FIG. 9, the gate line 121, the gate insulating layer pattern 140, the semiconductor patterns 151 and 154, and the data lines 171, 173, 175, 176, 177 and 179 are disposed on the first substrate 110. ) Is formed.

A plurality of pixel electrodes 190 made of ITO or IZO are formed on the pixel area defined by the gate line 121 and the data line 171 intersecting with each other.

The auxiliary data lines 191 are formed on the data lines 171, 173, and 175 in almost the same pattern. That is, the auxiliary data lines 191 on the source electrode 173 and the drain electrode 175 are separated by a predetermined interval. The auxiliary data line 191 may be formed of the same material as that of the pixel electrode 190.

A plurality of contact assistants 81 and 82 are formed on one end 129 of the gate line and one end 179 of the data line.

The column spacer 320 is formed on the auxiliary data line 191, the channel part 154 of the semiconductor layer, and the pixel electrode 190.

An alignment layer 11 that determines the alignment of the liquid crystal is formed on the pixel electrode 190 and the column spacer 320. The spacer 320 for maintaining the cell gap of the liquid crystal display device is formed on the alignment layer 11. A sealing material is formed on the edge of the thin film transistor array panel. The liquid crystal is injected into the sealing material of the thin film transistor array panel to form the liquid crystal layer 3.

The color filter display panel includes a second substrate 210 spaced apart from the first substrate 110 by a predetermined distance. The black matrix 220 is formed on the second substrate 210. The black matrix 220 is formed in a matrix to define a pixel area.

The color filter 230 is formed on the insulating substrate 210 and the black matrix 220. The transparent common electrode 270 is formed on the color filter 230. An over coat may be formed between the color filter 230 and the common electrode 270 to prevent the color filter from being damaged when the common electrode is formed.

And the alignment film 21 which determines the orientation of a liquid crystal is formed on the common electrode.

Although the preferred embodiments of the present invention have been described in detail above, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Accordingly, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concept of the present invention as defined in the following claims also fall within the scope of the present invention.

In the thin film transistor array panel according to the present invention, the column spacer formed on the color filter panel is formed in the channel portion of the thin film transistor array panel to protect the channel portion, thereby eliminating the protective film forming process, thereby simplifying the conventional 4 mask or 5 mask process to a 3 mask process. can do.

1 is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention.

2A and 2B are cross-sectional views of the thin film transistor array panel of FIG. 1 taken along lines IIa-IIa 'and IIb-IIb', respectively.

3, 5, and 7 are layout views at an intermediate stage in the method of manufacturing the thin film transistor array panel according to the exemplary embodiment illustrated in FIGS. 1 and 2B.

4A and 4B are cross-sectional views taken along lines IVa-IVa 'and IVb-IVb' of FIG. 3, respectively.

6A and 6B are cross-sectional views at the next stage of FIGS. 4A and 4B, respectively;

8A and 8B are cross-sectional views at the next stage of FIGS. 6A and 6B, respectively;

9 is a cross-sectional view of a liquid crystal display device in which a color filter display panel in which a common electrode, a color filter, and a black matrix are formed is attached to the thin film transistor array panel illustrated in FIGS. 1 to 2B.

Claims (8)

Insulation board, A gate line formed on the insulating substrate, A gate insulating pattern formed on the insulating substrate and overlapping the gate line; A semiconductor pattern formed on the gate insulating layer pattern in the same pattern as the gate insulating layer pattern; A data line formed on the semiconductor pattern and including a data line, a source electrode, and a drain electrode formed in the same pattern as the semiconductor pattern except for the channel portion; A pixel electrode formed in the pixel region formed by the intersection of the gate line and the data line and covering the drain electrode; An auxiliary data line covering the data line and formed of the same material as the pixel electrode Thin film transistor array panel comprising a. In claim 1, And a column spacer formed on the auxiliary data line and the pixel electrode. The method of claim 1 or 2, A gate contact auxiliary member and a data contact auxiliary member respectively connecting the ends of the gate line and the data line with an external circuit; And a gate contact assistant member formed on an end portion of the gate line, and a data contact assistant member formed on an end portion of the data line. Forming a gate line on the insulating substrate, Stacking a gate insulating film, a semiconductor layer, and a data metal layer covering the gate line; Patterning the data metal layer, the semiconductor layer, and the gate insulating film together to form a data metal pattern, a semiconductor pattern, and a gate insulating film pattern; Forming a pixel electrode and an auxiliary data line on the data metal pattern and the insulating substrate; The data metal pattern exposed between the pixel electrode and the auxiliary data line is etched to form a data line including a data line, a source electrode, and a drain electrode, and expose a semiconductor layer between the source electrode and the drain electrode. Steps, Forming a column spacer on the auxiliary data line and the pixel electrode Method of manufacturing a thin film transistor array panel comprising a. In claim 4, The column spacer covers the exposed semiconductor layer between the source electrode and the drain electrode. In claim 4, The gate insulating layer pattern may be formed by etching the gate insulating layer using the data metal pattern and the semiconductor pattern as an etch stop layer after forming the data metal pattern and the semiconductor pattern. First substrate, A gate line formed on the first substrate, A gate insulating layer pattern formed on the first substrate and overlapping the gate line; A semiconductor pattern formed on the gate insulating layer pattern in the same pattern as the gate insulating layer pattern; A data line formed on the semiconductor pattern and including a data line, a source electrode, and a drain electrode formed in the same pattern as the semiconductor pattern except for the channel portion; A pixel electrode formed on the first substrate and formed in a pixel region formed by the intersection of the gate line and the data line and covering the drain electrode; An auxiliary data line covering the data line and formed of the same material as the pixel electrode First display panel comprising a, A second display panel including a second substrate positioned above the first substrate and spaced apart from the first substrate, and a common electrode formed on the second substrate; And a liquid crystal layer formed between the first display panel and the second display panel. In claim 7, And a column spacer formed on the auxiliary data line and the pixel electrode.