KR20060091376A - Thin film transistor array panel and manufacturing method thereof - Google Patents

Abstract

A thin film transistor array panel according to the present invention includes a gate line and a sustain electrode formed on a substrate, a gate insulating film formed on the gate line and a sustain electrode, a semiconductor layer formed on the gate insulating film, and a data line formed at least partially on the semiconductor layer. At least partially formed over the semiconductor layer and over the drain electrode, the data line and the drain electrode, the protective film having a first contact hole for exposing at least a portion of the drain electrode, the protective film being formed over the protective film and having the first contact. A pixel electrode connected to the drain electrode through the hole, and formed on the same layer as the pixel electrode, and including a conductor for the sustain electrode separated from the pixel electrode and formed at a position overlapping with the sustain electrode; The conductors are connected to each other and the drain electrode Extension part may overlap the conductor for which the sustain electrode and the sustain electrode. Accordingly, the thin film transistor array panel and the method of manufacturing the same according to the present invention have an advantage of improving the storage capacitance by allowing the conductive capacitor and the storage electrode to overlap the extension portion of the drain electrode.

LCD, Holding Capacitance, Kickback Voltage

Description

Thin film transistor array panel and manufacturing method therefor {THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF}

1 is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention.

FIG. 2A is a cross-sectional view of the thin film transistor array panel of FIG. 1 taken along a line IIa-IIa ',

FIG. 2B is a cross-sectional view of the thin film transistor array panel of FIG. 1 taken along lines IIb-IIb 'and IIb'-IIb ";

3 is a layout view at an intermediate stage of a method of manufacturing the thin film transistor array panel shown in FIG. 1 according to an embodiment of the present invention;

FIG. 4A is a cross-sectional view of the thin film transistor array panel of FIG. 3 taken along line IVa-IVa '.

FIG. 4B is a cross-sectional view of the thin film transistor array panel of FIG. 3 taken along lines IVb-IVb 'and IVb'-IVb';

5 is a layout view of the next step of FIG. 3,

FIG. 6A is a cross-sectional view of the thin film transistor array panel of FIG. 5 taken along the line VIa-VIa ′.

FIG. 6B is a cross-sectional view of the thin film transistor array panel of FIG. 5 taken along lines VIb-VIb ′ and VIb′-VIb ″;

FIG. 7 is a layout view of the next step of FIG. 5;

FIG. 8A is a cross-sectional view of the thin film transistor array panel of FIG. 7 taken along the line VIIIa-VIIIa ′.

FIG. 8B is a cross-sectional view of the thin film transistor array panel of FIG. 7 taken along lines VIIIb-VIIIb 'and VIIIb'-VIIIb ", and FIG.

FIG. 9 is a layout view of the next step of FIG. 7;

FIG. 10A is a cross-sectional view of the thin film transistor array panel of FIG. 9 taken along the line Xa-Xa ′,

FIG. 10B is a cross-sectional view of the thin film transistor array panel of FIG. 9 taken along lines Xb-Xb 'and Xb'-Xb', and FIG.

11 is a diagram illustrating a drop in data voltage due to a kickback phenomenon.

12 is a layout view of a thin film transistor array panel according to another exemplary embodiment of the present invention.

FIG. 13 is a cross-sectional view of the thin film transistor array panel of FIG. 12 taken along the line XIII-XIII ′.

<Description of the symbols for the main parts of the drawings>

110: substrate 121, 129: gate line

124: gate electrode 140: gate insulating film

151 and 154: semiconductors 161 and 165: ohmic contact members

171 and 179: data line 173: source electrode

175: drain electrode 180p: protective film

180q: organic film 190: pixel electrode

81, 82: contact auxiliary member

The present invention relates to a thin film transistor array panel and a method of manufacturing the same.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two display panels on which a field generating electrode is formed and a liquid crystal layer interposed therebetween. It is a display device which controls the transmittance | permeability of the light which passes through a liquid crystal layer by rearranging.

Among the liquid crystal display devices, a field generating electrode is provided in each of two display panels. Among them, a liquid crystal display device having a structure in which a plurality of pixel electrodes are arranged in a matrix form on one display panel and one common electrode covering the entire display panel on the other display panel is mainstream. The display of an image in this liquid crystal display device is performed by applying a separate voltage to each pixel electrode. To this end, a thin film transistor, which is a three-terminal element for switching a voltage applied to a pixel electrode, is connected to each pixel electrode, and a gate line for transmitting a signal for controlling the thin film transistor and a data line for transmitting a voltage to be applied to the pixel electrode are provided. Install on the display panel.

Such a liquid crystal display panel has a layered structure in which a plurality of conductive layers and an insulating layer are stacked. The gate line, the data line, and the pixel electrode are made of different conductive layers (hereinafter, referred to as gate conductors, data conductors, and pixel conductors, respectively) stacked in turn and separated into insulating layers. The thin film transistor has three electrodes: a gate electrode made of a gate conductor and a source and drain electrode made of a data conductor. The source electrode and the drain electrode are usually connected to a semiconductor disposed below the drain electrode, and the drain electrode is connected to the pixel electrode through a hole formed in the insulating film.

The pixel electrode and the common electrode form a capacitor to maintain an applied voltage even after the thin film transistor is turned off. In order to enhance the voltage holding capability, another capacitor connected in parallel with the liquid crystal capacitor is provided, which is called a storage capacitor. In addition, the capacitance of the holding capacitor, that is, the holding capacitance, affects the kickback voltage and thus has a major influence on the image quality characteristics.

Such a storage capacitor is made by overlapping a pixel electrode and a storage electrode line, or by overlapping a pixel electrode and a neighboring gate line. At this time, the storage capacitance becomes larger as the width of the overlapping gate lines becomes wider, but the width of the gate lines cannot be expanded because the aperture ratio decreases.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a thin film transistor array panel and a method for manufacturing the same, which improve a storage capacitance without reducing an aperture ratio.

A thin film transistor array panel according to the present invention includes a gate line and a sustain electrode formed on a substrate, a gate insulating film formed on the gate line and a storage electrode, a semiconductor layer formed on the gate insulating film, and at least partially formed on the semiconductor layer. A passivation layer formed on at least a portion of the semiconductor layer, the drain electrode being separated from the data line, the passivation layer formed on the data line and the drain electrode, and having a first contact hole exposing at least a portion of the drain electrode; A pixel electrode formed on the passivation layer and connected to the drain electrode through the first contact hole, and formed on the same layer as the pixel electrode and separated from the pixel electrode and formed at a position overlapping with the storage electrode; Conductor for electrode And also, the sustain electrode and the conductor for the sustain electrodes is preferably that are connected to each other, expansion of the drain electrode portion overlaps a conductor for the sustain electrode and the sustain electrode.

In addition, it is preferable that an organic film is further formed between the protective film and the pixel electrode.

In addition, the semiconductor layer may have substantially the same planar shape as the data line and the drain electrode except for a portion positioned between the data line and the drain electrode.

In addition, the sustain electrode and the conductor for the sustain electrode are preferably made of the same material.

In addition, the sustain electrode and the conductor for the sustain electrode are preferably connected to each other through a second contact hole formed in the protective film.

In addition, the method of manufacturing a thin film transistor array panel according to the present invention includes the steps of forming a gate line and a sustain electrode on a substrate, laminating a gate insulating film on the gate line and the sustain electrode, forming a semiconductor on the gate insulating film, the Forming a drain electrode and a data line on the semiconductor and gate insulating layers, laminating a protective film and an organic layer on the data line and the drain electrode, and patterning the organic, protective and gate insulating layers to expose a portion of the drain electrode. Forming a first contact hole and a second contact hole exposing a portion of the sustain electrode, a pixel electrode connected to the drain electrode through the first contact hole, and a connection of the sustain electrode through the second contact hole Forming a conductive electrode conductor on the protective film; The conductive electrode conductor preferably overlaps the extension of the drain electrode.

In addition, the sustain electrode and the conductor for the sustain electrode are preferably made of the same material.

Then, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

Hereinafter, a thin film transistor array panel and a method of manufacturing the same according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

First, a thin film transistor array panel and a method of manufacturing the same according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1, 2A, and 2B.

1 is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention, and FIG. 2A is a cross-sectional view of the thin film transistor array panel of FIG. 1 taken along a line IIa-IIa ', and FIG. 2B is a thin film transistor array panel of FIG. 1. Is a cross-sectional view taken along lines IIb-IIb 'and IIb'-IIb ".

A plurality of gate lines 121 and a plurality of sustain electrodes 137 are formed on the insulating substrate 110. The gate line 121 and the storage electrode 137 are separated from each other.

Each gate line 121 includes a plurality of portions protruding upward and downward to form a plurality of gate electrodes 124 and an extended end portion 129 having a large area for connection with another layer or an external device. do. The sustain electrode 137 receives a predetermined voltage such as a common voltage.

The gate line 121 and the sustain electrode 137 may be formed of aluminum-based metal such as aluminum (Al) or aluminum alloy, silver-based metal such as silver (Ag) or silver alloy, or copper-based such as copper (Cu) or copper alloy. Metal, molybdenum-based metals such as molybdenum (Mo) or molybdenum alloy, chromium (Cr), titanium (Ti) or tantalum (Ta) or the like. The gate line 121 and the storage electrode line 131 may have a multilayer film structure including two films having different physical properties. One of these films is made of a low resistivity metal, for example, an aluminum-based metal, so as to reduce the signal delay or voltage drop of the gate line 121 and the sustain electrode 137. In contrast, the other membrane has a good physical, chemical and electrical contact with other materials, especially indium zinc oxide (IZO) or indium tin oxide (ITO), such as chromium, molybdenum and molybdenum alloys (eg molybdenum-tungsten). MoW) alloy], tantalum and titanium. Examples of the combination of the lower film and the upper film include a chromium lower film, an aluminum (alloy) upper film, an aluminum (alloy) lower film and a molybdenum upper film.

The side surface of the gate line 121 is inclined with respect to the surface of the substrate 110 and its inclination angle is about 30-80 degrees.

A gate insulating layer 140 made of silicon nitride (SiNx) is formed on the gate line 121.

A plurality of linear semiconductors 151 made of hydrogenated amorphous silicon (amorphous silicon is abbreviated a-Si) and the like are formed on the gate insulating layer 140. The linear semiconductor 151 mainly includes a plurality of projections 154 extending in the longitudinal direction and extending toward the gate electrode 124.

A plurality of linear and island ohmic contacts 161 and 165 made of a material such as n + hydrogenated amorphous silicon doped with silicide or n-type impurities at a high concentration are formed on the semiconductor 151. have. The linear contact member 161 has a plurality of protrusions 163, and the protrusions 163 and the island contact members 165 are paired and positioned on the protrusions 154 of the semiconductor 151.

Side surfaces of the semiconductor 151 and the ohmic contacts 161 and 165 are also inclined with respect to the surface of the substrate 110, and the inclination angle is about 30-80 °.

A plurality of data lines 171 and a plurality of drain electrodes 175 are formed on the ohmic contacts 161 and 165.

The data line 171 mainly extends in the vertical direction to cross the gate line 121 and transmit a data voltage. Each data line 171 has an expansion portion 179 having a large area for connection with another layer or an external device.

A plurality of branches extending from the data line 171 toward the drain electrode 175 forms a source electrode 173. Each of the drain electrodes 175 is positioned above the gate electrode 124 and partially surrounded by the source electrode 173, and the other end extending to overlap the storage electrode 137 to form a storage capacitor. Extends 176. The gate electrode 124, the source electrode 173, and the drain electrode 175 form a thin film transistor (TFT) together with the protrusion 154 of the semiconductor 151, and the channel of the thin film transistor is a source. A protrusion 154 is formed between the electrode 173 and the drain electrode 175.

The data line 171 and the drain electrode 175 may be made of a refractory metal such as chromium, molybdenum alloy, titanium, or tantalum. However, these may also include a low resistance film and a contact film.

Like the gate line 121, the data line 171 and the drain electrode 175 are also inclined with respect to the surface of the substrate 110 at an angle of about 30-80 °.

The ohmic contacts 161 and 165 exist only between the semiconductor 151 below and the data line 171 and the drain electrode 175 above and serve to lower the contact resistance.

Lower (first) and upper (second) passivation layers 180p and 180q are sequentially formed on the data line 171, the drain electrode 175, and the exposed semiconductor 151. It is preferable that the first passivation layer 180p is made relatively thin and made of an inorganic insulator such as silicon nitride, and the second passivation layer 180q is made relatively thick and made of an organic insulator. In the first and second passivation layers 180p and 180q, a plurality of contact holes 182 and 185 exposing the end portion 179 of the data line 171 and the drain electrode 175 are formed, respectively. In the first and second passivation layers 180p and 180q and the gate insulating layer 140, a plurality of contacts exposing portions of the contact hole 181 and the sustain electrode 137 exposing the end portion 129 of the gate line 121. The hole 186 is formed. The contact holes 181, 182, 185, and 186 have sidewalls with gentle angles, and may be rectangular planar, polygonal or circular in shape.

On the passivation layer 180, a plurality of pixel electrodes 190 made of ITO or IZO, a conductor 195 for a sustain electrode, and a plurality of contact assistants 81 and 82 are formed.

The pixel electrode 190 is physically and electrically connected to the drain electrode 175 through the contact hole 185 to receive a data voltage from the drain electrode 175.

The pixel electrode 190 applied with the data voltage generates an electric field together with a common electrode (not shown) of another display panel (not shown) to which a common voltage is applied, thereby generating liquid crystal molecules of the liquid crystal layer between the two electrodes. Rearrange them.

In addition, the pixel electrode 190 and the common electrode form a capacitor (hereinafter, referred to as a "liquid crystal capacitor") to maintain an applied voltage even after the thin film transistor is turned off. There is another capacitor connected in parallel with it, which is called a storage capacitor. The storage capacitor is formed by overlapping between the storage capacitor conductor 195 formed on the same layer as the pixel electrode 190, the storage electrode 137 connected thereto, and the extension 176 of the drain electrode.

However, when the voltage holding capability of the storage capacitor is small, leakage charges occur, and the amount of the kickback voltage increases due to the voltage drop phenomenon due to the leakage charge.

That is, as shown in FIG. 11, the kickback voltage refers to a sudden voltage drop occurring at the beginning of application of the data voltage when the data voltage Vd slowly applied over the data line slowly decreases with time. Clc denotes a liquid crystal capacitor formed between the pixel electrode 190 and the common electrode, Cst denotes a storage capacitor formed between the storage electrode 137 and the storage capacitor conductor 195 and the extension 176 of the drain electrode, Cgd denotes a parasitic capacitance formed between the gate electrode 124 and the drain electrode 175, Vg denotes a voltage applied to the gate line 121, ΔVp is to display the voltage drop due to the kickback phenomenon. In the following Equation 1, ΔVp is shown.

As described above, when the kickback voltage is increased, a flicker phenomenon is likely to occur.

Therefore, in one embodiment of the present invention, in order to increase the capacitance of the storage capacitor, that is, the storage capacitance, the storage capacitor conductor 195 is formed on the upper portion of the extension portion 176 of the drain electrode, thereby maintaining the storage capacitor conductor 195. ) Overlaps the extension 176 of the drain electrode, and the sustain electrode 137 is formed under the extension 176 of the drain electrode so that the sustain electrode 137 overlaps the extension 176 of the drain electrode. In addition, the storage electrode 137 and the storage capacitor conductor 195 may be connected through the second contact hole 186.

Therefore, the sustain voltage applied through the storage electrode 137 is also applied to the storage capacitor conductor 195 in three dimensions so that the extension portion 176 of the drain electrode, the storage electrode 137 and the storage capacitor conductor 195 are three-dimensionally. The holding capacity is improved by allowing the holding capacity to be formed.

The contact auxiliary members 81 and 82 are connected to the end portion 129 of the gate line and the end portion 179 of the data line through the contact holes 181 and 182, respectively. The contact auxiliary members 81 and 82 complement the adhesion between the end portions 129 and 179 of the gate line 121 and the data line 171 and the external device, and serve to protect them.

ITO or a transparent conductive polymer may be used as the material of the pixel electrode 190 and the storage capacitor conductor 195. In the case of a reflective liquid crystal display, an opaque reflective metal may be used. Do. In this case, the contact assistants 81 and 82 may be made of a material different from the pixel electrode 190, in particular, IZO or ITO.

The liquid crystal display according to the exemplary embodiment of the present invention includes the thin film transistor array panel illustrated in FIGS. 1 and 2B, a common electrode display panel (not shown), and a liquid crystal layer (not shown) disposed therebetween. Each display panel may include an alignment layer coated thereon.

Next, a method of manufacturing the thin film transistor array panel illustrated in FIGS. 1 to 2B will be described in detail with reference to FIGS. 3 to 10B and FIGS. 1 to 2B.

FIG. 3 is a layout view at an intermediate stage of a method of manufacturing the thin film transistor array panel shown in FIG. 1 according to an exemplary embodiment of the present invention, and FIG. 4A is a cutaway view of the thin film transistor array panel of FIG. 3 along line IVa-IVa '. 4B is a cross-sectional view of the thin film transistor array panel of FIG. 3 taken along lines IVb-IVb 'and IVb'-IVb ", and FIG. 5 is a layout view of the next step of FIG. 3, and FIG. 6A is a view of FIG. 5 is a cross-sectional view of the thin film transistor array panel of FIG. 5 taken along the line VIa-VIa ', and FIG. 6B is a cross-sectional view of the thin film transistor array panel of FIG. 5 taken along the line VIb-VIb' and VIb'-VIb ', and FIG. 7 is a layout view of the next step of FIG. 5, FIG. 8A is a cross-sectional view of the thin film transistor array panel of FIG. 7 taken along the line VIIIa-VIIIa ', and FIG. 8B is a line VIIIb-VIIIb' and the thin film transistor array panel of FIG. Is a cross-sectional view taken along the line VIIIb'-VIIIb ", 9 is a layout view of the next step of FIG. 7, and FIG. 10A is a cross-sectional view of the thin film transistor array panel of FIG. 9 taken along the line Xa-Xa ', and FIG. 10B is a line Xb-Xb' line of the thin film transistor array panel of FIG. It is sectional drawing cut along the line Xb'-Xb ".

First, as shown in FIGS. 3 to 4B, a metal film such as chromium, molybdenum, aluminum, silver, or an alloy thereof is laminated on the insulating substrate 110 such as transparent glass by sputtering or the like. The metal film is dry or wet etched by a photolithography process to form a plurality of gate lines 121 including the gate electrode 124 and a plurality of sustain electrodes 137. At this time, the sidewalls of the gate line 121 and the storage electrode 137 are formed to be tapered, and the tapered shape allows the layers formed thereon to be in close contact with each other.

Next, as shown in Figs. 5 to 6B, a three-layer film of a gate insulating film 140 made of silicon nitride or silicon oxide, an intrinsic amorphous silicon layer, and an impurity amorphous silicon layer (extrinsic amorphous silicon) is successively laminated. Then, the impurity amorphous silicon layer and the intrinsic amorphous silicon layer are photo-etched to form a linear intrinsic semiconductor 151 each including a plurality of linear impurity semiconductors 164 and a plurality of protrusions 154.

Referring to FIGS. 7 to 8B, the conductor layers are stacked by photolithography and photolithography to form a plurality of data lines 171 including the source electrode 173 and a plurality of drain electrodes 175. In this case, the extended portion 176 of the drain electrode is formed to partially overlap the sustain electrode 137.

Subsequently, the portions of the impurity semiconductor 164 that are not covered by the data line 171 and the drain electrode 175 are removed, and thus, the plurality of linear ohmic contacts 161 each including the plurality of protrusions 163 and the plurality of portions. The island-like ohmic contact 165 is completed, while the portion of the intrinsic semiconductor 151 below it is exposed.

9 and 10B, the lower passivation layer 180p made of silicon nitride or silicon oxide and the upper passivation layer 180q made of photosensitive organic insulating material are successively stacked and etched together with the gate insulating layer 140 to form a plurality of contact holes. (181, 182, 185, 186). The contact holes 181, 182, 185, and 186 expose the end portion 129 of the gate line 121, the end portion 179 of the data line 171, the drain electrode 175, and the storage electrode 137.

Finally, as shown in FIGS. 1 and 2B, a plurality of pixel electrodes 190, a storage capacitor conductor 195, and a plurality of pixel electrodes 190, ITO or ITO film are stacked on the upper passivation layer 180q by sputtering, and photo-etched. Contact assisting members 81 and 82 are formed.

A thin film transistor array panel according to another exemplary embodiment of the present invention is illustrated in FIGS. 12 and 13.

12 and 13, the layer structure of the thin film transistor array panel for a liquid crystal display device according to the present embodiment is generally the same as the layer structure of the thin film transistor array panel for liquid crystal display devices shown in Figs.

That is, the plurality of gate lines 121 including the gate electrode 124 and the plurality of sustain electrodes 137 are formed on the substrate 110, and the gate insulating layer 140 and the protrusion 154 are formed thereon. A plurality of linear semiconductors 151, a plurality of linear ohmic contacts 161 including protrusions 163, and a plurality of island-type ohmic contacts 165 are sequentially formed. A plurality of data electrodes 171 including a source electrode 153 and a plurality of drain electrodes 175 having an extension 176 are formed on the ohmic contacts 161 and 165, and the lower and upper passivation layers 175 are formed thereon. 180p, 180q) is formed. A plurality of contact holes 182, 185, and 186 are formed in the passivation layers 180p and 180q and the gate insulating layer 140, and the plurality of pixel electrodes 190 and the storage capacitor conductor 195 are disposed on the upper passivation layer 180q. ) And a plurality of contact assistants 82 are formed. Accordingly, in order to increase the capacitance of the storage capacitor, that is, the storage capacitor, a storage capacitor 195 is formed on the upper portion of the extension portion 176 of the drain electrode, so that the storage capacitor conductor 195 extends the drain electrode. The storage electrode 137 is formed under the extension portion 176 of the drain electrode so that the storage electrode 137 overlaps the extension portion 176 of the drain electrode, and the storage electrode 137. ) And the maintenance capacitance conductor 195 are connected through the second contact hole 186.

Therefore, the sustain voltage applied through the storage electrode 137 is also applied to the storage capacitor conductor 195 in three dimensions so that the extension portion 176 of the drain electrode, the storage electrode 137 and the storage capacitor conductor 195 are three-dimensionally. The holding capacity is improved by allowing the holding capacity to be formed.

However, unlike the thin film transistor array panel shown in FIGS. 1 to 2B, the semiconductor 151 has a plane substantially the same as the data line 171, the drain electrode 175, and the ohmic contacts 161 and 165 thereunder. It has a shape. However, the protrusion 154 of the linear semiconductor 151 has a portion exposed between the data line 171 and the drain electrode 175 such as between the source electrode 173 and the drain electrode 175.

In addition, there is no contact hole exposing the gate line 121 and a contact auxiliary member thereon. The gate line 121 may be directly connected to the gate driving circuit integrated on the substrate 110 together with the signal lines 121 and 171 and the electrodes 124, 173 and 175. However, a plurality of contact holes (not shown) are formed in the passivation layers 180p and 180q and the gate insulating layer 140 to connect with other portions of the gate driving circuit, and a plurality of connection members (not shown) are formed on the upper passivation layer 180q. Not).

In the method of manufacturing the thin film transistor according to the exemplary embodiment of the present invention, the data line 171, the drain electrode 175, the semiconductor 151, and the ohmic contacts 161 and 165 are formed in one photo process.

The photosensitive film pattern used in such a photo process differs in thickness according to a position, and especially includes a 1st part and a 2nd part in order of decreasing thickness. The first part is located in the wiring area occupied by the data line and the drain electrode, and the second part is located in the channel area of the thin film transistor.

There may be various methods of varying the thickness of the photoresist pattern according to the position. For example, a method of providing a translucent area in addition to the transparent area and the light blocking area in the photomask is possible. have. The translucent region is provided with a slit pattern, a lattice pattern, or a thin film having a medium transmittance or a medium thickness. When using the slit pattern, it is preferable that the width of the slits and the interval between the slits are smaller than the resolution of the exposure machine used for the photographic process. Another example is to use a photoresist film that can be reflowed. That is, a thin portion is formed by forming a reflowable photoresist pattern with a normal exposure mask having only a transparent region and a light shielding region and then reflowing to allow the photoresist film to flow down into a region where no residue is left.

In this way, a one-time photographic process can be reduced, thereby simplifying the manufacturing method.

Many features of the thin film transistor array panel for the liquid crystal display of FIGS. 1 to 2B described above may also be applied to the thin film transistor array panels of FIGS. 12 and 13.

The thin film transistor array panel and the method of manufacturing the same according to the present invention have an advantage of improving the storage capacitance by allowing the conductor for the storage capacitor and the storage electrode to overlap the extension of the drain electrode.

Although the preferred embodiments of the present invention have been described in detail above, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Accordingly, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concept of the present invention as defined in the following claims also belong to the scope of the present invention.

Claims (7)

A gate line and a sustain electrode formed on the substrate, A gate insulating film formed on the gate line and the storage electrode; A semiconductor layer formed on the gate insulating film, A data line formed at least in part on the semiconductor layer, A drain electrode formed at least in part on the semiconductor layer and spaced apart from the data line, A protective film formed on the data line and the drain electrode and having a first contact hole exposing at least a portion of the drain electrode; A pixel electrode formed on the passivation layer and connected to the drain electrode through the first contact hole; A conductive electrode conductor formed on the same layer as the pixel electrode and formed at a position which is separated from the pixel electrode and overlaps the storage electrode. Including, And the sustain electrode and the sustain electrode conductor are connected to each other, and an extension of the drain electrode overlaps the sustain electrode and the sustain electrode conductor. In claim 1, A thin film transistor array panel in which an organic layer is further formed between the passivation layer and the pixel electrode. In claim 1, The semiconductor layer has a planar shape substantially the same as the data line and the drain electrode except for a portion disposed between the data line and the drain electrode. In claim 1, The thin film transistor array panel of which the sustain electrode and the conductor for the sustain electrode are made of the same material. In claim 1, And the sustain electrode and the conductor for the sustain electrode are connected to each other through a second contact hole formed in the passivation layer. Forming a gate line and a sustain electrode on the substrate, Stacking a gate insulating film on the gate line and the storage electrode; Forming a semiconductor on the gate insulating film, Forming a drain electrode and a data line on the semiconductor and gate insulating film, Stacking a passivation layer and an organic layer on the data line and the drain electrode; Patterning the organic layer, the passivation layer, and the gate insulating layer to form a first contact hole exposing a portion of the drain electrode and a second contact hole exposing a portion of the sustain electrode; Forming a pixel electrode connected to the drain electrode through the first contact hole and a conductor for a sustain electrode connected to the sustain electrode through the second contact hole on the passivation layer; Including, And the sustain electrode conductor overlaps with an extension of the drain electrode. In claim 6, The sustain electrode and the conductor for the sustain electrode are made of the same material.

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