KR100200706B1 - Fabrication method of polysilicon tft-lcd device - Google Patents
Fabrication method of polysilicon tft-lcd device Download PDFInfo
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- KR100200706B1 KR100200706B1 KR1019960025220A KR19960025220A KR100200706B1 KR 100200706 B1 KR100200706 B1 KR 100200706B1 KR 1019960025220 A KR1019960025220 A KR 1019960025220A KR 19960025220 A KR19960025220 A KR 19960025220A KR 100200706 B1 KR100200706 B1 KR 100200706B1
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- 238000000034 method Methods 0.000 title claims abstract description 34
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 19
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 19
- 239000010408 film Substances 0.000 claims abstract description 29
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 22
- 239000010409 thin film Substances 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 239000004973 liquid crystal related substance Substances 0.000 claims abstract description 12
- 238000000206 photolithography Methods 0.000 claims abstract description 9
- 239000011521 glass Substances 0.000 claims abstract description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 6
- 229910004205 SiNX Inorganic materials 0.000 claims description 5
- 230000003213 activating effect Effects 0.000 claims description 3
- 238000007743 anodising Methods 0.000 claims description 3
- 230000001678 irradiating effect Effects 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 43
- 229920002120 photoresistant polymer Polymers 0.000 description 19
- 150000002500 ions Chemical class 0.000 description 15
- 239000012535 impurity Substances 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 230000004913 activation Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000002425 crystallisation Methods 0.000 description 2
- 230000008025 crystallization Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000005499 laser crystallization Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
- H01L29/78693—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate the semiconducting oxide being amorphous
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Abstract
신규한 폴리실리콘 박막트랜지스터 액정표시소자의 제조방법이 개시되어 있다. 유리기판 상에 게이트를 형성한 후, 기판 전면에 게이트절연막 및 비정질실리콘층을 차례로 증착한다. 사진식각 공정으로 상기 비정질실리콘층을 패터닝하여 액티브층을 형성한다. 상기 액티브층의 채널영역이 형성될 부위에 도핑 마스크층을 형성한다. 상기 도핑 마스크층을 이용하여 소오스/드레인 이온 도핑을 실시한다. 상기 결과물 전면에 레이저를 조사하여 상기 액티브층을 결정화시킴과 동시에 상기 도핑된 소오스/드레인을 활성화시킨다. 기존의 비정질실리콘 박막트랜지스터 액정표시소자의 제조공정을 최대한 이용하여 추가 투자를 최소화하고 개발기간을 단축시킬 수 있다.A novel method of manufacturing a polysilicon thin film transistor liquid crystal display device is disclosed. After the gate is formed on the glass substrate, a gate insulating film and an amorphous silicon layer are sequentially deposited on the entire surface of the substrate. The amorphous silicon layer is patterned by a photolithography process to form an active layer. A doping mask layer is formed on a portion where the channel region of the active layer is to be formed. Source / drain ion doping is performed using the doping mask layer. Laser irradiation of the entire surface of the resultant crystallizes the active layer and simultaneously activates the doped source / drain. By utilizing the existing manufacturing process of the amorphous silicon thin film transistor liquid crystal display device to maximize the additional investment and development period can be minimized.
Description
제1a도 내지 제1f도는 종래방법에 의한 폴리실리콘 박막트랜지스터 액정표시소자의 제조방법을 설명하기 위한 단면도들.1A to 1F are cross-sectional views illustrating a method of manufacturing a polysilicon thin film transistor liquid crystal display device by a conventional method.
제2a도 내지 제2h도는 본 발명에 의한 하부게이트 폴리실리콘 박막트랜지스터 액정표시소자의 제조방법을 설명하기 위한 단면도들.2A to 2H are cross-sectional views illustrating a method of manufacturing a lower gate polysilicon thin film transistor liquid crystal display device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
1, 10 : 기판 2, 12 : 액티브층1, 10: substrate 2, 12: active layer
3, 13 : 게이트절연막 4, 14 : 게이트3, 13 gate insulating film 4, 14 gate
15 : 도핑 마스크층 6, 16 : 층간절연막15: doping mask layer 6, 16: interlayer insulating film
7, 17 : 금속배선층7, 17: metallization layer
본 발명은 박막트랜지스터 액정표시장치의 제조방법에 관한 것으로, 특히 하부전극(bottom gate) 구조의 저온 폴리실리콘 박막트랜지스터 액정표시장치의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a thin film transistor liquid crystal display device, and more particularly, to a method for manufacturing a low temperature polysilicon thin film transistor liquid crystal display device having a bottom gate structure.
일반적으로 저원가 및 고성능의 박막트랜지스터 액정표시소자(thin film transistor liquid crystal display; 이하 TFT-LCD라 한다)에서는 스위칭 소자로서 비정질실리콘 박막트랜지스터를 사용하고 있다. 현재, 액정표시소자는 VGA(video graphic array; 최대 해상도는 640×480화소)에서 SVGA(800×600), XGA(1024×768), EWS(1280×1024)로 고해상도로 기술 및 제품이 개발되고 있다. 액정표시소자에 있어서, 화소의 크기는 VGA급 대비 EWS급에서 매우 작아지게 된다. 예를 들어, 10.4 VGA의 화소크기는 110×330㎛이며, 13.6 EWS의 화소크기는 70×210㎛이다 (상대면적은 40% 이다). 이와 같이, 화소가 작고 고정세일 경우, 박막트랜지스터가 화소 내에서 차지하는 면적이 상대적으로 증가하게 되며, 요구되는 박막트랜지스터의 온(ON)-전류 증가를 위해 박막트랜지스터의 크기가 더욱 커져야 하는 문제가 발생한다. 특히, 미래에 투사형 HDTV(High Density TV)를 위한 화소는 약 20㎛×20㎛이하로 작아질 수 있는데, 이 경우 이동도(mobility)가 큰 폴리실리콘 박막트랜지스터를 사용하여야 한다.In general, a low cost and high performance thin film transistor liquid crystal display (hereinafter referred to as TFT-LCD) uses an amorphous silicon thin film transistor as a switching element. Currently, liquid crystal display devices are developed in high resolution from VGA (video graphic array; maximum resolution is 640x480 pixels) to SVGA (800x600), XGA (1024x768), and EWS (1280x1024). have. In the liquid crystal display device, the pixel size becomes very small in the EWS class compared to the VGA class. For example, the pixel size of 10.4 VGA is 110 x 330 μm and the 13.6 EWS pixel size is 70 x 210 μm (relative area is 40%). As such, when the pixel is small and has a high definition, the area occupied by the thin film transistor in the pixel is relatively increased, and a problem that the size of the thin film transistor must be further increased is required to increase the ON-current of the thin film transistor. do. In particular, in the future, the pixel for a projection HDTV (High Density TV) may be reduced to about 20 μm × 20 μm or less. In this case, a polysilicon thin film transistor having a high mobility should be used.
이와 같이 차세대 액정표시소자로 각광받고 있는 폴리실리콘 TFT-LCD중에서, 소형에 주로 적용되는 고온 폴리실리콘 TFT-LCD는 석영(Qz)기판을 사용하여 고온공정을 적용한다. 반면에, 중대형에 적용될 것으로 예상되는 약 400℃ 이하의 온도에서 형성되는 저온 폴리실리콘 TFT-LCD는 유리 기판을 사용하여 기존의 비정질실리콘 TFT-LCD의 제조라인에 적용가능하다는 특징이 있다. 이러한 저온 폴리실리콘 TFT-LCD의 제조에 있어서 중요한 핵심기술은 크게 액티브층의 결정화, 게이트절연막 형성, 게이트 형성, 및 소오스/드레인 활성화 기술을 들 수 있다.Among the polysilicon TFT-LCDs that are spotlighted as the next-generation liquid crystal display devices, the high temperature polysilicon TFT-LCD mainly applied to small size uses a high temperature process using a quartz (Qz) substrate. On the other hand, the low temperature polysilicon TFT-LCD formed at a temperature of about 400 ° C. or less, which is expected to be applied to the medium-large size, is characterized by being applicable to the manufacturing line of the existing amorphous silicon TFT-LCD using a glass substrate. Important technologies in the manufacture of such low-temperature polysilicon TFT-LCDs include crystallization of active layers, gate insulating film formation, gate formation, and source / drain activation technologies.
제1a도 내지 제1f도는 종래방법에 의한 폴리실리콘 TFT-LCD의 제조방법을 설명하기 위한 단면도들이다.1A to 1F are cross-sectional views for explaining a method of manufacturing a polysilicon TFT-LCD by a conventional method.
제1a도를 참조하면, 유리기판(1) 상에 비정질실리콘층(2′)을 증착한 후, 그 전면에 엑시머 레이저(Excimer laser)(9)를 조사하여 상기 비정질실리콘층(2′)을 결정화시킨다.Referring to FIG. 1A, after depositing an amorphous silicon layer 2 'on a glass substrate 1, an excimer laser 9 is irradiated to the entire surface thereof to irradiate the amorphous silicon layer 2'. Crystallize.
제1b도를 참조하면, 사진공정으로 상기 결과물 상에 포토레지스트 패턴(도시되지 않음)을 형성한 후, 이를 마스크로 이용하여 상기 결정화된 비정질실리콘층(2′)을 식각함으로써 액티브층(2)을 형성한다. 이어서, 상기 결과물 전면에 게이트절연막(3)으로, 예컨대 실리콘산화막(SiO2)을 증착한다.Referring to FIG. 1B, a photoresist pattern (not shown) is formed on the resultant by a photographic process, and then the crystallized amorphous silicon layer 2 'is etched using the photoresist pattern as a mask to form the active layer 2. To form. Subsequently, a silicon oxide film (SiO 2 ), for example, is deposited on the entire surface of the resulting product as a gate insulating film 3.
제1c도를 참조하면, 상기 결과물 전면에 게이트용 도전물질로서 폴리실리콘 혹은 금속막을 증착한 후, 사진식각 공정으로 이를 패터닝하여 게이트(4)를 형성한다.Referring to FIG. 1C, a gate layer 4 is formed by depositing a polysilicon or a metal film as a gate conductive material on the entire surface of the resultant, and then patterning it by a photolithography process.
제1d도를 참조하면, 사진공정으로 상기 결과물 상에 N형 소오스/드레인 형성을 위한 제1 포토레지스트 패턴(5)을 형성한 후, 이를 마스크로 이용하여 노출된 액티브층(2) 영역에 N형 불순물, 예컨대 인(P+)을 이온 샤워(ion shower) 방식으로 도핑시킨다.Referring to FIG. 1D, after forming a first photoresist pattern 5 for forming an N-type source / drain on the resultant by a photographic process, N is formed on the exposed active layer 2 region using the mask as a mask. Type impurities such as phosphorus (P + ) are doped in an ion shower manner.
제1e도를 참조하면, 상기 제1 포토레지스트 패턴(5)을 제거한 후, 다시 결과물 상에 P형 소오스/드레인 형성을 위한 제2 포토레지스트 패턴(5′)을 형성한다. 상기 제2 포토레지스트 패턴(5′)을 마스크로 이용하여 노출된 액티브층(2) 영역에 P형 불순물, 예컨대 보론(B+)으로 이온 샤워 방식으로 도핑시킨다.Referring to FIG. 1E, after removing the first photoresist pattern 5, a second photoresist pattern 5 ′ for forming a P-type source / drain is formed on the resultant. Using the second photoresist pattern 5 ′ as a mask, the exposed active layer 2 is doped with P-type impurities such as boron (B + ) in an ion shower method.
제1f도를 참조하면, 상기 제2 포토레지스트 패턴(5′)을 제거한 후, 결과물 전면에 층간절연막(6)을 형성한다. 사진식각 공정으로 상기 게이트(4)와 소오스/드레인 영역 상에 적층된 층들을 식각하여 콘택홀들을 형성한 후, 상기 콘택홀들을 통해 게이트(4)와 소오스/드레인에 접속되는 금속배선층(7)을 형성한다. 그 결과, N형 박막트랜지스터(N-TFT)와 P형 박막트랜지스터(P-TFT)가 완성된다.Referring to FIG. 1f, after removing the second photoresist pattern 5 ′, an interlayer insulating film 6 is formed on the entire surface of the resultant. After forming the contact holes by etching the layers stacked on the gate 4 and the source / drain regions by a photolithography process, the metal wiring layer 7 connected to the gate 4 and the source / drain through the contact holes. To form. As a result, an N-type thin film transistor (N-TFT) and a P-type thin film transistor (P-TFT) are completed.
상술한 바와 같이 종래에 가장 많이 사용되고 있는 저온 폴리실리콘 TFT-LCD의 제조방법은 상부 게이트(top gate) 구조를 사용하고 게이트절연막으로 실리콘산화막을 사용하기 때문에, 기존의 비정질실리콘 TFT-LCD 제조라인을 이용할 경우, 결정화를 위한 레이저 시스템, 산화막 제작을 위한 화학기상증착(chemical vapor deposition) 장비, 소오스/드레인 도핑을 이한 이온 샤워(ion shower) 장비 등이 추가로 필요하게 된다. 일반적으로, 소오스/드레인 도핑은 이온주입 공정으로 실시되어 왔는데, 이온주입 공정은 불순물의 활성화를 위해 고온 어닐링 공정이 수반되는데, 대면적의 유리기판을 사용하고 약 400℃ 이하의 저온공정을 진행하는 저온 폴리실리콘 TFT-LCD에 적용하기 위해서는 고온 어닐링 공정 대신 레이저를 이용한 활성화 방법을 사용하여야 하므로 공정이 복잡해지는 문제가 있다. 따라서, 이를 해결하기 위해 이온 샤워라는 공정을 도입하게 되었는데, 이온 도핑 중 셀프-큐어링(self-curing)이 가능하며 비교적 낮은 온도(∼450℃이하)에서 활성화가 가능하다는 장점을 지니고 있지만, 기판 온도가 높아지게 되어 마스킹 재료로서 반도체 공정에서 흔히 이용하고 있는 포토레지스트를 사용할 경우 포토레지스트의 경화를 유발한다. 특히, 기존의 비정질실리콘 TFT-LCD의 제조라인에서는 게이트절연막으로 실리콘질화막(SiNx)을 사용하기 때문에, 궁극적으로 실리콘질화막을 게이트절연막으로 사용할 경우 절연막 두께가 2배 정도 증가하게 되어 투사범위(Projected range; Rp)를 맞추기 위해 에너지를 높이면 포토레지스트의 경화현상이 더욱 심해지게 된다.As described above, the manufacturing method of the low temperature polysilicon TFT-LCD which is most commonly used in the related art uses a top gate structure and a silicon oxide film as the gate insulating film, thus making it possible to eliminate the conventional amorphous silicon TFT-LCD manufacturing line. When used, a laser system for crystallization, chemical vapor deposition equipment for oxide film production, ion shower equipment with source / drain doping, and the like are additionally required. In general, source / drain doping has been carried out by ion implantation process, which involves high temperature annealing process to activate impurities, using a large area glass substrate and low temperature process of about 400 ° C or less. In order to apply to low-temperature polysilicon TFT-LCD, it is necessary to use an activation method using a laser instead of a high temperature annealing process. Therefore, to solve this problem, a process called ion shower was introduced, which has the advantage of being self-curing during ion doping and activating at a relatively low temperature (~ 450 ° C. or lower). As the temperature increases, the photoresist commonly used in the semiconductor process as a masking material causes hardening of the photoresist. In particular, in the conventional amorphous silicon TFT-LCD manufacturing line, since the silicon nitride film (SiNx) is used as the gate insulating film, when the silicon nitride film is used as the gate insulating film, the thickness of the insulating film is increased by about twice. Raising the energy to match Rp) makes the photoresist harder.
따라서, 본 발명의 목적은 상술한 종래방법의 문제점을 해결하기 위한 것으로, 기존에 설비(set up)되어 있는 비정질실리콘 TFT-LCD의 제작공정을 최대한 이용하여 장비의 추가 투자를 최소화하면서 개발기간을 단축시킬 수 있는 폴리실리톤 TFT-LCD의 제조방법을 제공하는데 있다.Accordingly, an object of the present invention is to solve the problems of the conventional method described above, and to minimize the additional investment of equipment by making the most of the manufacturing process of the amorphous silicon TFT-LCD that is already set up (set up), the development period is minimized. The present invention provides a method for manufacturing a polysilicon TFT-LCD that can be shortened.
상기 목적을 달성하기 위하여 본 발명은, 유리기판 상에 게이트를 형성하는 단계; 상기 게이트가 형성된 기판 전면에 게이트절연막 및 비정질실리콘층을 차례로 증착하는 단계; 사진식각 공정으로 상기 비정질실리콘층을 패터닝하여 액티브층을 형성하는 단계; 상기 액티브층의 채널영역이 형성될 부위에 도핑 마스크층을 형성하는 단계; 상기 도핑 마스크층을 이용하여 소오스/드레인 이온 도핑을 실시하는 단계; 및 상기 결과물 전면에 레이저를 조사하여 상기 액티브층을 결정화시킴과 동시에 상기 도핑된 소오스/드레인을 활성화시키는 단계를 구비하는 것을 특징으로 하는 폴리실리콘 TFT-LCD의 제조방법을 제공한다.The present invention to achieve the above object, forming a gate on a glass substrate; Sequentially depositing a gate insulating film and an amorphous silicon layer on the entire surface of the substrate on which the gate is formed; Patterning the amorphous silicon layer by a photolithography process to form an active layer; Forming a doping mask layer on a portion where the channel region of the active layer is to be formed; Performing source / drain ion doping using the doping mask layer; And crystallizing the active layer by irradiating a laser onto the entire surface of the resultant, and simultaneously activating the doped source / drain.
상기 도핑 마스크층은 실리콘질화막(SiNx)으로 형성하는 것이 바람직하다.The doping mask layer is preferably formed of a silicon nitride film (SiNx).
상기 도핑 마스크층은 배면 노광 공정을 사용하여 형성하는 것이 바람직하다.The doping mask layer is preferably formed using a back exposure process.
상기 게이트절연막을 증착하는 단계 전에, 상기 게이트를 양극산화시키는 공정을 더 구비할 수 있다.Before depositing the gate insulating layer, the method may further include anodizing the gate.
상기 소오스/드레인 이온 도핑은 이온 샤워 방식으로 실시하는 것이 바람직하다.The source / drain ion doping is preferably performed by an ion shower method.
상기 레이저를 조사하는 단계에서, 상기 도핑된 소오스/드레인 이온이 활성화된다.In the step of irradiating the laser, the doped source / drain ions are activated.
이하, 본 발명의 바람직한 실시예를 첨부한 도면을 참조하여 상세히 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
제2a도 내지 제2h도는 본 발명에 의한 하부게이트 폴리실리콘 박막트랜지스터 액정표시소자의 제조방법을 설명하기 위한 단면도들이다.2A to 2H are cross-sectional views illustrating a method of manufacturing a lower gate polysilicon thin film transistor liquid crystal display device according to the present invention.
제2a도를 참조하면, 유리기판(10) 상에 게이트용 도전물질로서 폴리실리콘 또는 금속막을 증착한 후, 사진식각 공정으로 이를 패터닝하여 게이트(14)를 형성한다. 이때, 상기 게이트(14)가 금속막, 예컨대 알루미늄(A1)으로 형성될 경우, 이를 양극산화시키는 공정을 더 구비할 수도 있다.Referring to FIG. 2A, a polysilicon or metal film is deposited on the glass substrate 10 as a conductive material for the gate, and then patterned by a photolithography process to form the gate 14. In this case, when the gate 14 is formed of a metal film, for example, aluminum (A1), it may further include a step of anodizing it.
제2b도를 참조하면, 상기 게이트(14)가 형성된 결과물 전면에 게이트절연막(13)으로, 예컨대 실리콘질화막(SiNx)을 증착한다.Referring to FIG. 2B, a silicon nitride film (SiNx), for example, is deposited on the entire surface of the product on which the gate 14 is formed.
제2c도를 참조하면, 계속해서, 상기 게이트절연막(13) 전면에 비정질실리콘층을 증착한 후, 사진식각 공정으로 상기 비정질실리콘층을 패터닝하여 액티브층(12)을 형성한다.Referring to FIG. 2C, the amorphous silicon layer is subsequently deposited on the entire gate insulating layer 13, and then the amorphous silicon layer is patterned by a photolithography process to form the active layer 12.
제2d도를 참조하면, 상기 액티브층(12)이 형성된 결과물 전면에 채널영역을 보호하기 위한 도핑 마스크층(15)으로, 예컨대 실리콘질화막(SiNx)을 증착한다. 사진공정으로 상기 결과물 상에 포토레지스트(도시되지 않음)를 도포한 후, 이를 기판의 배면에서 노광하여 포토레지스트 패턴을 형성한다. 상기 포토레지스트 패턴을 이용하여 상기 도핑 마스크층(15)을 패터닝한 후, 포토레지스트 패턴을 제거한다.Referring to FIG. 2D, a silicon nitride layer (SiNx) is deposited using the doped mask layer 15 to protect the channel region on the entire surface of the resultant layer on which the active layer 12 is formed. A photoresist (not shown) is applied on the resultant by a photolithography process, and then it is exposed on the back side of the substrate to form a photoresist pattern. After the doping mask layer 15 is patterned using the photoresist pattern, the photoresist pattern is removed.
제2e도를 참조하면, 상기 도핑 마스크층(15)이 형성된 결과물 상에 N형 소오스/드레인 형성을 위한 제1 포토레지스트 패턴(18)을 형성한 후, 이를 이용하여 노출된 액티브층(12) 영역에 N형 불순물, 예컨대 인(P+)을 이온 샤워 방식으로 도핑시킨다.Referring to FIG. 2E, after forming the first photoresist pattern 18 for forming an N-type source / drain on the resultant layer on which the doping mask layer 15 is formed, the active layer 12 exposed by using the same is formed. N-type impurities, such as phosphorus (P + ), are doped into the region by ion showering.
제2f도를 참조하면, 상기 제1 포토레지스트 패턴(18)을 제거한 후, 다시 결과물 상에 P형 소오스/드레인 형성을 위한 제2 포토레지스트 패턴(18′)을 형성한다. 상기 제2 포토레지스트 패턴(18′)을 마스크로 이용하여 노출된 액티브층(12) 영역에 P형 불순물, 에컨대 보론(B+)을 이온 샤워 방식으로 도핑시킨다.Referring to FIG. 2F, after removing the first photoresist pattern 18, a second photoresist pattern 18 ′ for forming a P-type source / drain is formed on the resultant. Using the second photoresist pattern 18 ′ as a mask, P-type impurities, for example boron (B + ), are doped in the exposed active layer 12 by an ion shower method.
제2g도를 참조하면, 상기 제2 포토레지스트 패턴(18′)을 제거한 후, 결과물 전면에 엑시머 레이저(19)를 조사함으로써, 비정질실리콘으로 이루어진 액티브층(12)을 결정화한다. 이때, 상기 이온 샤워 도핑시 N형 및 P형 소오스/드레인 이온들의 활성화가 덜 되었더라도, 레이저의 조사에 의해 다시 활성화가 되므로 저저항의 소오스/드레인을 형성하는데 유리한다.Referring to FIG. 2G, after the second photoresist pattern 18 ′ is removed, the excimer laser 19 is irradiated on the entire surface of the resultant to crystallize the active layer 12 made of amorphous silicon. At this time, even when the N-type and P-type source / drain ions are less activated when the ion shower is doped, the N-type and P-type source / drain ions are activated again by laser irradiation, so it is advantageous to form a low resistance source / drain.
제2h도를 참조하면, 상기 결과물 전면에 층간절연막(16)을 형성한다. 사진식각 공정으로 상기 소오스/드레인 영역 상에 적층된 층들을 식각하여 콘택홀들을 형성한 후, 상기 콘택홀들을 통해 소오스/드레인에 접속되는 금속배선층(17)을 형성한다. 그 결과, N형 박막트랜지스터(N-TFT)와 P형 박막트랜지스터(P-TFT)가 완성된다.Referring to FIG. 2H, an interlayer insulating film 16 is formed on the entire surface of the resultant product. After forming the contact holes by etching the layers stacked on the source / drain region by a photolithography process, a metal wiring layer 17 connected to the source / drain is formed through the contact holes. As a result, an N-type thin film transistor (N-TFT) and a P-type thin film transistor (P-TFT) are completed.
상술한 바와 같이 본 발명에 의한 저온 폴리실리콘 TFT-LCD 제조방법에 의하면, 기존의 비정질실리콘 TFT-LCD와 같은 하부게이트(bottom gate) 구조를 사용하고 실리콘질화막으로 게이트절연막을 형성한다. 따라서, 게이트를 형성한 후 게이트절연막과 액티브용 비정질실리콘층을 연속적으로 증착할 수 있어, 상기 게이트절연막과 액티브용 비정질실리콘층과의 계면에서 결함이 발생하는 것을 방지할 수 있다. 또한, 도핑 마스크층을 이용하여 소오스/드레인을 셀프얼라인(self-align)으로 형성할 수 있다. 또한, 이온 샤워 도핑시 소오스/드레인용 불순물의 활성화가 덜 되었더라도, 액티브층의 레이저 결정화 단계에서 다시 상기 불순물이 활성화가 되므로 저저항의 소오스/드레인 형성에 유리한다.As described above, according to the method for manufacturing a low temperature polysilicon TFT-LCD according to the present invention, a gate insulating film is formed using a silicon nitride film using a bottom gate structure such as a conventional amorphous silicon TFT-LCD. Therefore, after the gate is formed, the gate insulating film and the active amorphous silicon layer can be deposited successively, thereby preventing the occurrence of defects at the interface between the gate insulating film and the active amorphous silicon layer. In addition, the source / drain may be self-aligned using the doping mask layer. In addition, even if the activation of the source / drain impurity is less during ion shower doping, the impurity is activated again in the laser crystallization step of the active layer, which is advantageous in forming a low resistance source / drain.
따라서, 본 발명은 기존에 설비되어 있는 비정질실리콘 TFT-LCD의 제작공정을 최대한 이용하여 장비의 추가 투자를 최소화하면서 개발기간을 단축시킬 수 있다.Therefore, the present invention can shorten the development period while minimizing additional investment of equipment by making full use of the existing manufacturing process of amorphous silicon TFT-LCD.
본 발명이 상기 실시예에 한정되지 않으며, 많은 변형이 본 발명의 기술적 사상내에서 당분야에서 통상의 지식을 가진 자에 의하여 가능함은 명백하다.The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical idea of the present invention.
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| US6875644B2 (en) | 2001-11-20 | 2005-04-05 | Samsung Sdi Co., Ltd. | Methods of manufacturing thin film transistors using masks to protect the channel regions from impurities while doping a semiconductor layer to form source/drain regions |
| KR100585873B1 (en) * | 2003-11-03 | 2006-06-07 | 엘지.필립스 엘시디 주식회사 | Polycrystalline liquid crystal display device and fabfication method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6875644B2 (en) | 2001-11-20 | 2005-04-05 | Samsung Sdi Co., Ltd. | Methods of manufacturing thin film transistors using masks to protect the channel regions from impurities while doping a semiconductor layer to form source/drain regions |
| KR100491142B1 (en) * | 2001-11-20 | 2005-05-24 | 삼성에스디아이 주식회사 | Method for formming thin film transistor |
| US7205183B2 (en) | 2001-11-20 | 2007-04-17 | Samsung Sdi Co., Ltd. | Methods of manufacturing thin film transistors using masks to protect the channel regions from impurities while doping a semiconductor layer to form source/drain regions |
| KR100585873B1 (en) * | 2003-11-03 | 2006-06-07 | 엘지.필립스 엘시디 주식회사 | Polycrystalline liquid crystal display device and fabfication method thereof |
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| KR980003750A (en) | 1998-03-30 |
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