JP2003257989A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device structure capable of reducing the probability of the generation of any failure by reducing the number of masks and reducing the number of processes, and to provide a method for manufacturing a semiconductor device structure capable of determining a source (drain) electrode pattern position for a source (drain) area like self-alignment. <P>SOLUTION: The dope silicon layer of source/drain wiring materials is formed and then etched so that a source/drain electrode and a gate electrode can be simultaneously formed. Then, dopant impurity is thermally diffused from the source/drain electrode to the source/drain area by heat treatment so that an ohm contact junction can be formed, and that the source/drain area can be formed as a first conductive low sheet resistor. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device using a thin film transistor (hereinafter referred to as TFT) having an active layer formed of a crystalline semiconductor.

[0002]

(Prior Art 1) A conventional top gate type polycrystalline silicon N-channel TFT manufacturing process example
This will be described with reference to FIGS. 8 (A) to 8 (E). After forming the base insulating film 1 and the crystalline silicon layer to be the active layer on the substrate,
A crystalline silicon layer is formed on the island-shaped crystalline silicon film 2 by a photolithography and etching process. A gate insulating film 3 is formed on the island-shaped crystalline silicon layer 2.
A gate electrode film 4 is formed on the gate insulating film 3. (Fig. 8
(A))

A gate electrode 5 is formed on the gate electrode film 4 by photolithography and etching. Next, in order to form a lightly doped drain (LDD) region, N ⁻ doping is performed by using an ion shower method or an ion doping method. At this time, since the gate electrode serves as a doping mask, the N ^- doping region can be formed by self-alignment. (Fig. 8 (B))

[0004] subjected to patterning of the N ⁺ doped region by photolithography, using the ion shower method or an ion doping method, N ⁺ doping. However, if the LDD region is not formed, this photolithography process is not necessary (the entire surface of the substrate is N ⁺ doped,
It may be a single drain structure TFT), but
When using a polycrystalline silicon TFT as a pixel element of an active matrix type liquid crystal display device, it is necessary to form an LDD region in order to reduce off leak current.
An interlayer insulating film 8 is formed on the gate electrode 5 and the gate insulating film 3. (Fig. 8 (C))

Contact holes are formed in the interlayer insulating film by photolithography and etching processes. Then, the source and drain electrode layers 9 are formed. As a result, the source and drain regions of the island-shaped crystalline silicon layer 2 at the bottom of the contact hole come into contact with the source and drain electrode layers. (Figure 8 (D))

The source and drain electrode layers 9 are formed on the source and drain electrodes 10 by photolithography and etching processes. As described above, the number of photomasks required until the source and drain electrodes are formed in the top gate type polycrystalline silicon N-channel TFT manufacturing process having the LDD region is five. (Fig. 8
(E))

(Prior Art 2) Next, Japanese Patent Application Laid-Open No. 9-4592
As disclosed in Japanese Unexamined Patent Publication No. 5 (1998), by implanting impurities from the source and drain electrodes, one example in which the number of masks is reduced by 1 compared with the prior art 1 is shown in FIGS. This will be explained using (E).

After forming the base insulating film 11 and the crystalline silicon layer to be the active layer on the substrate, the crystalline silicon layer is formed on the island-shaped crystalline silicon film 12 by photolithography and etching. Island crystalline silicon layer 1
A gate insulating film 13 is formed on 2. Gate insulating film 13
A gate electrode film 14 is formed on top. (Fig. 9 (A))

A gate electrode 15 is formed on the gate electrode film 14 by photolithography and etching. (Fig. 9 (B))

An interlayer insulating film 16 is formed on the gate electrode 15 and the gate insulating film 13. (Fig. 9 (C))

Contact holes are formed in the interlayer insulating film by photolithography and etching. Then, the conductor layer 17 made of aluminum is formed. As a result, the source and drain regions of the island-shaped crystalline silicon layer 12 at the bottom of the contact hole come into contact with the conductor layer 17. (Fig. 9 (D))

The source and drain electrodes 18 are formed by patterning into a desired shape. Subsequently, lamp light is irradiated from the back surface of the transparent insulating substrate using the RTA method. Then, the source and drain electrodes 18 made of an aluminum film absorb the lamp light and are heated, so that the aluminum in the source and drain electrodes 18 becomes polycrystalline silicon film 1.
Solid phase diffusion into 2. As a result, for silicon p
P-type source and drain regions 19 are formed in the polycrystalline silicon film 2 by aluminum as a type impurity. (Fig. 9 (E))

As an advantage over the prior art 1, the source and drain regions can be formed in a self-aligned manner with respect to the source and drain electrodes, and the number of masks for implanting impurities into the source and drain regions is reduced by one. There are points that can be done.

[0014]

In manufacturing a semiconductor device, there is a finite value for the defective product occurrence rate in each process, and the probability of defective product occurrence in a semiconductor device increases as the number of processes increases. Therefore, the product yield will decrease. Therefore, reducing the number of steps is a very important issue in order to increase the yield of products.

For example, in Prior Art 2, as compared with Prior Art 1, one dope pattern mask for the source and drain regions can be reduced. By reducing the number of dope pattern masks in this way, all of the cleaning step, resist coating step, resist baking step, exposure step, developing step, substrate drying step, doping step, resist ashing, stripping step, and substrate drying step are eliminated. be able to.

Further, in the prior art 2, as compared with the prior art 1, one mask patterning step is eliminated, and the source and drain regions can be formed in a self-aligned manner with respect to the source and drain electrodes. In the fabrication of semiconductor devices, the amount of overlay misalignment between multiple masks used by the end of the process (the amount of misalignment from the ideal design pattern during mask design) is one of the factors that determine the semiconductor device structure. is there. If the amount of misalignment is too large,
This means that the desired semiconductor device structure cannot be obtained, and the required electrical characteristics of the semiconductor device may not be obtained. Therefore, it is highly desirable to be able to fabricate a semiconductor device structure in a self-aligned manner.

As described above, finding a process method for reducing the number of masks by one without changing the finally manufactured semiconductor device structure means that many steps associated therewith can be reduced and the semiconductor device structure can be self-assembled. That is, it can be manufactured in a consistent manner.

On the other hand, as a problem of Prior Art 2, although Al, which is the main material of the source and drain electrodes, is diffused in the active layer, this method cannot provide a stable process. Si and Al form an alloy layer at low temperature, and alloying causes the movement of atoms through the interface, resulting in "alloy penetration".
It is also shown in "Analysis and evaluation of surfaces and interfaces, edited by Japan Society of Applied Physics, edited by Akio Hiraki, Tadashi Narizawa, Ohmsha, pp4-6" that causes a famous trouble called ". This is probably due to the high solid solubility of Si atoms in Al and the high diffusion coefficient of Si in Al. "alloy pen
Since "etration" does not occur uniformly at the contact interfaces of all devices but locally occurs, this results in a TFT structure that varies among lots, between substrates, and between devices, and a stable controllable process method. Not really.

In particular, the pixel portion TFT, which is manufactured by a high temperature process for use in a projector or the like, tends to be downsized. For example, in order to realize a high-definition display of XGA (1024 × 768 pixels) in a 0.7-inch diagonal liquid crystal display device, each pixel has an extremely small area of 14 μm × 14 μm. Has become. Therefore, in order not to reduce the aperture ratio, the area of the contact hole is also about 1 μm square. As the transistor size shrinks in this way, the distance between the contact hole and the channel region also decreases to a few μm or less.
If "penetration" occurs, the impurities diffuse into the channel region and destroy the intended device structure.

It is an object of the present invention to provide a method of manufacturing a semiconductor device structure capable of reducing the number of steps by reducing the number of masks and reducing the probability of defective products as compared with the prior art. To do. Further, in the present invention, the position of the source (drain) electrode pattern with respect to the source (drain) region can be determined in a self-aligned manner, and the LD
An object of the present invention is to provide a method for manufacturing a semiconductor device structure capable of reducing the LDD length variation due to a mask overlay error by determining the D region in a self-aligned manner.

[0021]

In order to solve the above-mentioned problems, the structure of the present invention comprises a first step of forming a crystalline semiconductor layer which becomes an active layer of a TFT on an insulating substrate, and the crystalline semiconductor layer is formed as an island. Forming a gate insulating film so as to cover the island crystalline semiconductor layer, etching the gate insulating film on the source and drain regions of the island crystalline semiconductor layer Fourth step of forming holes, fifth step of forming a conductor layer doped with impurities on the gate insulating film and on the source and drain regions of the island-shaped crystalline semiconductor layer, etching the conductor layer,
A sixth step of simultaneously forming a source / drain electrode and a gate electrode, a dopant impurity is thermally diffused from the source / drain electrode to the source / drain regions of the island-shaped crystalline semiconductor layer by heat treatment to form an ohmic contact junction to form an island-shaped contact. It comprises a seventh step of making the source and drain regions of the crystalline semiconductor layer have a low sheet resistance of the first conductivity type.

In another configuration, the first step of forming the crystalline semiconductor layer on the insulating substrate, the second step of forming the crystalline semiconductor layer in an island shape, and the gate insulation so as to cover the island-shaped crystalline semiconductor layer. A third step of forming a film, a fourth step of etching a gate insulating film on the source and drain regions of the island-shaped crystalline semiconductor layer to form a contact hole, and a step of forming the contact hole on the gate insulating film and the island-shaped crystalline semiconductor layer. Fifth, forming a conductive layer doped with impurities on the source and drain regions
A sixth step of forming a source / drain electrode and a gate electrode simultaneously by etching the conductive counter layer, and a region where the source / drain electrode and the gate electrode do not exist immediately above using the source / drain electrode and the gate electrode as a mask. A seventh step of ion-doping or ion-implanting an impurity of the first conductivity type into the island-shaped crystalline semiconductor layer, a dopant impurity from the source and drain electrodes to the source and drain regions of the island-shaped crystalline semiconductor layer by heat treatment. The eighth step of thermally diffusing to form an ohmic contact junction and making the source and drain regions of the island-shaped crystalline semiconductor layer have a low sheet resistance of the first conductivity type.

In another configuration, a first step of forming a crystalline semiconductor layer to be an active layer of a TFT on an insulating substrate, a second step of forming the crystalline semiconductor layer in an island shape, and an island crystalline semiconductor layer. Step of forming a gate insulating film so as to cover the gate insulating film, a fourth step of etching the gate insulating film on the source and drain regions of the island-shaped crystalline semiconductor layer to form a contact hole, on the gate insulating film and the island A fifth step of forming a conductor layer doped with impurities on the source and drain regions of the crystalline semiconductor layer, a sixth step of etching the conductor layer to form source and drain electrodes and a gate electrode at the same time, By heat treatment, dopant impurities are thermally diffused from the source and drain electrodes to the source and drain regions of the island-shaped crystalline semiconductor layer to form ohmic contact junctions. Seventh step of the source and drain regions of Jo crystalline semiconductor layer and the low sheet resistance of the first conductivity type,
An eighth step of forming an LDD region by thermally diffusing a dopant impurity from the source and drain regions of the island-shaped crystalline semiconductor layer toward the channel region of the island-shaped crystalline semiconductor layer by heat treatment.

In the structure of the above invention, a doped silicon layer or a doped silicon germanium layer can be applied to the electric conductor layer. Further, the conductor layer has a stacked structure, and the layer which is connected to the source and drain regions of the island-shaped crystalline semiconductor layer may be formed of a doped silicon layer or a doped silicon germanium layer. At least one layer of the films forming the laminated structure can be formed of a silicide layer. As the silicide layer, any one of molybdenum silicide, tungsten silicide, titanium silicide, platinum silicide, palladium silicide, nickel silicide, and cobalt silicide can be used.

In the conductor layer, P, As, Sb, B and A are formed in the regions which are connected to the source and drain regions of the island-shaped crystalline semiconductor layer.
At least one of l, Ga, and In is 1 × 10 ¹⁹ cm
It may be contained at a concentration of ^-3 or more.

The structure of the present invention is applicable to the manufacture of a unipolar semiconductor device in which the first conductivity type is N-channel type and all transistors formed on the substrate are N-channel type. You can

The structure of the present invention is applicable to the manufacture of a unipolar semiconductor device in which the first conductivity type is a P-channel type and all transistors formed on the substrate are P-channel type. You can

FIG. 10 and FIG. 11 on the configuration of the present invention.
It will be explained using and. An island-shaped crystalline semiconductor layer 104 and a gate insulating film 105 which are to be active layers of thin film transistors and a gate insulating film 105 are formed over a substrate (FIG. 10B), and gates on source and drain regions where wiring and a semiconductor layer are in contact with each other A contact hole is formed by partially etching the insulating film (FIG. 10C), and a doped silicon layer 106 of a source and drain wiring material is formed (FIG. 10).
(D)).

Next, the doped silicon layer is etched by a photolithography method to form the source electrode 108, the drain electrode 107, and the gate electrode 109 at the same time (FIG. 10E). As a result, the positional relationship between the source / drain electrodes and the gate electrode is determined in a self-aligned manner.

Then, by heat treatment, dopant impurities are thermally diffused from the source and drain electrodes to the source and drain regions of the island-shaped crystalline semiconductor layer to form an ohmic contact junction, and the source and drain regions are formed. Is a low sheet resistance of the first conductivity type. This allows
The positional relationship between the source electrode and the source region and the positional relationship between the drain electrode and the drain region are determined in a self-aligning manner in a self-aligning manner. Here, the first conductivity type is
The dopant is an N-channel type or a P-channel type, and the dopant in the N-channel type is phosphorus or arsenic, and the dopant in the P-channel type is boron, gallium, indium and the like.

An offset gate type TFT can be manufactured as described above. The number of patterning masks required to manufacture a TFT having the same structure in the prior art 1 was 5, but in the method of the present invention, island-shaped semiconductor layer formation, contact hole formation, source and drain electrode and gate electrode formation are performed. There are three.

Further, in addition to the above-mentioned structure, when forming the LDD region, it is preferable to carry out by either of the following two methods.

First, in the method A, after forming the source and drain electrodes and the gate electrode at the same time, using these electrodes as a mask, an ion implantation apparatus or an ion doping apparatus is used to dope impurities of the first conductivity type. Method (FIG. 11 (F)). After that, a dopant impurity is thermally diffused from the source and drain electrodes by heat treatment to form an ohmic contact junction. At this time, the impurity concentration gradient from the high concentration impurity region of the source and drain regions to the LDD region needs to monotonically decrease. This is because if there is a high sheet resistance region between them, it is meaningless as an LDD region for the purpose of relaxing a high electric field. That is, FIG.
The region indicated by Δ in (G) is from the source and drain electrodes,
The dopant impurities must be thermally diffused. Therefore, the heat treatment temperature and time are determined under the temperature and time conditions in which the impurities can be thermally diffused so that the first conductivity type impurity concentration gradient from the source and drain regions to the LDD region monotonically decreases. In FIG. 11H, the impurity concentrations are 30, 31,
The figure shows a state in which the number decreases continuously in the order of 32 and 33.

Method B is a method of forming LDD regions by thermally diffusing dopant impurities from the source and drain regions toward the channel region of the semiconductor layer by heat treatment. At this time, the concentration distribution of the dopant impurities is determined only by thermal diffusion. Therefore, compared to method A, L
Ion implantation or ion doping steps in the DD region can be eliminated.

In either method A or method B, L is larger than in the case where the LDD region is formed by the conventional technique 2.
Variations in the DD area length can be reduced. Because the source and drain electrodes and the gate electrode are patterned at the same time, there is no relative positional deviation between the patterns due to the mask overlay error, which is a problem in Prior Art 2. In other words, in the manufacturing process of Conventional Technique 2, LD
When forming the D region, there is a variation factor of the distance between the source and drain electrodes and the gate electrode due to the mask overlay error, but in the present invention, a variation factor of the LDD region length due to the mask overlay error. Because it will disappear. Also, P or B in the doped silicon
When the impurities are diffused into the active layer, there is an advantage that the impurity region and the concentration are well controlled because they are not alloyed with silicon unlike aluminum.

To summarize the advantages of the present invention as compared with the prior art, (1) the source (drain) region and the source (drain) electrode pattern do not require mask overlay accuracy (they can be formed in self-alignment). . (2) Since the formation of the source and drain electrodes and the gate electrode (film formation / exposure / dry etching) is performed collectively, the number of steps is reduced. Further, there is no mask overlay error between the gate electrode pattern and the source and drain electrode patterns. (3)
A low sheet resistance is realized by diffusing the dopant in the doped silicon wiring into the silicon layer in the source and drain regions by heat treatment. It does not require patterning of the N + doped region and doping process using a doping device. (4) The impurity diffusion distance due to the heat treatment depends on the impurity concentration in the doped silicon and the impurity concentration in the active layer,
Determined by crystallinity and heat treatment temperature / time. At this time,
Since the gate electrode pattern and the source and drain electrode patterns can be formed in a self-aligned manner, the variation in LDD region length between the substrates can be reduced as compared with the prior art 2.

According to the present invention, the number of masks can be reduced by 2 in the present invention, so that the number of steps can be reduced, the probability of defective products can be reduced, and the product yield can be improved. A method for manufacturing a semiconductor device can be provided. Further, in the present invention, the source (drain)
A semiconductor device in which a source (drain) electrode pattern position with respect to a region can be determined in a self-aligned manner and an LDD region variation caused by a mask overlay error can be reduced by determining the LDD region in a self-aligned manner. A manufacturing method can be provided.

[0038]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will now be described in detail with reference to the drawings. As shown in FIG. 10A, a base insulating film 102 having a thickness of 10 nm to 1000 nm and a semiconductor film 103 having a thickness of 30 nm to 800 nm are formed over a substrate 101. As the substrate 101, a quartz substrate, a silicon substrate, or a stainless substrate can be used. As the base insulating film 102, a silicon oxide film, a silicon nitride film,
Any of silicon oxynitride films may be used, and two or more kinds of these films may be combined to form a laminated structure.
When manufacturing a TFT structure on a silicon substrate or a stainless substrate, a base insulating film is essential. The base insulating film is formed by preventing heat diffusion of impurities (alkali metal or heavy metal) in the substrate to the semiconductor layer of the active layer by heat treatment during the process, or by deforming (warping or waviness) of the substrate. It also has an effect of relaxing the generated stress acting on the active layer. On the other hand, when a quartz substrate is used, the impurity concentration in the substrate is originally low and
Since it also has heat resistance of about 000 ° C., the semiconductor film may be directly formed on the substrate without forming the base insulating film. As a film forming method, a sputtering method, plasma CVD
The film may be formed by a known method such as a CVD method or an LPCVD method.

The semiconductor film 103 may be any of a silicon film, a germanium film, and a silicon germanium film, and is a sputtering method, a plasma CVD method, an LPCVD method.
The film may be formed by a known method such as a method. At the stage of forming these films, they have either an amorphous structure, a polycrystalline structure, or a microcrystalline structure.

Next, the semiconductor film 103 is crystallized (or recrystallized) by a known method. Typical examples of the crystallization method include solid phase crystal growth by heat treatment in an electric furnace or RTA, and laser crystallization in which a pulsed or continuous wave gas laser or solid laser is irradiated. There is also a solid phase crystal growth method that utilizes a catalytic element.

When a catalytic element is used, it is disclosed in JP-A-7-130.
It is desirable to use the techniques disclosed in Japanese Patent No. 652 and Japanese Patent Laid-Open No. 8-78329. In this method, solid phase crystallization is performed using Ni after forming the semiconductor film 103. For example, when the technique disclosed in JP-A-7-130652 is used, a nickel acetate salt solution containing nickel in an amount of 5 to 100 ppm by weight is applied to the amorphous semiconductor film by spin coating to form a nickel-containing layer. Forming a 500
After the dehydrogenation process for 1 hour at 500 ° C., the temperature at 4 to 500 ° C. to 650 ° C.
Crystallization is performed by performing heat treatment for 12 hours, for example, at 550 ° C. for 8 hours. The usable catalytic element is nickel (Ni).
Besides, germanium (Ge), iron (Fe), palladium (Pd), tin (Sn), lead (Pb), cobalt (Co), platinum (Pt), copper (Cu), gold (Au), You may use such an element.

However, the polycrystalline semiconductor film obtained by crystallization using the catalytic element contains the catalytic element, and if it is used as it is as the active layer of the TFT, the off-leak current may increase. Therefore, it is necessary to perform a step (gettering) of removing the catalytic element from the crystalline semiconductor film after crystallization. Gettering is disclosed in JP-A-10-13546.
No. 8, JP-A-10-135469, or JP-A-10-135469.
The method disclosed in JP-A-270363 can be used.

After the above-mentioned crystallization, in order to improve the crystallinity of the semiconductor film, it is desirable to perform heat treatment after forming an insulating film on the semiconductor film to thermally oxidize the upper part of the semiconductor layer. For example, a 20 nm silicon oxide film is formed by a low pressure CVD apparatus, and then heat treatment is performed in a furnace annealing furnace. By this treatment, the upper part of the semiconductor layer is oxidized.
Then, the silicon oxide film and the oxidized portion of the semiconductor layer are wet-etched with a hydrofluoric acid-based chemical solution to obtain a semiconductor layer with improved crystallinity.

Then, a semiconductor film is formed on the island-shaped semiconductor layer 104 by patterning by photolithography and dry etching.

Next, the gate insulating film 105 of the transistor
To form. The gate insulating film 105 is an insulating film containing silicon with a film thickness of 20 to 150 nm formed by a known method such as an LPCVD method, a plasma CVD method, or a sputtering method. As the insulating film containing silicon, there are a silicon oxide film, a silicon oxynitride film, and a silicon nitride film, and a laminated structure of two or more of these may be used.
(Figure 10 (B))

Further, in order to improve the electric characteristics of the gate insulating film, after the gate insulating film 105 is formed, the temperature is 700 ° C. to 11 ° C. in an inert atmosphere or an atmosphere containing oxygen.
High temperature heat treatment at 00 ° C may be performed. As a result, the insulation resistance of the gate insulating film is increased, the fixed charges in the film are reduced, and the interface state density at the interface with the semiconductor film can be expected to be reduced.

After patterning by photolithography, the gate insulating film 105 on the source and drain regions of the semiconductor layer is etched to form a contact hole (FIG. 10C). Next, a film thickness of 100 to 500
A conductive film 106 having a heat resistance of nm is formed (FIG. 10).
(D)). A crystalline doped silicon film or a doped silicon germanium film is used as the conductive film. These films can be formed by the LPCVD method. Further, a doped silicon film (or a doped silicon germanium film) is laminated to form a doped silicon germanium film, a silicide film, Ta, W, Ti, Al, Mo, C.
A conductive film can be formed by forming a film containing an element selected from u, Cr, and Nd as a main component. However,
At a minimum, the layer that directly contacts the source and drain regions must be a crystalline doped silicon layer or a doped silicon germanium layer. Impurities in the doped silicon film or the doped silicon germanium film are Group 15 elements such as phosphorus and arsenic when manufacturing an N-channel transistor, and boron and boron when manufacturing a P-channel transistor. It is a Group 13 element such as gallium and must be contained at a concentration of 1 × 10 ¹⁹ cm ⁻³ or more.

Next, after forming a resist mask by photolithography, the source electrode 1 is etched.
08, the drain electrode 107 and the gate electrode 109 are simultaneously formed. As a result, the positional relationship between the source / drain electrodes and the gate electrode is determined in a self-aligned manner (FIG. 10E).

Here, when forming the LDD region,
Impurity doping can be performed by ion doping or ion implantation. Since the source and drain electrodes and the gate electrode serve as a doping mask, the LDD regions are selectively doped and the low concentration impurity regions 110 and 1 are formed.
11 can be manufactured (FIG. 11 (F)). This step may be omitted if it is not necessary to form the LDD region. In that case, the TFT has an offset gate structure.

Next, a first interlayer insulating film 112 is formed so as to cover the electrodes and wirings 107 to 109. The first interlayer insulating film 112 may be formed of an insulating film containing silicon with a thickness of 50 to 200 nm by a known film forming method such as a plasma CVD method, a sputtering method, or an LPCVD method. This interlayer insulating film is formed in order to prevent the surface of the gate wiring and the source and drain wiring from being oxidized and the wiring resistance from increasing during the heat treatment in the next step.

Then, heat treatment is performed to thermally diffuse the dopant impurities from the source and drain electrodes to the source and drain regions of the island-shaped crystalline semiconductor layer to form an ohmic contact junction and to form the source and drain. The region has a low sheet resistance of the first conductivity type (see FIG. 11).
(H)). As a result, the positional relationship between the source electrode and the source region and the positional relationship between the drain electrode and the drain region are determined in a self-aligning manner.

The heat treatment is carried out in an electric furnace at 800 ° C. to 1050 ° C. for 30 minutes in an inert atmosphere such as nitrogen.
It may be done in 6 hours.

The heat treatment temperature and time for obtaining the desired impurity concentration gradient (thermal diffusion length) vary depending on the crystallinity of the active layer, the impurity concentration of the doped silicon of the electrode, etc., and therefore the optimum conditions should be set. There is a need to. In the present invention, since the thermal diffusion length of the impurities is controlled while the positional relationship between the source / drain electrodes and the gate electrode is determined in a self-aligning manner, once the optimum conditions are obtained, the impurity introduction region is set. Can be determined with good controllability. It is also possible to fabricate the LDD region only by thermal diffusion. Further, the heat treatment at this time can also activate the impurities.

[0054]

[Embodiment 1] In this embodiment, a method for manufacturing an active matrix substrate will be described with reference to FIGS. In this specification, the pixel portion TFT, the storage capacitor, and
A substrate formed with the drive circuit TFT provided around the pixel portion on the same substrate is called an active matrix substrate for convenience.

As the substrate 501, a quartz substrate, a single crystal silicon substrate, a metal substrate or a stainless steel substrate having an insulating film formed on its surface is used. In this embodiment, a case where a quartz glass substrate is used as an active matrix substrate for incorporation in a projector which is a kind of liquid crystal display device is shown.

A lower light-shielding film is formed on the quartz substrate 501. The lower light-shielding film is formed to have a film thickness of about 300 nm by a conductive material containing Ta, W, Cr, Mo, Si or the like as a main element, a single layer structure using silicide, or a laminated structure thereof. This lower light-shielding film also has a function as a gate wiring. In this embodiment, a film thickness of 7 is formed by the LPCVD method.
A polycrystalline silicon film of 5 nm is formed, and then WSix (x = 2.0 to 2.8) having a film thickness of 150 nm is laminated by a sputtering method, followed by patterning by a photolithography method, and etching an unnecessary portion. Then, 502 in FIG.
And a lower light-shielding film is formed as indicated by 503.

Then, the substrate 501 and the lower light shielding film 503
An insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film has a thickness of 10 to 650 nm (preferably 5 nm).
A base film 504 of 0 to 600 nm) is formed. Further, the base film 504 may have a structure in which two or more insulating films are stacked instead of a single-layer structure. In this embodiment, the base film 504
As the silicon oxynitride film 504 (composition ratio Si = 32%, O = 59%, N = 7) having a film thickness of 580 nm formed by using a plasma CVD method with SiH ₄ and N ₂ O as reaction gases.
%, H = 2%).

Next, a semiconductor film 505 is formed on the base film 504.
To form. As the semiconductor film 505, an amorphous silicon film or an amorphous silicon germanium film is formed to a thickness of 25 to 80 nm (preferably 30 to 60 nm) by a known means (a sputtering method, an LPCVD method, a plasma CVD method, or the like). Form. In this embodiment, an amorphous silicon film having a thickness of 53 nm is formed by the LPCVD method.

Then, crystallization is performed. In the example, the crystallization method using a metal catalyst such as nickel is performed to crystallize the semiconductor film. In addition to the crystallization method using a catalyst such as nickel, a known laser crystallization method or thermal crystallization method may be used. Further, these crystallization methods may be combined. In this embodiment, Japanese Patent Laid-Open No. 7-
The technique disclosed in Japanese Patent No. 130652 is used. A nickel acetate salt solution containing 10 ppm by weight of nickel is applied to the amorphous semiconductor film to form a nickel-containing layer, and the dehydrogenation process is performed at 500 ° C. for 1 hour.
Crystallization is performed by performing heat treatment at 0 ° C. for 4 to 12 hours, for example, 550 ° C. for 8 hours. In addition to nickel (Ni), usable catalyst elements are germanium (Ge), iron (F).
e), palladium (Pd), tin (Sn), lead (P
b), cobalt (Co), platinum (Pt), copper (Cu),
An element such as gold (Au) may be used.

When the laser crystallization method is also applied, a pulse oscillation type or continuous emission type excimer laser, a YAG laser, a YVO ₄ laser or the like can be used. When these lasers are used, it is preferable to use a method in which laser light emitted from a laser oscillator is linearly condensed by an optical system and irradiated onto a semiconductor film. The crystallization conditions are appropriately selected by the practitioner. When an excimer laser is used, the pulse oscillation frequency is 300 Hz and the laser energy density is 100 to 800 mJ / cm ² (typically 300
~ 600 mJ / cm ² ). When a YAG laser is used, its second harmonic is used to generate pulse oscillation frequencies 1 to 3.
Laser energy density of 300 to 10 Hz
It is good to set it to 00 mJ / cm ² (typically 350 to 800 mJ / cm ² ). And a width of 100 to 1000 μm, for example 400 μm
It is also possible to irradiate a laser beam linearly condensed at m over the entire surface of the substrate and set the overlapping ratio (overlap ratio) of the linear beams at this time to 50 to 98%.

Then, gettering is performed in order to remove or reduce the metal element used for promoting crystallization from the semiconductor layer used as the channel region of the transistor. Regarding gettering, JP-A-10-1354
No. 68, JP-A-10-135469, JP-A-10-270363, or the like may be applied. In this embodiment, a silicon oxide film having a film thickness of 50 nm is formed as a mask and patterned to obtain silicon oxide films 507a to 507c having a desired shape. Then, an element belonging to Group 15 (typically P (phosphorus)) is selectively introduced into the semiconductor film to form the impurity region 508.
a to 508e are formed. Note that the impurity element may be introduced by one or a plurality of methods selected from a plasma doping method, an ion implantation method, and an ion shower doping method.

550 to 800 in a nitrogen atmosphere
Heat treatment is performed at 5 ° C. for 5 to 24 hours, for example, 600 ° C. for 12 hours. Then, since the phosphorus-doped regions 508a to 508e of the polycrystalline semiconductor film are regions having higher solid solubility of the catalytic metal than the non-doped regions, they function as gettering sites. By the heat treatment, the catalytic metal existing in the polycrystalline semiconductor film can be thermally diffused to the region to which phosphorus is added and segregated. As a result, TF
The concentration of the catalytic element in the channel region of T is 1 × 10 ¹⁷ atoms /
It is possible to obtain a semiconductor film in which the content is reduced to cm ³ or less, preferably to about 1 × 10 ¹⁶ atoms / cm ³ . Since the TFT manufactured in this manner has good crystallinity, high field-effect mobility can be obtained, the off-state current value can be reduced, and favorable transistor characteristics can be achieved.

After crystallization as described above, it is desirable to perform sacrificial oxidation in order to improve the crystallinity of the semiconductor film. After the insulating film is formed over the semiconductor film, heat treatment is performed to thermally oxidize the upper portion of the semiconductor layer. For example, reduced pressure CV
After forming a 20 nm silicon oxide film with the D device, heat treatment is performed in an electric furnace. By this treatment, the upper part of the semiconductor layer is oxidized. Then, the silicon oxide film and the oxidized portion of the semiconductor layer are wet-etched with a hydrofluoric acid-based chemical solution to obtain a semiconductor layer with improved crystallinity.

Further, the channel region may be doped with an impurity element (boron or phosphorus) in order to control the threshold value of the TFT. In that case, the doping process step can be performed at any step from the step of forming the semiconductor film to the step of forming the gate electrode film.
Further, it is also possible to introduce a dopant gas of B ₂ H ₆ or PH ₃ when forming a semiconductor film by the PCVD method or the LPCVD method.

Then, the crystalline semiconductor film is patterned by photolithography and then etched to form island-shaped semiconductor layers 509 to 511. (Fig. 2 (A))

Next, a gate insulating film 512 which covers the semiconductor layers 509 to 511 is formed. The gate insulating film 512 is formed of an insulating film containing silicon with a thickness of 20 to 150 nm by a plasma CVD method, an LPCVD method, or a sputtering method. In this embodiment, the thickness is 80 nm by the LPCVD method.
Formed with a silicon oxide film. Of course, the gate insulating film is not limited to the silicon oxide film, and another insulating film containing silicon may be used. For example, a silicon oxynitride film can be formed by a plasma CVD method using SiH ₄ and N ₂ O as reaction gases.

Then, a contact hole 513 for connecting the conductive film to the source and drain regions of the semiconductor layer.
A to 513f and a contact hole 513g for connecting the conductive film and the lower light-shielding film 503 are formed. Next, a conductive film 514 with a thickness of 100 to 500 nm is formed. In this embodiment, the film forming temperature is 640 ° C. and the pressure is 0.15.
Torr, SiH ₄ flow rate 200 sccm, PH ₃ flow rate 80
By forming the film under the condition of sccm, 1.5 × 10 ²⁰ cm
A polycrystalline doped silicon film containing ^-3 phosphorus is formed.

Although the conductive film 514 is made of phosphorus-doped silicon in this embodiment, it may be made of a phosphorus-doped silicon germanium film. Further, it may have a laminated structure of two or more layers. In that case, a silicide film or Ta, W, Ti, Mo, Cu, Cr, N is formed on the phosphorus-doped silicon (or phosphorus-doped silicon germanium) film.
An element selected from d or an alloy material or a compound material containing the element as a main component is formed into a stacked film. Also, A
A gPdCu alloy may be used. Alternatively, a three-layer structure in which a conductive film having low heat resistance such as Al is sandwiched between conductive films having high heat resistance may be used.

Next, the resist mask is patterned by using the photolithography method, and an etching process for forming electrodes and wirings is performed. In this embodiment, ICP (Inductively Coupled Plasma:
(Inductively coupled plasma) etching method, CF ₄ , Cl ₂ and O ₂ are used as etching gases, the flow rate ratio of each gas is set to 25:25:10 (sccm), and the coil type electrode is applied at a pressure of 1 Pa. RF (13.56 MHz) power of 500 W was applied to the substrate to generate plasma for etching.
150W RF (13.56MH) on the substrate side (sample stage)
z) Apply power and apply a substantially negative self-bias voltage. Thus, the gate electrodes 515, 516, 517,
Source and drain electrodes 518-522 are formed simultaneously.

FIG. 5 shows a top view of the state manufactured up to this point. The same reference numerals are used for corresponding parts in FIGS. The chain line AA ′ in FIG.
It corresponds to the cross-sectional view taken along the chain line AA ′.

Here, when manufacturing a TFT having an LDD region, phosphorus or arsenic, which is an n-type impurity element, is doped by an ion doping method or an ion implantation method.
The dose amount when introducing the impurity element is 1 × 10 ^{13 to} 5
The acceleration voltage is set to × 10 ¹⁴ / cm ² and the acceleration voltage is set to 5 to 80 keV. In this embodiment, the dose amount is 4.6 × 10 ¹³ / cm 3.
² and the acceleration voltage is set to 60 keV. At this time,
Since the gate electrode and the source and drain electrodes serve as a doping mask, the low-concentration impurity regions 524a-5
24d is formed, and in this region, 1 × 10 ¹⁸ to 1 × 10
^The phosphorus atoms will be doped in the concentration range of ²⁰ / cm ³ .

Next, a first interlayer insulating film 525 is formed so as to cover the electrodes and wirings 515 to 523. As the first interlayer insulating film 525, a silicon oxynitride film with a thickness of 100 nm formed by a plasma CVD method is used. This interlayer insulating film is formed in order to prevent the surface of the gate wiring, the source and drain wirings from being oxidized during the heat treatment of the next step.

Then, heat treatment is performed to thermally diffuse the dopant impurities from the source and drain electrodes into the source and drain regions of the island-shaped crystalline semiconductor layer to form an ohmic contact junction, and to form the source and drain. The regions 526 to 531 have a low sheet resistance of the first conductivity type (FIG. 3A). As a result, the positional relationship between the source electrode and the source region and the positional relationship between the drain electrode and the drain region are determined in a self-aligning manner.

The heat treatment conditions in this embodiment are as follows: vertical diffusion furnace, nitrogen atmosphere with oxygen concentration of 1 ppm or less,
The temperature was 950 ° C. for 30 minutes. It is necessary to determine the present processing conditions so that the impurities diffuse until the high resistance region disappears from the source and drain electrodes to the LDD region. FIG. 15 shows the drain current of the TFT manufactured by changing the heat treatment conditions and the distance between the contact end and the LDD region (the distance corresponding to Δ in FIG. 11G).
If there is a high resistance region between the source and drain electrodes and the LDD region, a series resistance will occur and the drain current will decrease. From the data in FIG. 15, when the distance between the contact end and the LDD is 0.8 μm or less, a sufficient drain current is obtained by performing heat treatment at 950 ° C. for 30 minutes, and between the source and drain electrodes and the LDD region. Indicates that there is no high resistance region.

The heat treatment temperature and time for obtaining the target impurity concentration gradient (thermal diffusion length) vary depending on the crystallinity of the active layer, the impurity concentration of the doped silicon of the electrode, etc., and therefore the optimum conditions should be set. There is a need to. In the present invention, since the thermal diffusion length of the impurities is controlled while the positional relationship between the source / drain electrodes and the gate electrode is determined in a self-aligning manner, once the optimum conditions are obtained, the impurity introduction region is set. Can be determined with good controllability. It is also possible to fabricate the LDD region only by thermal diffusion. Further, the heat treatment at this time can also activate the impurities.

Further, in an atmosphere containing 3% hydrogen, 35
Heat treatment is performed at 0 ° C. for 1 hour. It is considered that this hydrogenation treatment terminates grain boundaries and intragranular defects in the polycrystalline silicon layer, and dangling bonds at the interface with the gate insulating film. It has been known that the hydrogenation treatment significantly improves TFT characteristics such as a reduction in subthreshold coefficient and a reduction in off leak current. As a hydrogenation means, plasma hydrogenation (using hydrogen excited by plasma) or 30 in an atmosphere containing 3 to 100% hydrogen is used.
The heat treatment may be performed at 0 to 450 ° C. for 1 to 12 hours.

Then, a second interlayer insulating film 532 made of an inorganic insulating film material or an organic insulating material is formed on the first interlayer insulating film 525. At this time, it is preferable that the drain wiring and the upper light-shielding film that will be formed in a later step, which form the storage capacitor, are formed in parallel because the storage capacitor becomes larger. Therefore, it is desirable that the second interlayer insulating film 532 be a film whose surface is as flat as possible. A known technique for improving the flatness of the surface, for example, a polishing process called CMP (Chemical Mechanical Polishing) may be used. Furthermore, the capacitance can be increased when the distance between one electrode and the other electrode of the storage capacitor is shorter. Therefore, it is desirable that the surface of the second insulating film and the drain wiring be made as close to each other as possible by further performing an etchback process or a polishing process after forming the insulating film having flatness. At this time, it is desirable to expose the first interlayer insulating film 525 formed on the drain wiring. The capacitance also increases in proportion to the dielectric constant of the dielectric. Therefore, if the first interlayer insulating film is formed of a film having a higher dielectric constant than the second interlayer insulating film, the storage capacitance formed by the drain wiring, the interlayer insulating film and the upper light shielding film should be further increased. Is possible. In this embodiment, an acrylic resin film with a thickness of 1 μm is formed as the second interlayer insulating film 532, and etching is performed to form the first interlayer insulating film 525 formed over the gate electrode, the source wiring, and the drain wiring. Is exposed and the surface is flattened by the first interlayer insulating film and the second interlayer insulating film.

In this embodiment, the first interlayer insulating film and the second interlayer insulating film are formed, but of course, a single layer structure may be used. Even in this case, it is desirable to use a film having a flat surface.

Then, A is formed on the second interlayer insulating film 532.
The upper light-shielding film 53 is formed by patterning a film having a high light-shielding property such as 1, Ti, W, Cr, or black resin into a desired shape.
3 is formed. The light-shielding film 533 is arranged in a mesh shape so as to shield the portions other than the openings of the pixels from light. (Fig. 3 (B))

FIG. 6 shows a top view of the state manufactured up to this point. The same reference numerals are used for corresponding parts in FIGS. The chain line AA ′ in FIG.
It corresponds to the cross-sectional view taken along the chain line AA ′.

Further, a third interlayer insulating film 534 is formed of an inorganic insulating material or an organic insulating material so as to cover the upper light shielding film 533. The third interlayer insulating film 53 is formed in order to make a sufficient storage capacitor formed by the upper light-shielding film, the third interlayer insulating film, and the pixel electrode formed in a later step.
4 is preferably a film whose surface is flat. Also,
After forming the insulating film, the third interlayer insulating film 534 may be formed by performing an etch back or polishing process to planarize the surface. Further, in order to increase the capacitance, it is desirable to use a film having a high dielectric constant and form the film as thin as possible.

Then, a contact hole communicating with the drain wiring 522 is formed, and a transparent conductive film such as ITO is formed to a thickness of 1.
The pixel electrode 535 is formed by patterning into a desired shape with a thickness of 00 nm.

There are two kinds of storage capacitors, one is a capacitor 536 having the upper light-shielding film 533 and the pixel electrode 535 as electrodes and the third interlayer insulating film 534 as a dielectric, and the other is the upper light-shielding film. A capacitor 537 having the film 533 and the drain wiring 522 as electrodes and the first interlayer insulating film 525 as a dielectric.
Is. This embodiment shows a method capable of ensuring a sufficient capacity without increasing the number of steps.

FIG. 7 shows a top view of the state manufactured up to this point. The same reference numerals are used for the parts corresponding to FIGS. A chain line AA 'in FIG. 4 is a chain line A- in FIG.
It corresponds to the cross-sectional view cut at A ′.

As described above, the active matrix substrate in which the driving circuit 555 for the n-channel TFT, the n-channel pixel TFT 553, and the storage capacitors 536 and 537 are formed on the same substrate is completed.

[Embodiment 2] In Embodiment 1, the lower light-shielding film was used as the gate line, but in this embodiment, there is no lower light-shielding film and the upper light-shielding film is used as the gate line. Explain. Since the active matrix substrate manufactured in this embodiment is inferior in light-shielding property to the first embodiment, it is desirable to incorporate it in a liquid crystal display device such as a viewfinder.

As the substrate 601, a quartz substrate, a single crystal silicon substrate, a metal substrate or a stainless substrate having an insulating film formed on its surface is used. Then, a film thickness of 10 to 650 nm (preferably 50 to 6) made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed on the substrate 601.
A base film 602 having a thickness of 00 nm is formed.

Next, a semiconductor film is formed on the base film 602. As the semiconductor film 505, an amorphous silicon film is formed by a known method (a sputtering method, an LPCVD method, or a plasma CVD method).
Method, etc., 25-80 nm (preferably 30-60)
nm).

The steps from the formation of the amorphous silicon to the flattening of the second interlayer insulating film are the same as those in the first embodiment, and the description thereof will be omitted. (Figure 14 (A))

The second interlayer insulating film 621 is patterned and etched to form a contact hole leading to the gate wiring 620, and a light-shielding conductive film having a thickness of 100 nm is formed.
To form a film. As the light-shielding conductive film, Al, Ti,
A film having a high light-shielding property and conductivity such as W or Cr is used. The light-shielding conductive film is patterned into a desired shape to form the upper light-shielding film and the gate line 614.

Further, a third interlayer insulating film 615 is formed of an inorganic insulating material or an organic insulating material so as to cover the upper light shielding film 614. The third interlayer insulating film 61 is formed in order to make a sufficient storage capacitor formed by the upper light-shielding film, the third interlayer insulating film, and the pixel electrode formed in a later step.
5 is preferably a film whose surface is flat. Also,
After forming the insulating film, the surface may be flattened by performing etch back or polishing process. Further, in order to increase the capacitance, it is desirable to use a film having a high dielectric constant or to form the film as thin as possible.

Then, a contact hole communicating with the drain wiring 607 is formed, and a transparent conductive film such as ITO is formed to a thickness of 1.
The pixel electrode 616 is formed by forming the pixel electrode 616 with a thickness of 00 nm and patterning into a desired shape.

The storage capacitor is the upper light-shielding film (gate line).
The capacitor 617 has the electrodes 614 and the pixel electrodes 616 as electrodes and the third interlayer insulating film 615 as a dielectric.

As described above, the active matrix substrate in which the driving circuit 666 of the n-channel type TFT and the pixel portion 663 having the n-channel type pixel TFT and the storage capacitor are formed on the same substrate is completed.

[Embodiment 3] In this embodiment, a process of manufacturing a transmissive liquid crystal display device from the active matrix substrate manufactured in Embodiment 1 will be described below. Figure 12
To use.

First, according to the first embodiment, after obtaining the active matrix substrate in the state of FIG. 4, an alignment film 567 is formed on the active matrix substrate and at least on the pixel electrode 535, and a rubbing process is performed. In this embodiment, before forming the alignment film 567, an organic resin film such as an acrylic resin film is patterned to form columnar spacers (not shown) for holding the substrate distance at desired positions. . Further, spherical spacers may be dispersed over the entire surface of the substrate instead of the columnar spacers.

Next, the counter substrate 569 is prepared. Then, the colored layer 570 and the planarization film 573 are formed over the counter substrate 569.
To form. A counter electrode 576 made of a transparent conductive film is formed at least in the pixel portion over the planarization film 573, an alignment film 574 is formed over the entire surface of the counter substrate, and rubbing treatment is performed.

Then, a sealing material 568 is formed between the active matrix substrate on which the pixel portion and the driving circuit are formed and the counter substrate.
Stick together. A filler is mixed in the sealing material 568, and the two substrates are bonded to each other with a uniform interval by the filler and the columnar spacers. afterwards,
A liquid crystal material 575 is injected between both substrates and completely sealed with a sealant (not shown). A known liquid crystal material may be used as the liquid crystal material 575. Thus, the transmissive liquid crystal display device shown in FIG. 12 is completed. Then, if necessary, the active matrix substrate or the counter substrate is cut into a desired shape. Further, a polarizing plate (not shown) was attached only to the counter substrate. Then, using a known technique, F
I stuck a PC. The liquid crystal display device manufactured as described above can be manufactured.

Note that this embodiment can be freely combined with any one of Embodiments 1 and 2.

[Example 4] The present invention was applied to produce
The driver circuit and the pixel portion transistor can be used in an electro-optical device typified by an active matrix liquid crystal display device. That is, the present invention can be implemented in all electronic devices in which the electro-optical device is incorporated in the display section.

Examples of such electronic equipment include projectors. As an example, it is shown in FIG.

FIG. 13A shows a front type projector including a projection device 3601, a screen 3602 and the like. The present invention can be applied to the liquid crystal display device 3808 which constitutes a part of the projection device 3601 and other drive circuits.

FIG. 13B shows a rear type projector, which includes a main body 3701, a projection device 3702, and a mirror 370.
3, screen 3704 and the like. The present invention is a projection device 2
The invention can be applied to the liquid crystal display device 3808 which forms a part of 702 and other driver circuits.

Note that FIG. 13C is a diagram showing an example of the structure of the projection devices 3601 and 3702 in FIGS. 13A and 13B. Projection devices 3601, 37
02 is a light source optical system 3801, mirrors 3802, 380
4 to 3806, dichroic mirror 3803, prism 3807, liquid crystal display device 3808, retardation plate 380.
9, a projection optical system 3810. Projection optical system 28
Reference numeral 10 is composed of an optical system including a projection lens. Although the present embodiment shows an example of a three-plate type, it is not particularly limited and may be, for example, a single-plate type. In addition, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting the phase difference, and an IR film in the optical path indicated by the arrow in FIG. 13C. Good.

FIG. 13D is a diagram showing an example of the structure of the light source optical system 3801 in FIG. 13C. In this embodiment, the light source optical system 3801 includes the reflector 3811, the light source 3812, the lens arrays 3813, and 3.
814, a polarization conversion element 3815, and a condenser lens 3816. The light source optical system shown in FIG. 13D is an example and is not particularly limited. For example, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, and an IR film in the light source optical system.

[0106]

By adopting the constitution of the present invention, the following significant effects can be obtained. (A)
It is possible to reduce the number of processes. (B) The mask overlay accuracy of the source (drain) region and the source (drain) electrode pattern is not required (it can be formed in self-alignment). (C) Since the source / drain electrodes and the gate electrodes are formed (film formation / exposure / dry etching) at the same time, the number of steps is reduced. Further, there is no mask overlay error between the gate electrode pattern and the source and drain electrode patterns. As a result, variations in LDD region length can be reduced. (D) A low sheet resistance is realized by diffusing the dopant in the doped silicon wiring into the silicon layers in the source and drain regions by heat treatment. The patterning of the high-concentration impurity doping region and the doping process using the doping apparatus are not required. (E) In addition to satisfying the above advantages, in a semiconductor device typified by an active matrix type liquid crystal display device, it is possible to improve the operating characteristics and reliability of the semiconductor device and improve the yield. Further, it is possible to reduce the manufacturing cost of the semiconductor device.

[Brief description of drawings]

1A to 1C are cross-sectional views illustrating a manufacturing process of a TFT described in Embodiment 1.

2A to 2C are cross-sectional views illustrating a manufacturing process of a TFT described in Embodiment 1.

3A to 3C are cross-sectional views illustrating a manufacturing process of a TFT described in Embodiment 1.

4A to 4C are cross-sectional views illustrating a manufacturing process of a TFT described in Embodiment 1.

FIG. 5 is a top view showing a configuration of a pixel TFT.

FIG. 6 is a top view showing a configuration of a pixel TFT.

FIG. 7 is a top view showing a configuration of a pixel TFT.

FIG. 8 is a cross-sectional view showing a TFT manufacturing process of Prior Art 1.

FIG. 9 is a cross-sectional view showing a TFT manufacturing process of Conventional Technique 2.

FIG. 10 is a cross-sectional view showing a TFT manufacturing process of the present invention.

FIG. 11 is a cross-sectional view showing a TFT manufacturing process of the present invention.

FIG. 12 is a cross-sectional view showing an active matrix liquid crystal display device shown in Embodiment 3.

FIG. 13 is a sectional view showing a projector according to a fourth embodiment.

14A to 14C are cross-sectional views illustrating a manufacturing process of a TFT described in Example 2.

FIG. 15 is a graph showing the relationship between heat treatment conditions and drain current.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 21/28 301 H01L 21/28 301R 21/285 301 21/285 301 29/78 616L 21/3205 616A 21 / 768 616U 29/786 616V 617M 21/90 C 21/88 QF term (reference) 2H092 GA11 GA59 GA60 JA24 JA41 KA02 KA15 KA16 MA02 MA14 MA20 MA41 NA27 RA05 4M104 AA01 AA02 BB01 BB02 BB13 BB14 BB16 BB01 BB17 BB17 BB17 BB17 BB17 DD02 DD09 DD16 DD17 DD18 DD43 DD65 DD78 DD92 EE06 FF02 FF13 FF22 GG09 GG10 GG14 GG20 HH15 HH20 5F033 HH03 HH07 HH08 HH11 HH17 HH19 HH21 HJ19 KK JJ JJ JJ JJ JJ JJ JJ JJ JJ JJ 20 JJ 20 JJ 20 JJ 20 JJ 21 JJ 20 JJ 20 JJ 20 JJ 04 JJ 04 JJ 04 JJ 04 JJ 04 JJ 14 JJ 20 JJ 04 JJ 04 JJ 04 JJ 14 JJ 20 JJ 20 JJ 20 NN06 PP09 PP15 QQ09 QQ10 QQ12 QQ31 QQ48 QQ73 QQ79 RR06 RR08 RR21 SS08 SS13 SS15 VV15 WW04 XX01 XX09 XX10 XX15 XX20 5F052 AA02 AA17 AA24 BA02 BA07 BB02 BB07 DA03 DB02 DB03 DB07 EA12 EA15 EA16 JA01 5F110 AA03 AA16 AA30 CC02 DD01 DD03 DD05 DD13 DD14 DD15 EE02 GG03 GG04 GG34 FF04 EE25 FF15 EE04 FF15 EE05 FF15 EE05 FF15 EE45 FF15 EE04 FF15 EE04 FF15 EE45 FF15 EE04 HJ04 HJ12 HJ13 HJ23 HK02 HK03 HK04 HK08 HK09 HK14 HK21 HK27 HK42 HL02 HL04 HL05 HL06 HL08 HL12 HL24 HM14 NN03 NN04 NN22 NN27 NN27 PP35 QPQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQ

Claims (11)

[Claims] 1. A method of manufacturing a semiconductor device formed on an insulating substrate, comprising: a first step of forming a crystalline semiconductor layer to be an active layer of a thin film transistor on the insulating substrate; A second step of forming the semiconductor layer in an island shape, a third step of forming a gate insulating film so as to cover the island crystalline semiconductor layer, and a step of forming a gate insulating film on the source and drain regions of the island crystalline semiconductor layer. Fourth step of forming a contact hole by etching the gate insulating film, and forming an impurity-doped conductor layer on the gate insulating film and on the source and drain regions of the island-shaped crystalline semiconductor layer A fifth step, a sixth step of etching the conductor layer to form source and drain electrodes and a gate electrode at the same time, and a heat treatment to remove the source and drain electrodes. , The source and drain regions of the island-like crystalline semiconductor layer, a dopant impurity is thermally diffused to form an ohmic contact junction and,
And a seventh step of making the source and drain regions of the island-shaped crystalline semiconductor layer have a low sheet resistance of the first conductivity type. 2. A method of manufacturing a semiconductor device formed on an insulating substrate, comprising: a first step of forming a crystalline semiconductor layer on the insulating substrate; and forming the crystalline semiconductor layer in an island shape. A second step of forming, a third step of forming a gate insulating film so as to cover the island-shaped crystalline semiconductor layer, and an etching process of the gate insulating film on the source and drain regions of the island-shaped crystalline semiconductor layer. And a fourth step of forming a contact hole, and a fifth step of forming an impurity-doped conductor layer on the gate insulating film and on the source and drain regions of the island-shaped crystalline semiconductor layer, A sixth step of forming a source / drain electrode and a gate electrode at the same time by etching the conductive counter layer, and using the source / drain electrode and the gate electrode as a mask,
Selectively in the island-shaped crystalline semiconductor layer in a region where the source and drain electrodes and the gate electrode do not exist immediately above,
A seventh step of ion-doping or ion-implanting impurities of the first conductivity type and a heat treatment to thermally diffuse the dopant impurities from the source and drain electrodes to the source and drain regions of the island-shaped crystalline semiconductor layer. And forming an ohmic contact junction and making the source and drain regions of the island-shaped crystalline semiconductor layer have a low sheet resistance of the first conductivity type. 3. A method of manufacturing a semiconductor device formed on an insulating substrate, comprising: a first step of forming a crystalline semiconductor layer to be an active layer of a thin film transistor on the insulating substrate; A second step of forming the semiconductor layer in an island shape, a third step of forming a gate insulating film so as to cover the island crystalline semiconductor layer, and a step of forming a gate insulating film on the source and drain regions of the island crystalline semiconductor layer. Fourth step of forming a contact hole by etching the gate insulating film, and forming an impurity-doped conductor layer on the gate insulating film and on the source and drain regions of the island-shaped crystalline semiconductor layer A fifth step, a sixth step of etching the conductor layer to form source and drain electrodes and a gate electrode at the same time, and a heat treatment to remove the source and drain electrodes. , The source and drain regions of the island-like crystalline semiconductor layer, a dopant impurity is thermally diffused to form an ohmic contact junction and,
The seventh step of setting the source and drain regions of the island-shaped crystalline semiconductor layer to a low sheet resistance of the first conductivity type, and the heat treatment to remove the island-shaped crystals from the source and drain regions of the island-shaped crystalline semiconductor layer. Eighth step of forming an LDD region by thermally diffusing a dopant impurity in the direction of the channel region of the conductive semiconductor layer. 4. The method for manufacturing a semiconductor device according to claim 1, wherein the conductor layer is formed of a doped silicon layer or a doped silicon germanium layer. 5. The layer according to claim 1, wherein the conductor layer is formed to have a laminated structure, and the layer that joins with the source and drain regions of the island-shaped crystalline semiconductor layer is doped. A method for manufacturing a semiconductor device, which comprises forming a doped silicon layer or a doped silicon germanium layer. 6. The method for manufacturing a semiconductor device according to claim 5, wherein at least one layer of the films constituting the laminated structure is formed of a silicide layer. 7. The silicide layer according to claim 6,
A method for manufacturing a semiconductor device, which is formed using any one of molybdenum silicide, tungsten silicide, titanium silicide, platinum silicide, palladium silicide, nickel silicide, and cobalt silicide. 8. The P, As, and S according to claim 1, wherein a region of the conductor layer that is joined to the source and drain regions of the island-shaped crystalline semiconductor layer is P, As, S.
At least one of b, B, Al, Ga, and In is 1 × 1
A method for manufacturing a semiconductor device, characterized in that it is contained at a concentration of 0 ¹⁹ cm ^-3 or more. 9. The first conductivity type according to claim 1, wherein the first conductivity type is an N-channel type, and
A method for manufacturing a semiconductor device, characterized in that all transistors formed on the substrate are N-channel type. 10. The first conductivity type according to claim 1, wherein the first conductivity type is a P-channel type, and all transistors formed on the substrate are P-channel type. A method for manufacturing a semiconductor device, comprising: 11. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is a front projector, a rear projector, or a viewfinder.