JPS6149423A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To ignore the superposing errors by superposing the second resist on the first resist pattern to form the prescribed figure A' larger than the prescribed figure A, treating wafer, then removing the second resist, and forming the prescribed figure B' larger than the prescribed figure B with the resist. CONSTITUTION:Patterns A-C are formed of a resist 5 on a GaAs substrate 4, a resist mask 7 of a figure A' larger than a figure A is formed, the substrate 4 is etched to remove the second mask 7. Then, the third resist mask 8 of a figure B' larger than a figure B is formed, AuGe/Au are deposited for source and drain, lifted off to form electrodes 9. Then, a resist 10 is formed, a recess region 11 is formed, aluminum is then deposited to form a gate electrode 12, and the first resist 5 is removed. According to this configuration, pattern superposing errors can be ignored in a principle to obtain a semiconductor element having accurate superposition.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device that involves a plurality of resist patterning steps and achieves highly accurate overlay.

Conventional Structures and Their Problems As semiconductor devices become more highly integrated and miniaturized, there is a need for improved overlay accuracy in pattern formation.

The conventional method for manufacturing semiconductor devices was changed to GaAs F E
The case of manufacturing a T will be explained based on the plan views of FIGS. 1a and 1b as an example. First, a resist pattern for the source/drain is formed, and the source/drain 1 is formed by vapor deposition and lift-off of AuGe/Au (see Fig. 1a).
). At that time, alignment marks 2 for the next patterning are formed. Next, while overlapping using the alignment mark 2, a gate pattern 3 is placed between the source and drain 1.
(Fig. 1b). What becomes a problem at this time is the superposition of the gate pattern 3 on the source/drain 1. As the miniaturization of semiconductor devices progresses, there is a demand for improved overlay accuracy. However, there is a limit to the improvement in overlay accuracy in the method of overlapping a new notch turn on a previously provided pattern, and it is desired to improve this point and further improve overlay accuracy.

OBJECTS OF THE INVENTION The present invention is a method for manufacturing a semiconductor device that solves the above problems, and by using the present invention, highly accurate overlay can be realized.

Structure of the Invention The present invention is to form a first resist pattern consisting of a predetermined figure A and a predetermined figure B on a semiconductor substrate by one exposure and development process, and then to form a first resist pattern on the first resist pattern. , a second resist is applied, and a second resist pattern of a predetermined figure A' that is slightly larger than the predetermined figure A is formed by an exposure and development process, and then a first wafer processing process is performed, and then the second resist pattern is formed. Remove only the third resist, then apply the third resist again, expose and develop f
This is a semiconductor device manufacturing method in which a second wafer processing step is performed after forming a third resist pattern of a predetermined figure B' that is slightly larger than the predetermined figure B of the first resist pattern. , 1st
．． No pattern shift occurs due to the second wafer processing step.

DESCRIPTION OF THE EMBODIMENTS The present invention will be described in detail by taking the case of manufacturing a GaAs FET as an example and using the step-by-step sectional views shown in FIGS. 2a-j.

In the mesa etching process, source/drain formation process, and gate formation process in a GaAs FET, the mesa pattern is A, the source/drain pattern is B, and the gate pattern is C. For example, a resist agent known under the trade name 0FPR800 manufactured by Tokyo Ohka Co., Ltd. is applied to a thickness of 1 μm on the GaAs substrate 4, and prebaked at 85° C. for 20 minutes. Next, exposure is performed using an exposure mask including mesa pattern A, source/drain pattern B, and gate pattern C. For example, using a developer known as NMD-3 manufactured by Tokyo Ohka Co., Ltd. A pattern 5 is formed on the 0FPR800 resist by developing it for 1 minute. Next, the wavelength is 250 nm.

Far ultraviolet light with a light intensity of 40 mW/cA is irradiated onto the resist turn 6 for 6 minutes. Further 300°C2
Heat treatment is performed for 30 minutes. This process makes the resist pattern 6 insoluble in the developer. This cross-sectional shape is shown in FIG. Perform pre-baking (Figure 2b). Then, for the second resist 6, a pattern A' that is slightly larger than the mesasoid turn A is formed.
Exposure and development are performed using the mask, and turn 7
(Figure 2C). Here, the mesa pattern 7 may be superposed fairly loosely on the predetermined figure A, and even if the superposition of the figure A and the same figure A' changes, the actual notch turn is determined by the figure A. Does not affect turn formation. Next, using the figures A and A/ as masks, mesa etching is performed on the substrate 4 to a depth of 1 μm using a mixed solution of H2SO4/H2o2 (FIG. 2d).

After removing the remaining resist 7 using NMD-3'i or an organic solvent resist remover, 0FPRsoo resist is applied again to a thickness of 1 μm and prebaked at 86°C for 220 minutes (Figure 2e). ).

Exposure and development are performed using an exposure mask with a notch B' that is slightly larger than the source/drain pattern B, and a resist source/drain hole (turf 8) is formed (FIG. 2 f). Next, the electrode material AuGe/Au of 0.5μ
The source/drain electrodes 9 are formed by vapor deposition to a thickness of m and boiling in trichlorethylene to form source/drain electrodes 9 (Fig. 2q).Next, 0FPRsoo resist is applied again to a thickness of 1 μm. , pre-bake at 86°C for 20 minutes (Fig. 2h)
). And for this resist.

Exposure and development are performed using a notched turn C' that is slightly larger than the gate pattern C, thereby forming a gate pattern 1o having an opening of four notched turns C' (FIG. 2i). here,
The notch turn C' may be loosely overlapped with the gate notch turn C formed in advance, and the gate pattern C
The position of C with respect to the source and drain is determined in FIG. 2a and is therefore completely independent of variations in the superposition of pattern C'. A GaAg substrate is etched using a tartaric acid-based etching solution to form a recessed region 11. Finally A
Form a gate electrode using evaporation of l and lift-off (
Figure 2j).

In the above explanation, 0 is used as the resist 6 for pattern formation.
A positive electron beam resist such as PMMA may also be used for the tail using FP1't 800. In that case, deep ultraviolet light irradiation is not necessary. Note that PMMA dissolves in organic solvents, so to remove the upper layer 0FPR800,
It is necessary to use NMD-a or an alkaline developer.

Furthermore, even when there is a thin film such as an Si02 film on a GaAs substrate, except that a wet etching process for the Si02 film is added in the process shown in Figure 2a, □
The process is exactly the same as described above.

Effects of the Invention As described above in detail, by using the present invention, overlay errors can be ignored in principle, and a semiconductor element with highly accurate overlay can be realized.

[Brief explanation of drawings]

1A and 1B are plan views showing a conventional semiconductor device manufacturing method, and FIGS. 2A to 2J are step-by-step sectional views showing a semiconductor device manufacturing method according to the present invention. 1... Source/drain pattern, 2...
...Overlay mark, 3...Gate pattern, 4...GaAs substrate, 5...
・Resist pattern (A...Mesach turn, B
...Source/drain pattern, C...
gate pattern), 6, 7, 8.10...resist, 9...source/drain electrode, 11...
...Recess region, 12...Gate electrode, A
/, f3/, C'... Pattern slightly larger than patterns A, E, and C.

Claims (1)

[Claims] A first resist pattern consisting of a predetermined figure A and a predetermined figure B is formed on a semiconductor substrate by one exposure and development process, and then a second resist pattern is formed on the first resist pattern.
After applying a resist of Remove only the
A third resist is applied again, and a third resist pattern of a predetermined figure B', which is slightly larger than the predetermined figure B of the first resist pattern, is formed by an exposure and development process, and then a second wafer processing step is performed. A method for manufacturing a semiconductor device.