JPH09191018A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make the saturated drain current of each gate finger in an FET uniform, by forming a control electrode arranged in a recess pattern having a uniform depth which is formed in an active layer, in such a manner that the electrode faces, in a cross finger type, a first and a second main electrodes. SOLUTION: After an N-GaAs layer (active layer) 6 is formed on a semiinsulating GaAs substrate 5, patterning is performed by using photoresist, and a first main electrode (drain electrode) 2 and a second main electrode (source electrode) 3 are formed. In a recess 7A having a uniform depth which is formed in an active layer 6, a control electrode (gate electrode) 1 and the drain and source electrodes 2, 2 are staggered. Dummy recess patterns 8a, 8b are formed on both sides of the operating region (active layer region) of a field-effect transistor (FET). Thereby a metal gate FET wherein the saturation drain current of each gate finger in the FET is uniform can be obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, in a recess type gate FET, dummy gate patterns are provided on both sides of an FET operating portion, or a gate pattern is uniformly formed on the entire surface of a wafer. The present invention relates to a semiconductor device and a method for manufacturing the same, in which the saturated drain current value of each gate finger in the FET can be made uniform by forming a gate and using only a necessary portion as the FET.

[0002]

2. Description of the Related Art FIG. 14 shows a conventional semiconductor device, for example, a recess type gate FET having a plurality of gate fingers.
FIG. In the figure, 1 is a gate electrode as a control electrode, 2 is a drain electrode as a first main electrode, and 3 is a source electrode as a second main electrode. The gate electrode 1 is provided so as to face the drain electrode 2 and the source electrode 3 in a cross finger shape.

FIG. 15 is a sectional view showing a manufacturing process of the conventional recess type gate FET shown in FIG. Hereinafter, FIG.
The manufacturing method will be described with reference to FIG. First, FIG. 15 (a)
As shown in FIG. 15, after the n-GaAs layer (active layer) 6 is formed on the semi-insulating GaAs substrate 5 by the ion implantation method or the epitaxial crystal growth method, as shown in FIG. Patterning is performed (not shown), and the drain electrode 2 and the source electrode 3 made of AuGe-based metal are formed by the vapor deposition / lift-off method.

Next, as shown in FIG. 15 (c), patterning is performed with a photoresist 9, and the n-GaAs layer 6 is dug by wet etching using this as a mask to form a recess 7 as a first recess pattern. Form. afterwards,
As shown in FIG. 15D, the gate electrode 1 made of Al-based metal is formed on the n-GaAs layer 6 in the recess 7 by vapor deposition / lift-off method.
To form As a result, a recess type gate FET as shown in FIG. 14 can be obtained.

FIG. 16 is a diagram showing the saturated drain current value for each gate finger of the conventional recess type gate FET formed as described above, corresponding to the array thereof. FE
Due to the difference in etching rate at the time of forming the recess in each gate finger in T, the depth of the formed recess is different for each gate finger. That is, the etching rate is
Since the gate fingers tend to decrease as they become denser, if the gate fingers are dense (in FIG. 16, the central portion excluding the end portions) and the etching rate is slow, the depth of the recess 7 to be formed becomes shallow and the active layer is not formed. A certain n-GaAs layer 6 becomes thicker and the saturated drain current value for each gate finger increases, but conversely, the gate finger becomes sparse (see FIG. 16).
If the etching rate is fast at the edge), the depth of the formed recess 7 becomes deep and the thickness of the n-GaAs layer 6 which is the active layer becomes thin, and the saturated drain current value for each gate finger decreases. To do. Therefore, as shown in FIG. 16, the manufactured FET has a saturated drain current value lower in the vicinity a of both ends of the FET than in the central portion b of the FET. The nonuniformity of the saturated drain current value causes nonuniform operation of the FET during high frequency operation, which hinders performance improvement.

FIG. 17 is a diagram showing the saturated drain current value for each gate finger of FETs having different total gate widths formed in the same wafer, corresponding to the array. Here, the case where the total gate width of the FET shown in FIG. 17B is larger than the total gate width of the FET shown in FIG. 17A is shown. In this case also, for the same reason as above, FIG.
In the FET shown in FIG. 7A, the smaller the area where the gate fingers are denser, that is, the smaller the total gate width is, the more FET the area where the gate fingers are dense is shown in FIG. 17B. In comparison, the saturated drain current value per the same gate width becomes smaller.

[0007]

As described above, in the case of the conventional recess type gate FET having a plurality of gate fingers, the saturated drain current value for each gate finger is not constant and is not uniform in the FET. In addition, when FETs with different total gate widths are simultaneously formed in the same wafer, the saturated drain current value per same gate width varies depending on the total gate width. There were problems such as difficulty.

The present invention has been made in order to solve the above-mentioned conventional problems. The saturated drain current value of each gate finger in the FET is uniform, and the FETs having different total gate widths are the same. It is an object of the present invention to provide a semiconductor device having excellent high frequency characteristics in which a saturated drain current value per the same gate width is uniform even when they are simultaneously formed in a wafer, and a manufacturing method thereof.

[0009]

According to another aspect of the present invention, there is provided a semiconductor device comprising: an active layer provided on a semiconductor substrate; first and second main electrodes formed on the active layer; In the recess pattern formed with a uniform depth in the layer, the first and second main electrodes and the control electrodes provided so as to face each other in a cross finger shape are provided.

A semiconductor device according to a second aspect of the present invention is the semiconductor device according to the first aspect, wherein the semiconductor device includes a plurality of semiconductor elements including a first electrode, a second main electrode and a control electrode. The control electrodes of the device have different widths.

A semiconductor device according to a third aspect of the present invention is the semiconductor device according to the second aspect, wherein one of the plurality of semiconductor elements is used for an original operation and the other is used as a spare.

A semiconductor device according to a fourth aspect of the present invention is the semiconductor device according to the third aspect, wherein a semiconductor element for operation and a semiconductor element for backup are connected to each other for high output.

According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, which comprises a step of forming an active layer on a semiconductor substrate, a step of forming first and second main electrodes on the active layer, and a step of forming an active layer on the active layer. It includes a step of forming the first and second recess patterns through a mask and a step of forming a control electrode in at least the first recess pattern.

A method of manufacturing a semiconductor device according to a sixth aspect of the present invention is the first and second aspects of the invention of the fifth aspect.
Of the main electrode and control electrode of the
The step of removing the portion of the active layer in which the recess pattern is formed is included.

According to a seventh aspect of the present invention, there is provided a method of manufacturing a semiconductor device, which comprises a step of forming an active layer on a semiconductor substrate,
A step of forming a first insulating film on the active layer and forming first and second recess patterns in the active layer using the first insulating film as a mask; and a step of forming a second insulating pattern on the entire surface of the wafer including the first insulating film.
And forming a side wall in the first recess pattern by etching the second insulation film, and forming a metal film on the entire surface of the wafer including the side wall.
It includes a step of processing the metal film to form a control electrode having a predetermined shape, and a step of removing the first insulating film and the side wall and forming the first and second electrodes on the active layer.

The semiconductor device manufacturing method according to an eighth aspect of the present invention is the method according to the seventh aspect of the present invention.
Of the main electrode and the control electrode are removed to remove the portion of the active layer in which the second recess pattern is formed.

According to a ninth aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the fifth aspect, wherein the first layer on the active layer is the first layer.
And the second main electrode, the control electrode in the first recess pattern and at least the second recess pattern are continuously formed on the entire surface of the wafer, and the active layer portion where the second recess pattern is formed is formed. It is removed to form a plurality of semiconductor elements.

According to a tenth aspect of the present invention, in the method of manufacturing a semiconductor device according to the seventh aspect, the control electrode having a predetermined shape in the first recess pattern and the first layer on the active layer are formed.
And a second electrode are continuously formed on the entire surface of the wafer, and a portion of the active layer in which the second recess pattern is formed is removed to form a plurality of semiconductor elements.

The method of manufacturing a semiconductor device according to an eleventh aspect of the present invention is the method according to the ninth or tenth aspect of the present invention, wherein a part of the control electrodes forming the plurality of semiconductor elements is used for current value monitoring during recess current adjustment. It is used as a TEG.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to the drawings. Embodiment 1 FIG. In the present embodiment, the present invention is applied to a recess type Al as a semiconductor device having a plurality of gate fingers.
A case where the present invention is applied to a metal-based gate FET will be described. FIG. 1 is a plan view showing a recess type Al-based metal gate FET having a plurality of gate fingers according to the present embodiment. In FIG. 1, parts corresponding to those in FIG. 14 are designated by the same reference numerals, and detailed description thereof will be omitted. In the figure, 4a,
4b is a dummy gate electrode, 7A is a recess, and 8a and 8b are F.
The dummy recess patterns are arranged on both sides of the ET operation region (active layer region) and serve as a second recess pattern for substantially absorbing variations in the saturated drain current value during recess formation. As will be described later, the dummy gate patterns 4a and 4b are formed on the dummy recess patterns 8a and 8b, respectively.
Is formed.

FIG. 2 shows the recess type Al-based metal gate FE of FIG.
FIG. 6 is a cross-sectional view showing the manufacturing process of T. Hereinafter, the manufacturing method will be described with reference to FIG. First, as shown in FIG. 2A, an n-GaAs layer (active layer) 6 is formed on a semi-insulating GaAs substrate 5 by an ion implantation method or an epitaxial crystal growth method, and then, as shown in FIG. As shown, patterning is performed with a photoresist (not shown), and the drain electrode 2 and the source electrode 3 made of AuGe-based metal are formed by the vapor deposition / lift-off method.

Next, as shown in FIG. 2C, patterning is performed with a photoresist 9 and the n-GaAs layer 6 is dug by wet etching using this as a mask to form a recess 7
A and dummy recess patterns 8a and 8b as second recess patterns are formed. After that, as shown in FIG. 2D, the gate electrode 1 and the dummy gate electrode 4 made of Al-based metal are formed on the n-GaAs layer 6 in the recess 7A and the dummy recess patterns 8a and 8b by the vapor deposition / lift-off method. To form. As a result, a recess type Al-based metal gate FET as shown in FIG. 1 can be obtained.

FIG. 3 is a diagram showing the saturated drain current value for each gate finger of the recess type Al-based metal gate FET in the present embodiment formed as described above, corresponding to the array. By providing dummy recess patterns in which dummy gate electrodes 4a and 4b are formed on both sides of the FET operation region (active layer region) as shown in FIG. 1, the original gate electrode 1 is formed as shown in FIG. This dummy recess pattern substantially absorbs the variation in the saturated drain current value at the time of forming the recess near both ends of the recess pattern c, and only the region where the current value is uniform (hatched portion in the figure) is used as the FET operating portion. Is possible.

That is, the saturation drain current value at the time of forming the recess can be made uniform by providing the dummy recess pattern in which the dummy gate electrodes 4a and 4b are formed on both sides of the FET operating region (active layer region). In particular, the density of the recess pattern in which the gate fingers are arranged at the end of the FET operating region becomes the same as that of the central part, and the etching rate for the gate fingers in the FET operating region becomes uniform at least, and the depth of the formed recess 7A is increased. This is because the thickness becomes uniform, the thickness of the n-GaAs layer 6 as the active layer becomes uniform, and the saturated drain current value becomes uniform for each gate finger in the FET operating region.

Thus, in this embodiment, the FET is
Recessed Al-based metal gate in which the saturated drain current value of each gate finger in the FET is uniform by providing dummy recess patterns on both sides of the operating region (active layer region)
FET can be obtained.

Embodiment 2 FIG. In the present embodiment, a case will be described where the present invention is applied to a recess type WSi / Au T type gate FET as a semiconductor device having a plurality of gate fingers. FIG. 4 is a plan view showing a recess type WSi / Au T type gate FET having a plurality of gate fingers according to the present embodiment. 4, parts corresponding to those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted. In the figure, 10 is a T-shaped gate electrode as a control electrode having a predetermined shape.

FIG. 5 shows the recess type WSi / Au T type gate of FIG.
It is sectional drawing which shows the manufacturing process of FET. The manufacturing method will be described below with reference to FIG. First, as shown in FIG. 5A, an n-GaAs layer 6 is formed on a semi-insulating GaAs substrate 5 by an ion implantation method or an epitaxial crystal growth method, and then an SiO film 11 is deposited on the entire surface of the wafer. Then, FIG.
As shown in (b), patterning is performed with a photoresist 12, and a SiO 2 film 11 as a first insulating film is opened by reactive ion etching using this as a mask. Layer 6 is etched to form recess 7A and dummy recess patterns 8a and 8b.

Next, as shown in FIG. 5C, a SiO film 13 as a second insulating film is further deposited on the entire surface of the wafer, and the SiO film 13 is anisotropically etched by reactive ion etching. As shown in FIG. 5 (d), n-GaA in the recess 7A
The SiO sidewall 14 is formed on the s layer 6. afterwards,
As shown in FIG. 5E, a WSi film 15 and an Au film 16 as metal films are deposited on the entire surface of the wafer by a sputtering method, and then patterned with a photoresist 17 so that only the gate electrode 10 in FIG. 4 is left. Then, after ion-milling and dry etching to form a T-shape as shown in FIG. 5F, the SiO film 11 and the SiO sidewall 14 are removed with a hydrofluoric acid-based solution.

The WSi film 15 and the Au film 16 are used as metal films.
Both of these are used in order to improve the current flow of the gate electrode formed of these metals by coating the lower WSi film 15 with the Au film 16 having a lower resistance value than the upper one. If the resistance value is sufficiently low, it is not always necessary to use a plurality of resistance values. Finally, as shown in FIG. 5G, the drain electrode 2 and the source electrode 3 made of AuGe system are formed by the vapor deposition / lift-off method. As a result, FIG.
It is possible to obtain a recess type WSi / Au T type gate FET as shown in FIG.

Thus, in this embodiment, the FET is
By providing dummy recess patterns on both sides of the operating area (active layer area), variations in the current value at the time of recess formation near both ends of the gate pattern are substantially absorbed by the dummy recess pattern, and areas with uniform current values are obtained. Recessed WSi / Au that can be used as the FET operating region only and the saturation drain current value of each gate finger in the FET is uniform.
A T-type gate FET can be obtained. Further, in the present embodiment, the dummy recess pattern portion can be removed by etching the insulating film and the sidewalls, but only the recess step remains, but other unnecessary gate patterns can be removed.

Embodiment 3 In this embodiment, a case where the present invention is applied to a recess type Al-based metal gate FET having a plurality of gate fingers will be described. FIG.
FIG. 3 is a plan view showing a recess type Al-based metal gate FET having a plurality of gate fingers according to the present embodiment. FIG.
In FIG. 3, the same reference numerals are given to the portions corresponding to those in FIG. In the figure, 18a and 18b are compound semiconductor regions having a flat surface formed by etching a dummy recess pattern portion as described later.

FIG. 7 shows the recess type Al-based metal gate FE of FIG.
FIG. 6 is a cross-sectional view showing the manufacturing process of T. Hereinafter, the manufacturing method will be described with reference to FIG. First, as shown in FIG. 7A, the recess 7A in the FET operating region, the gate electrode 1, the drain electrode 2, the source electrode 3, and the outside of the FET operating region are manufactured by the same manufacturing method as in the first embodiment. The formation of the dummy recess patterns 8a and 8b and the dummy gate electrodes 4a and 4b is performed.

After that, as shown in FIG. 7B, the FET operation region is masked with a photoresist 19, and as shown in FIG. 7C, the dummy gate electrodes 4a and 4b are dry-etched or wet-etched. , And then FIG.
As shown in (d), the compound semiconductor substrate in the regions of the dummy recess patterns 8a, 8b is dry-etched or wet-etched from the surface to form compound semiconductor regions 18a, 18b having flat surfaces, By stopping the etching by an etching stopper layer or a buffer layer (not shown) provided under the active layer region, that is, under the n-GaAs layer 6, as shown in FIG.
It is possible to obtain a recess type Al-based metal gate FET equivalent to the above FET.

Thus, in this embodiment, the FET is
By providing dummy recess patterns on both sides of the operating region (active layer region), the dummy recess pattern substantially absorbs variations in the current value during recess formation near both ends of the gate electrode recess pattern, and Only a uniform region can be used as the FET operating region, and a recess type Al-based metal gate FET in which the saturated drain current value of each gate finger in the FET is uniform can be obtained as in the first embodiment. Also, by removing unnecessary dummy gate electrodes and dummy recess patterns outside the FET operating area, the substrate surface has a flat surface with no steps, and wiring, MI
It is possible to obtain a recess type Al-based metal gate FET having a structure advantageous for forming a circuit portion such as an M capacitor and a resistor.

Embodiment 4 FIG. In this embodiment, the present invention is applied to a recess type WSi / Au T having a plurality of gate fingers.
The case of application to a mold gate FET will be described. FIG.
FIG. 6 is a plan view showing a recess type WSi / Au T type gate FET having a plurality of gate fingers in the present embodiment. 8, parts corresponding to those in FIGS. 4 and 6 are designated by the same reference numerals, and detailed description thereof will be omitted. Also in this embodiment, the compound semiconductor regions 18a and 18b having flat surfaces are formed by etching the dummy recess pattern portion.

FIG. 9 shows the recess type WSi / Au T type gate of FIG.
It is sectional drawing which shows the manufacturing process of FET. The manufacturing method will be described below with reference to FIG. First, as shown in FIG. 9A, the recess 7A, the T-type gate electrode 10, the drain electrode 2, the source electrode 3, and the FET operating region in the FET operating region are manufactured by the same manufacturing method as that of the second embodiment. The formation of the outer dummy recess patterns 8a and 8b is performed. After that, Fig. 9 (b)
As shown in FIG. 9, the FET operating region is masked with a photoresist 19, and as shown in FIG. 9C, the compound semiconductor substrate in the region of the dummy recess patterns 8a and 8b is dry-etched or wet from its surface. Compound semiconductor regions 18a, 18 having a flat surface by etching
Etching stopper layer or buffer layer (not shown) formed under the active layer region, that is, under the n-GaAs layer 6 by forming b
As shown in FIG. 9D, the recess type WSi / Au T type gate F corresponding to the FET of FIG.
You can get ET.

Thus, in this embodiment, the FET is
By providing dummy recess patterns on both sides of the operating region (active layer region), the dummy recess pattern substantially absorbs variations in the current value during recess formation near both ends of the gate electrode recess pattern, and It is possible to obtain a recess type WSi / Au T type gate FET in which only a uniform region can be used as the FET operation region and the saturated drain current value of each gate finger in the FET is uniform, as in the second embodiment. it can. In addition, by removing unnecessary dummy recess patterns during FET operation, there is a flat surface without steps on the substrate surface, and a recess type WSi / with a structure advantageous for forming circuit parts such as wiring, MIM capacitors, and resistors. Au T-type gate FET can be obtained.

Embodiment 5 FIG. 10 is a recessed gate having a plurality of gate fingers according to the present embodiment.
It is a top view which shows the semiconductor substrate in which FET was formed. FIG.
0, parts corresponding to those in FIG.
The detailed description is omitted. FIG. 11 is a plan view showing a manufacturing process of the recess type gate FET of FIG. Hereinafter, FIG.
The manufacturing method will be described with reference to FIG. As shown in FIG. 11A, a gate finger pattern is continuously arranged on the entire surface of the wafer in a direction perpendicular to the gate finger direction in the drawing to form a gate electrode 1 and a dummy gate electrode 4. Next, as shown in FIG. 11B, unnecessary gate electrodes 4 other than the FET portion are removed by using the manufacturing method described in the third or fourth embodiment to form a necessary FET, A recess type gate FET as shown in FIG. 10 can be obtained. In this case, the type of the FET gate may be an Al-based metal gate or a WSi / Au T type gate.

In this way, in this embodiment, it is possible to obtain the recess type gate FET in which the saturated drain current value of each gate finger is uniform. Further, by using the method as described above, when various FETs having different total gate widths are formed on the same substrate, various FETs having a uniform saturated drain current value per the same gate width can be obtained.

Sixth Embodiment FIG. 12 is a recessed gate having a plurality of gate fingers according to the present embodiment.
It is a top view which shows the semiconductor substrate in which FET was formed. FIG.
2, parts corresponding to those in FIG.
The detailed description is omitted. In the present embodiment, in the recess type gate FET of the fifth embodiment, an arbitrary part of the gate fingers arranged on the entire surface of the wafer is used as the current value monitoring TEG 20 for adjusting the recess current.

In this way, in this embodiment, in addition to the effects of the above-mentioned fifth embodiment, the adjustment current can be monitored during recess formation, so that a recess pattern with a more uniform depth can be formed and the saturated drain can be formed. The uniformity of current value can be improved.

Embodiment 7 FIG. 13 is a recessed gate having a plurality of gate fingers according to the present embodiment.
It is a top view which shows FET. In FIG. 13, parts corresponding to those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted. In the figure, 21 is a region where the unit FET is arranged, and 22 is a region where the spare unit FET is arranged. In this embodiment, a FET having spare unit gate cells of a required number or more is formed, and when some unit gate cells in the FET are defective or destroyed, the spare unit gate cells are By reconnecting to, the desired performance is obtained. Incidentally, FIG. 13 shows a case where the region 21 has three unit gate cells and the region 22 has one spare unit gate cell. In this case,
The gate type of the FET may be either an Al-based metal gate or a WSi / Au T type gate.

In this way, also in the present embodiment, the saturation drain current value can be made uniform as in the above-mentioned embodiment, and further, in the present embodiment, the recess type as described above is used. By using the gate FET in the module, it is possible to improve the chip yield and the assembly yield.

Embodiment 8 FIG. In the present embodiment, the same FETs as in the above-described seventh embodiment, that is, a unit FET (area 21) necessary for output and a spare unit FET (area 2) are used.
It constitutes a high output semiconductor device having 2). In such a semiconductor device, the unit FE of the region 21
If the output does not meet the design value when a module etc. is formed using T, a spare unit FET (region 22)
And add the wires.

In this way, also in this embodiment, the saturation drain current value can be made uniform as in the case of the above-mentioned embodiment, and further, in this embodiment, a spare drain current value can be obtained according to the output. Unit FET of the original unit FET
In addition to wiring, the yield of chips is improved,
And the yield at the time of assembly can be improved,
The required high-power semiconductor device can be easily configured, and the demand can be immediately met.

[Brief description of the drawings]

FIG. 1 is a plan view showing a first embodiment of the present invention.

FIG. 2 is a sectional view showing a manufacturing process for the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a saturated drain current value for each gate finger of the semiconductor device according to the first embodiment of the present invention in correspondence with the array thereof.

FIG. 4 is a plan view showing a second embodiment of the present invention.

FIG. 5 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 6 is a plan view showing a third embodiment of the present invention.

FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the third embodiment of the present invention.

FIG. 8 is a plan view showing a fourth embodiment of the present invention.

FIG. 9 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the fourth embodiment of the present invention.

FIG. 10 is a plan view showing a fifth embodiment of the present invention.

FIG. 11 is a plan view showing a manufacturing process of a semiconductor device according to a fifth embodiment of the present invention.

FIG. 12 is a plan view showing a sixth embodiment of the present invention.

FIG. 13 is a plan view showing a semiconductor device according to seventh and eighth embodiments of the present invention.

FIG. 14 is a plan view showing a conventional semiconductor device.

FIG. 15 is a cross-sectional view showing the manufacturing process of the conventional semiconductor device.

FIG. 16 is a diagram showing a saturated drain current value for each gate finger of a conventional semiconductor device, corresponding to the array.

FIG. 17 is a diagram showing the saturated drain current value for each gate finger of a conventional semiconductor device having a different total gate width, corresponding to the array.

[Explanation of symbols]

1 gate electrode, 2 drain electrode, 3 source electrode,
4a, 4b dummy gate electrodes, 5 semi-insulating GaAs substrate, 6 n-GaAs layer (active layer), 7A recess, 8a, 8
b dummy recess pattern, 10 T-type gate electrode, 1
1,13 SiO film, 14 SiO sidewall, 15 WS
i film, 16 Au film, 18a, 18b compound semiconductor region, 20 current value monitoring TEG, 21 unit FET
Area, 22 spare unit FET area.

Claims (11)

[Claims] 1. An active layer provided on a semiconductor substrate, first and second main electrodes formed on the active layer, and a recess pattern formed on the active layer with a uniform depth. A semiconductor device, characterized in that the control electrode is provided inside the first and second main electrodes so as to face each other in an interdigitated manner. 2. A plurality of semiconductor elements including the first electrode, the second main electrode and the control electrode are provided, and the widths of the control electrodes of the plurality of semiconductor elements are different from each other. The semiconductor device according to claim 1. 3. The semiconductor device according to claim 2, wherein one of the plurality of semiconductor elements is used for an original operation and the other is used as a spare. 4. The semiconductor device according to claim 3, wherein the semiconductor element for operation and the semiconductor element for backup are connected to each other for high output. 5. A step of forming an active layer on a semiconductor substrate, a step of forming first and second main electrodes on the active layer, and a step of forming a first and second main layer on the active layer via a mask. A method of manufacturing a semiconductor device, comprising: a step of forming a recess pattern; and a step of forming a control electrode in at least the first recess pattern. 6. At least the second electrode by masking portions of the first electrode, the second main electrode and the control electrode.
6. The method for manufacturing a semiconductor device according to claim 5, further comprising the step of removing a portion of the active layer in which the recess pattern of FIG. 7. A step of forming an active layer on a semiconductor substrate, providing a first insulating film on the active layer, and using the first insulating film as a mask, first and second recesses in the active layer. A step of forming a pattern, and a step of forming a second insulating film over the entire surface of the wafer including the first insulating film, etching the second insulating film, and forming a sidewall in the first recess pattern. And providing a metal film on the entire surface of the wafer including the sidewall,
A step of processing the metal film to form a control electrode having a predetermined shape, removing the first insulating film and the sidewall,
And a step of forming first and second electrodes on the active layer. 8. A step of masking the portions of the first electrode, the second main electrode and the control electrode to remove the portion of the active layer in which the second recess pattern is formed. The method of manufacturing a semiconductor device according to claim 7, wherein 9. A first electrode and a second main electrode on the active layer, a control electrode in the first recess pattern and at least the second recess pattern are continuously formed on the entire surface of the wafer, 6. The method for manufacturing a semiconductor device according to claim 5, wherein a portion of the active layer in which the second recess pattern is formed is removed to form a plurality of semiconductor elements. 10. A control electrode having a predetermined shape in the first recess pattern and a first electrode and a second electrode on the active layer are continuously formed on the entire surface of the wafer, and the second recess pattern is formed. 8. The method for manufacturing a semiconductor device according to claim 7, wherein a plurality of semiconductor elements are formed by removing a portion of the active layer in which is formed. 11. A TEG for monitoring a current value when adjusting a recess current in a part of a control electrode constituting the plurality of semiconductor elements.
11. The method for manufacturing a semiconductor device according to claim 9, wherein the method is used as a semiconductor device.