JPS62217671A - Manufacture of field-effect transistor - Google Patents

Abstract

PURPOSE:To reduce the gate parasitic capacity while shortening the gate length by a method wherein a sidewall pattern comprising an insulating layer is formed on the sidewalls of a recession formed in a base and then a gate electrode is formed in the recession. CONSTITUTION:A source electrode 3, a drain electrode 4 and the first insulating layer 5 are formed on a base comprising a substrate 1 with a cap layer 2 deposited thereon. First, an opening 7 is made in the insulating layer 5 using a resist film 6 with an opening pattern made therein further to etch the cap layer 2 using the insulating layer 5 as a mask. Second, after forming the second this insulating layer 8, the base 1 is exposed by directional etching process simultaneously to form sidewall pattern on sidewalls of recession. Successively after coating overall surface with an Al layer to form a gate electrode pattern on the recession, the resist film 6 and the Al layer 9 coated thereon are removed to manufacture a FET. Through these procedures, the gate parasitic capacity can be reduced while shortening the gate length.

Description

[Detailed Description of the Invention] [Summary] The present invention involves forming a recess (recess) in a semiconductor substrate using a first insulating layer as a mask, and forming a sidewall pattern made of a second insulating layer on the side wall of the recess. After that, by forming a gate electrode in the recessed part, the gate parasitic capacitance and the gate length are reduced.
Especially in a transistor having a recess l in the gate part,
Reduces gate parasitic violet, and.

The present invention relates to a manufacturing method for obtaining a transistor with good characteristics by shortening the gate length.

[Problems to be solved by the prior art and the invention] Conventionally, in a beta-junction field effect transistor using a compound semiconductor such as GaAs/AtGaAs, a recess is formed in the n-GaAs cap layer. However, since the gate electrode is in contact with the cap layer, parasitic capacitance is added to the gate, which hinders high-speed operation.

Furthermore, in the past, attempts have been made to shorten the gate length in order to achieve high-speed operation, but this has been limited due to the finely processed silk.

The present invention provides a method for manufacturing a field effect transistor that reduces gate parasitic capacitance and shortens gate length, thereby achieving higher speed operation.

[Means for solving problems]

According to the present invention, the above-mentioned problem can be solved by forming a resist film on the semiconductor substrate provided with the first insulating layer, partially removing the gate electrode formation region t& of the resist film, and further removing the gate electrode formation region t& of the resist film. removing up to the first insulating layer to form an opening that partially exposes the surface of the base, etching the exposed portion of the base using the first insulating IvI as a mask to form a recess in the base; A second insulating layer is formed on the substrate in which the recess is formed, and the second insulating layer is button-etched perpendicularly to the substrate using a directional etching means to partially expose the surface of the substrate and to remove the sidewalls of the recess. This problem can be solved by forming a sidewall pattern, depositing a conductive layer on the substrate using the resist film as a mask, and removing the resist film and the conductive layer thereon to form a goo+vt electrode.

[Effect]

In the present invention, the gate 'll is formed by the first and second insulating layers.
The gate parasitic capacitance is reduced by preventing the l-pole from contacting the surface of the semiconductor substrate, and the gate length is shortened by narrowing the opening of the recess by forming the sidewall pattern made of the second insulating layer.

〔Example〕

No. 11N is a process sectional view for explaining a method for manufacturing a field effect transistor according to an embodiment of the present invention.

The present embodiment will be described below with reference to this drawing.

First, semi-insulating GaAs K GaAs layers and AtGaA
As shown in FIG. 1(a), a cap layer 2Y made of n-type GaAg or the like is deposited on a substrate 1 on which layers related to transistor operation, such as an s-layer, are formed.

A source electrode 3 and a drain electrode 4 are formed on the substrate. These electrodes can be formed by patterning using etching means, lift-off method using resist, or the like. In addition, a first insulating layer 5 made of silicon dioxide, for example, is formed between the source electrode 3 and the drain electrode 4. This insulating layer 5 is formed using a spacer when the source electrode 3 and drain electrode 4t are formed by the lift-off method. It can be formed as

Next, a resist IgY is applied to the entire surface of the substrate 1, exposed and developed to form an opening pattern in the gate electrode formation gAM, and using this as a mask, the resist IgY is partially etched. Opening holes 7 shown in (b) are formed.

In this etching of the insulating layer, the etching means is selected so that the surface of the cap layer 2 is exposed to have approximately the same width as the opening pattern of the mask of the resist film, and the resist film has an eaves shape. A plurality of etching means may be combined.

Next, as shown in FIG. 1(C), the cap layer 2t is etched using the first insulating layer 5 as a mask to form a recess.
As shown in Figure (d), a second insulating layer N8 having a ridge of silicon dioxide, for example, is formed thinly so as not to completely fill the recessed portion.

Next, the second insulating layer 8ya-etching is performed on the substrate 1 by directional dry etching means. At the same time, a sidewall pattern is formed on the sidewall of the recess.

Thereafter, the exposed portions of the recesses are etched if necessary. Next, for example, an aluminum layer 9 is deposited on the entire surface of the substrate 1, and a gate electrode pattern is formed in the recessed portion using the resist film 6 as a mask, as shown in FIG. 1(e).

Next, when the resist film 6 and the aluminum layer 9 thereon are removed, a field effect transistor with a shortened gate length is formed by the sidewall pattern 8 shown in FIG. 1(f)K.

〔Effect of the invention〕

According to the present invention, the first and second insulating layers prevent the gate electrode from coming into contact with the semiconductor surface, thereby reducing gate parasitic capacitance.

Further, since the sidewall pattern made of the insulating layer @2 is formed with a recess K, the gate length can be further shortened.

[Brief explanation of drawings]

FIG. 1 is a process sectional view for explaining an embodiment of the present invention. In the figure, l is the substrate, 2 is the cap layer, 3 is the source electrode, 4
is a drain electrode, 5 is a first insulating layer, 6 is a resist film,
7 is an opening, 8 is a second insulating film, 9 is a conductive layer, and 10 is a gate electrode. Book V Mei-Tk Example P Mae Mei 7 Filter Work J7 Menguchi ¥1 [2
1

Claims (1)

[Claims] A resist film is formed on a semiconductor substrate provided with a first insulating layer, and a gate electrode formation region of the resist film is partially removed;
Further, the first insulating layer underneath is removed to form an opening that partially exposes the surface of the substrate, and the exposed portion of the substrate is etched using the first insulating layer as a mask to form a recess in the substrate. forming a second insulating layer on the substrate in which the recess is formed, and etching the second insulating layer perpendicularly to the substrate using a directional etching means to partially expose the surface of the substrate. At the same time, a sidewall pattern is formed on the sidewall of the recess, a conductive layer is deposited on the substrate using the resist film as a mask, and the resist film and the conductive layer thereon are removed to form a gate electrode. A method for manufacturing a field effect transistor.