KR950013900B1 - Dram cell manufacturing process - Google Patents

Dram cell manufacturing process Download PDF

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Publication number
KR950013900B1
KR950013900B1 KR1019920002285A KR920002285A KR950013900B1 KR 950013900 B1 KR950013900 B1 KR 950013900B1 KR 1019920002285 A KR1019920002285 A KR 1019920002285A KR 920002285 A KR920002285 A KR 920002285A KR 950013900 B1 KR950013900 B1 KR 950013900B1
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KR
South Korea
Prior art keywords
polysilicon
depositing
etching
contact hole
mask
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KR1019920002285A
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Korean (ko)
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KR930018721A (en
Inventor
정제승
Original Assignee
금성일렉트론주식회사
문정환
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Priority to KR1019920002285A priority Critical patent/KR950013900B1/en
Publication of KR930018721A publication Critical patent/KR930018721A/en
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Publication of KR950013900B1 publication Critical patent/KR950013900B1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/318—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor the storage electrode having multiple segments

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

The method for manufacturing a capacitor storage electrode for a DRAM cell comprises the steps of: forming transistors over a semiconductor substrate, depositing an oxide layer over the substrate and sequentially depositing a nitride layer and a polysilicon; performing a storage node contact mask process and etching the polysilicon of the portion where a contact hole is to be formed; depositing the polysilicon again and forming a side wall of the polysilicon by etching back; etching the nitride layer and oxide layer by using the polysilicon as a mask and forming a contact hole; depositing the polysilicon to completely fill the contact hole with the polysilicon and depositing thick oxide layer thereover; forming a contact hole at the oxide layer over the polysilicon by using a storage node contact mask and depositing the polysilicon; etching back the polysilicon to form a small cylinder, patterning a photo resist by using a storage node mask, etching the oxide layer and removing the photo resist; and depositing and etching back the polysilicon to form a large cylinder outside of the small cylinder, removing the oxide layer between the small and large cylinders by a wet-etching process.

Description

디램셀의 캐패시터 저장전극 제조방법Method for manufacturing capacitor storage electrode of DRAM cell

제 1 도는 : 본 발명의 공정도.1 is a process diagram of the present invention.

본 발명은 디램셀의 캐패시터 저장전극 제조방법에 관한 것이며, 특히 캐패시터의 저장전극과 소오스/드레인을 접속하는 콘택형성 기술을 개량한 캐패시터의 저장전극 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a capacitor storage electrode of a DRAM cell, and more particularly, to a method of manufacturing a storage electrode of a capacitor having an improved contact forming technology for connecting a storage electrode of a capacitor and a source / drain.

반도체 디램의 집적도가 증가됨에 따라 셀의 캐패시터 저장전극과 소오스/드레인을 연결시키는 스토리지 노드 콘택 형성이 어려운 문제로 되어왔다.As the degree of integration of semiconductor DRAMs has increased, it has become a difficult problem to form storage node contacts connecting the capacitor storage electrodes of the cells and the source / drain.

즉, 이 콘택이 차지하는 면적이 집적도 증가의 장애요인 중 하나가 되었다.In other words, the area occupied by this contact became one of the obstacles to the increase in density.

본 발명에서는 종래의 이 콘택문제를 해결하여 높은 집적도를 달성시키는 기술을 제공하려는 것으로, 제 1 도를 참조하면서 자세히 설명한다.The present invention seeks to provide a technique for achieving a high degree of integration by solving this conventional contact problem, which will be described in detail with reference to FIG.

먼저, 제 1 도의 a에서 보인 바와 같이, 디램용 트랜지스터들을 반도체 기판상에 종래의 방법으로 형성한다.First, as shown in a of FIG. 1, DRAM transistors are formed on a semiconductor substrate by a conventional method.

도면부호 제10번은 소오스/드레인을, 제11번은 게이트를, 그리고 제12번은 게이트상부절연막을 가르킨다.Reference numeral 10 denotes a source / drain, 11th a gate, and 12th a gate upper insulating film.

다음에 제 1 도의 b와 같이, 기판전체에 산화막(20)을 데포지션하여 평탄화시키고, 그 위에 질화막(21)과 폴리실리콘(22)을 차례로 데포지션한다. 그후 캐패시터의 스토리지 노드 콘택마스크 작업을 하여 콘택홀이 형성될 부분의 폴리실리콘(22)를 식각하여 제거한다(제 1 도의 c).Next, as shown in FIG. 1B, the oxide film 20 is deposited and planarized over the entire substrate, and the nitride film 21 and the polysilicon 22 are sequentially deposited thereon. After that, the storage node contact mask operation of the capacitor is performed to etch and remove the polysilicon 22 in the portion where the contact hole is to be formed (c in FIG. 1).

이렇게 한 후, 다시 폴리실리콘을 데포지션하고 에치백하여 폴리실리콘의 사이드월(23)을 형성한다. 이때 콘택홀의 크기가 결정된다(제 2 도의 d).After this, polysilicon is again deposited and etched back to form sidewalls 23 of polysilicon. At this time, the size of the contact hole is determined (d in FIG. 2).

다음에, 이 폴리실리콘(22,23)을 마스크로 이용하여 질화막(21)과 산화막(20)을 에치하여 콘택홀을 형성한다(제 1 도의 e).Next, using the polysilicon 22, 23 as a mask, the nitride film 21 and the oxide film 20 are etched to form a contact hole (e in FIG. 1).

그후 폴리실리콘(23)을 데포지션하여 콘택홀을 폴리실리콘으로 완전히 채우고, 그 위에 산화막(24)를 두껍게 데포지션 한 후( 제 1 도의 f), 다시 스토리지노드 콘택마스크를 이용하여 폴리실리콘(23)위의 산화막(24)에 콘택홀을 형성하고 폴리실리콘(25)를 데포지션한다(제 1 도의 g). 그리고, 폴리실리콘(25)를 에치백 하여 작은 실린더(26)을 형성한 후, 스토리지 노드 마스크를 이용하여 포토레지스트를 패턴닝하고 산화막(24)을 식각한 후 포토레지스트를 제거한다(제 1 도의 b).Thereafter, the polysilicon 23 is deposited to completely fill the contact hole with polysilicon, and the oxide layer 24 is thickly deposited thereon (f in FIG. 1), and then the polysilicon 23 is formed using the storage node contact mask. A contact hole is formed in the oxide film 24 on the top layer, and the polysilicon 25 is deposited (g in FIG. 1). After etching the polysilicon 25 to form a small cylinder 26, the photoresist is patterned using a storage node mask, the oxide film 24 is etched and the photoresist is removed (Fig. 1). b).

이렇게 한 후 폴리실리콘을 데포지션하고 에치백하여 작은 실린더(26)바깥쪽으로 큰 실린더(27)를 형성하고, 작은실린더(26)와 큰 실린더(27) 사이의 산화막(24)을 습식식각 공정으로 제거하며 캐패시터의 저장전극을 형성을 완료한다.After this, polysilicon is deposited and etched back to form a large cylinder 27 out of the small cylinder 26, and the oxide film 24 between the small cylinder 26 and the large cylinder 27 is wet-etched. Removal is completed to form the storage electrode of the capacitor.

본 발명의 공정을 이용하므로써 0.5마이크로미터 이상의 콘택패턴을 이용하여 약 0.1마이크로미터의 극히 미세한 콘택홀도 실현할 수 있게 된다.By using the process of the present invention, an extremely fine contact hole of about 0.1 micrometer can be realized by using a contact pattern of 0.5 micrometer or more.

Claims (1)

디램셀의 캐패시터 저장전극 제조방법에 있어서, 디램용 트랜지스터들을 반도체 기판상에 종래의 방법으로 형성한 다음에, 기판전체에 산화막(20)을 데포지션하여 평탄화시키고, 그 위에 질화막(21)과 폴리실리콘(22)을 차례로 데포지션하는 단계, 캐패시터의 스토리지 노드 콘택마스크 작업을 하여 콘택홀이 형성될 부분의 폴리실리콘(22)를 식각하여 제거하는 단계, 다시 폴리실리콘을 데포지션하고 에치백하여 폴리실리콘의 사이드월(23)을 형성하는 단계, 이 폴리실리콘(22,23)을 마스크로 이용하여 질화막(21)과 산화막(20)을 에치하여 콘택홀을 형성하는 단계, 그후 폴리실리콘(23)을 데포지션하여 콘택홀을 폴리실리콘으로 완전히 채우고, 그 위에 산화막(24)를 두껍게 데포지션하는 단계, 다시 스토리지노드 콘택마스크를 이용하여 폴리실리콘(23)위의 산화막(24)에 콘택홀을 형성하고 폴리실리콘(25)를 데포지션하는 단계, 폴리실리콘(25)를 에치백하여 작은 실린더(26)을 형성한 후, 스토리지 노드 마스크를 이용하여 포토레지스트르 패터닝하고 산화막(24)을 식각한 후 포토레지스트를 제거하는 단계, 폴리실리콘을 데포지션하고 에치백하여 작은 실린더(26) 바깥쪽으로 큰 실린더(27)를 형성하고, 작은실린더(26)와 큰 실린더(27) 사이의 산화막(24)을 습식식각 공정으로 제거하는 단계로 이루어지는 디램셀의 캐패시터 저장전극 제조방법.In the method of manufacturing a capacitor storage electrode of a DRAM cell, DRAM transistors are formed on a semiconductor substrate in a conventional manner, and then the oxide film 20 is deposited and planarized over the entire substrate, and the nitride film 21 and the polyimide film are formed thereon. Depositing the silicon 22 in sequence, etching the polysilicon 22 in the portion where the contact hole is to be formed by performing a storage node contact mask operation of the capacitor, and depositing and etching back the polysilicon. Forming sidewalls 23 of silicon, etching the nitride film 21 and the oxide film 20 using the polysilicon 22, 23 as a mask to form a contact hole, and then the polysilicon 23 And depositing the contact hole completely with polysilicon, and thickly depositing the oxide film 24 thereon, and again using the storage node contact mask, the acid on the polysilicon 23. Forming a contact hole in the film 24 and depositing the polysilicon 25, etching back the polysilicon 25 to form a small cylinder 26, and then patterning the photoresist using a storage node mask. And etching the oxide film 24 to remove the photoresist, depositing and etching back the polysilicon to form a large cylinder 27 out of the small cylinder 26, and a small cylinder 26 and a large cylinder ( 27) A method for manufacturing a capacitor storage electrode of a DRAM cell comprising the step of removing the oxide film (24) between the wet etching process.
KR1019920002285A 1992-02-15 1992-02-15 Dram cell manufacturing process KR950013900B1 (en)

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KR930018721A KR930018721A (en) 1993-09-22
KR950013900B1 true KR950013900B1 (en) 1995-11-17

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KR100745924B1 (en) * 2005-06-30 2007-08-02 주식회사 하이닉스반도체 Method for manufacturing semiconductor device

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