KR0136777B1 - Dram cell & method of manufacturing therfor - Google Patents

Abstract

none

Description

DRAM cell by self-matching method and manufacturing method thereof

1 is a cross-sectional view of a conventional stacked DRAM cell.

2 is an equivalent circuit diagram of a typical DRAM cell.

3 is a cross-sectional view of the DRAM cell of the present invention.

(A)-(e) of FIG. 4 is a manufacturing process diagram of the multilayer DRAM cell of the present invention.

Explanation of symbols on the main parts of the drawings

11 substrate 12 field oxide film

13: n + buried layer 14: gate

15, 18, 22: isolation oxide layer 19, 21: polysilicon layer

16: nitride oxide layer 17: photosensitive film

20 capacitor dielectric film 23 side wall

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DRAM cell. In particular, a bit line contact is formed by a self-aligning method to extend the area of a storage node, thereby increasing the integration of devices. A self-aligning method relates to a DRAM cell and a method of manufacturing the same.

FIG. 1 is a cross-sectional structure diagram of a conventional DRAM cell. As shown therein, a gate electrode 4 and a contact hole are formed on a substrate 1 having an n + buried layer 3 formed therein and a field oxide film 2 formed on both sides thereof. The first isolation oxide film 5 formed thereon is formed in turn, and the first isolation oxide film 6 is formed, and the capacitor dielectric film 7 and the second polysilicon layer 8 are formed on the first polycrystalline silicon layer 6. ) Is sequentially formed, and a second isolation oxide film 9 having a contact hole formed in an isolation region portion is formed on the second polysilicon layer 8, and a contact hole of the isolation region is formed on the second isolation oxide layer 9. The bit line 10 is formed to be in contact with the substrate 1 through, and the manufacturing process thereof will be described with reference to FIG.

First, the field oxide film 2 is formed on the semiconductor substrate 1, and then an active region and an isolation region are defined, and the gate electrode 4 is formed in the active region defined above.

Subsequently, a high concentration (n +) impurity ion implantation is performed using the gate electrode 4 as a mask to form an n + buried layer 3 as a source / drain region in the substrate 1, and then 1 After the isolation oxide film 5 is applied, the first isolation oxide film 5 on the n + buried layer 3 is removed to form a contact hole.

Next, a first polycrystalline silicon layer 6 is formed on the first isolation oxide film 5 and in contact with the n + buried layer 3 through the contact hole, and then the capacitor dielectric film 7 and the second polycrystal are formed thereon. After the silicon layer 8 is formed in sequence, the second isolation oxide film 9 is coated on the front surface of the device.

Thereafter, a contact hole is formed by removing the second isolation oxide layer 9 of the isolation region portion defined above, and then contacting the substrate 1 through the contact hole of the isolation region on the second isolation oxide layer 9. The bit line 10 was formed to manufacture a DRAM cell.

An equivalent circuit diagram of the DRAM cell manufactured as described above is shown in FIG. 2, which will be described below.

The first polysilicon layer 6 contacts the source region of the cell transistor to form a storage node, and the second polysilicon layer 8 uses one electrode of the cell capacitor as a plate node. Form a cell.

However, in the conventional DRAM cell, since the bit line is formed after all of the storage portions for storing charges are formed, the portion where the bit line contacts are formed becomes wider in consideration of a matching error, and also with the bit line storage portion. In order to ensure isolation, the area of the storage node has been reduced, which makes it difficult for high integration of DRAM cells.

Therefore, in view of the above problems, the contact portion is formed by a self-aligning method, thereby expanding the area of the storage node and easily integrating the same. The present invention will be described in detail with reference to the accompanying drawings.

3 is a cross-sectional structure diagram of a DRAM cell according to the present invention. As shown therein, the gate electrode 14 and the first isolation oxide film are formed on the center of the substrate 11 on which the field oxide film 12 and the n + buried layer 13 are formed. 15, a pattern of a nitride oxide layer 16 is formed in turn, and a second isolation oxide film 18 having contact holes formed on the nitride oxide layer 16 is formed, and the n + is formed on the second isolation oxide film 18. The second polysilicon layer 21 and the second isolation oxide layer 22 which are in contact with the buried layer 13 are sequentially formed, and the gate electrode 14 is formed on the sidewalls 23 and 23 from the second isolation oxide layer 22. The bit line 24 which is separated by ') and is in contact with the engine 11 through the side walls 23 and 23' is formed on the front surface of the device.

When described in detail with reference to Figure 4 attached to the manufacturing method of the present invention configured as described as follows.

4A to 4D are manufacturing process diagrams of the DRAM cell of the present invention. First, as shown in FIG. 4A, first, an active region and an isolation region are defined on the substrate 11, and then the substrate 11 is formed. After forming the field oxide film 12 on both sides, the gate metal layer 14a, the first isolation oxide film 15, and the nitride oxide layer 16 are successively coated on the front surface of the device.

Thereafter, as shown in (b) of FIG. 4, the first photoresist film 17 is applied to the front surface of the device to remove the remaining nitride oxide layer 16 except for the gate portion, and then the second photoresist film is applied again. After patterning the second photoresist layer to be formed only on the remaining nitride oxide layer 16, the first isolation oxide layer 15 and the metal layer 14a other than the gate portion are removed to form the first isolation oxide layer 15 pattern. And a gate electrode 14 pattern are formed.

Next, as shown in FIG. 4C, ion implantation of high concentration (n +) impurities using the gate electrode 14 and the field oxide film 12 as a mask is carried out, and then a second isolation oxide film 18 is deposited on the front surface of the device. After that, the second isolation oxide layer 18 on the n + buried layer 13 is removed to form a contact hole. Then, a first polycrystalline silicon layer 19 is formed on the second isolation oxide film 18 in contact with the n + buried layer 13, and the capacitor dielectric film 20 and the second polycrystalline silicon layer are continuously formed thereon. 21), the third isolation oxide film 22 is deposited.

After defining the bit line forming region as shown in (d) of FIG. 4, the defined portions are etched to form contact holes, and then, as shown in (e) of FIG. 4, sidewalls 23 and 23 on both sides of the contact holes. ') Is formed to separate the gate electrode 14, and a bit line 24 is formed between the sidewalls 23 and 23' to manufacture the DRAM cell of the present invention.

In the DRAM cell manufacturing process, when the second isolation oxide layer 18 is etched at the time of forming a contact hole for forming a bit line, the nitride oxide layer 16 is used as an etch limit layer and when the gate electrode 14 is etched. The first isolation oxide layer 15 is used as an etch limit layer so that the contact portion is formed by a self-aligning method.

As described above, the present invention increases the area of the storage, thereby reducing the size of the cell, thereby facilitating integration.

Claims (2)

Forming a field oxide film on the substrate, defining an active region and an isolation region in the device, and subsequently depositing a metal layer, a first isolation oxide layer, and a nitride oxide layer; and a double oxide layer, Forming a first isolation oxide film and a gate electrode pattern; forming an n + buried layer; depositing a second isolation oxide film in the device; and forming a contact hole; and n + buried through the contact hole. Forming a first polysilicon layer in contact with the layer, depositing a capacitor dielectric film, a second polycrystalline silicon layer, and a third isolation oxide film in sequence, defining a bit line formation region, and the above defined Forming a contact hole in the portion, forming a sidewall in the side of the contact hole, and forming a bit line in contact with the substrate through the contact hole between the sidewalls. The method of de raemsel by self-defined polymerization, characterized in that that. A gate electrode, a first isolation oxide layer, and a nitride oxide layer pattern are sequentially formed on the center of the substrate on which the field oxide layer and the n + buried layer are formed, and on the second isolation oxide layer on the second isolation oxide layer having contact holes formed on the nitride oxide layer. A first polysilicon layer in contact with the n + buried layer is formed, and a capacitor dielectric film, a second polysilicon layer, and a third isolation oxide film are sequentially formed on the first polycrystalline silicon layer, and the gate electrode is formed from the third isolation oxide film. A DRAM cell according to the self-aligning method, characterized in that a bit line is separated by the side walls and is in contact with the substrate through the side walls of the device.

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