KR0135174B1 - Manufacture of dram cell - Google Patents

Manufacture of dram cell

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Publication number
KR0135174B1
KR0135174B1 KR1019890012084A KR890012084A KR0135174B1 KR 0135174 B1 KR0135174 B1 KR 0135174B1 KR 1019890012084 A KR1019890012084 A KR 1019890012084A KR 890012084 A KR890012084 A KR 890012084A KR 0135174 B1 KR0135174 B1 KR 0135174B1
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South Korea
Prior art keywords
forming
film
storage node
oxide film
polysilicon
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KR1019890012084A
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Korean (ko)
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KR910005298A (en
Inventor
금은섭
강찬호
김준기
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문정환
엘지반도체주식회사
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Priority to KR1019890012084A priority Critical patent/KR0135174B1/en
Publication of KR910005298A publication Critical patent/KR910005298A/en
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Publication of KR0135174B1 publication Critical patent/KR0135174B1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)

Abstract

A fabrication method of capacitance-increased DRAM is disclosed. The method comprises the steps of: sequentially depositing a gate(12), a side wall(13a), a source/drain(15) and an LTO(low temperature oxide)(16a) on a silicon substance(11); depositing a polysilicon for storage node and forming a buried contact(17) using a photoresist(21); depositing an LTO(16b) on the photoresist(21); stripping the photoresist(21) and depositing a thin polysilicon(18b) for storage node; forming a dielectric layer(19) on the resultant structure; and forming a polysilicon plate(20).

Description

디램(DRAM)셀의 제조방법Manufacturing method of DRAM cell

제 1도는 (가)-(바)는 종래의 DRAM셀의 제조공정단면도1 is a cross-sectional view of a conventional DRAM cell manufacturing process.

제 2도는 (가)-(자)는 본 발명의 실시예에 따른 DRAM셀의 제조공정단면도2 is a cross-sectional view of a manufacturing process of a DRAM cell according to an embodiment of the present invention.

*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

31 : 기판32 : 필드산화막31 substrate 32 field oxide film

33 : 게이트 산화막34 : 게이트33 gate oxide film 34 gate

35 : 사이드월37 : 소오스/드레인,35: sidewall 37: source / drain,

38,42 : 저온산화막40 : 포토레지스트막38, 42 low temperature oxide film 40 photoresist film

41 : 베리드콘택43 : 저온산화막 측벽,41: buried contact 43: low temperature oxide film sidewalls,

39,44 : 스토리지노드용 폴리실리콘막 45 : 캐패시터 유전체막39,44: polysilicon film for storage node 45: capacitor dielectric film

46 : 플레이트전극46: plate electrode

본 발명은 DRAM의 제조방법에 관한 것으로, 특히 메모리 소자의 고집적화에 요구되는 충분한 캐패시턴스를 얻을 수 있는 DRAM셀의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a DRAM, and more particularly, to a method for manufacturing a DRAM cell capable of obtaining sufficient capacitance required for high integration of a memory device.

제1도는 종래의 DRAM의 제조 공정도이다.1 is a manufacturing process diagram of a conventional DRAM.

제1도 (가)를 참조하면, 기판(11)의 필드영역에 필드산화공정을 수행하여 필드 산화막(12)을 형성하고, 게이트 산화막(13)과, 게이트(14)를 형성한다.Referring to FIG. 1A, a field oxide film 12 is formed in a field region of the substrate 11 to form a field oxide film 12, and a gate oxide film 13 and a gate 14 are formed.

이어서, 게이트(14)를 격리시키고 후 속의 폴리식각공정시 리본(Ribborn)이 생기는 것을 방지하기 위한 사이드월(15)을 게이트(14) 양측에 형성한다.Subsequently, sidewalls 15 are formed on both sides of the gate 14 to isolate the gate 14 and prevent a ribbon from being generated during the subsequent poly etching process.

제1동 (나)를 참조하면, 기판과 반대 도전형을 갖는 불순물을 기판으로 이온 주입시켜(16)(Ion Implant) 소오스/드레인영역(17)을 형성한다.Referring to the first cavity (b), a source / drain region 17 is formed by ion implanting an impurity having a conductivity opposite to that of the substrate (16) (Ion Implant).

이로써, 모스트랜지스터가 형성된다.As a result, a morph transistor is formed.

제1도 (다)를 참조하면, 기판 전면에 저온산화막(LTO, Low Temperature Oxide)(28)을 증착하고, 후속공정에서 형성될 스토리지노드(Storage node)와 엑티브(Active)영역인 소오스 또는 드레인영역(17)과의 연결을 위해 베리드 콘택(Buried contact)(19)을 형성한다.Referring to FIG. 1 (C), a low temperature oxide (LTO) 28 is deposited on the entire surface of a substrate, and a storage node and an active region, which is a storage node and an active region, to be formed in a subsequent process. Burried contact 19 is formed for connection with region 17.

제1도 (라)에 도시된 바와같이 스토리지노드용 폴리실리콘막(20)을 기판 전면에 증착하고, 제1도 (마)에 도시한 바와같이 사진 식각공정을 통해 폴리실리콘막(20)을 캐패시터영역에 형성하여 식각함으로써 스토리지노드를 형성하고, 제1도 (바)에 도시한 바와같이 고유전물질을 증착하여 캐패시터 유전체막(21)을 형성하며, 그위에 폴리실리콘막(22)을 증착하여 플레이트전극을 형성하여 캐패시터를 제조한다.As shown in FIG. 1D, a polysilicon film 20 for a storage node is deposited on the entire surface of the substrate, and the polysilicon film 20 is formed through a photolithography process as shown in FIG. A storage node is formed by forming and etching in the capacitor region, and depositing a high dielectric material to form a capacitor dielectric film 21, as shown in FIG. 1 (bar), and depositing a polysilicon film 22 thereon. To form a plate electrode to manufacture a capacitor.

이로써, 종래의 DRAM셀이 얻어진다.As a result, a conventional DRAM cell is obtained.

그러나, 이와 같은 종래의 DRAM셀은 메모리 소자가 고집적화됨에 따라 요구되는 충분한 용량의 캐패시턴스를 얻지못하는 문제점이 있었다.However, such a conventional DRAM cell has a problem in that it is not possible to obtain a capacitance of sufficient capacity as the memory devices are highly integrated.

본 발명은 상기한 문제점을 개선하기 위한 것으로서, 캐패시터의 면적을 증가시켜 캐패시턴스를 증가시킬 수 DRAM셀의 제조방법을 제공하는데 그 목적이 있다.An object of the present invention is to provide a method for manufacturing a DRAM cell that can increase capacitance by increasing the area of a capacitor.

이하, 본 발명의 실시예를 첨부 도면에 의하여 상세히 설명하면 다음과 같다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

제2도 (가)에 도시한 바와같이, 필드영역에 해당하는 기판(31)상에 필드산화공정을 수행하여 필드산화막(32)을 형성하고, 게이트 산화막(33)과 게이트(34)를 형성한다.As shown in FIG. 2A, a field oxidation process is performed on the substrate 31 corresponding to the field region to form the field oxide film 32, and the gate oxide film 33 and the gate 34 are formed. do.

이어서, 게이트(34)를 격리시켜(isolation)주고 후 속의 폴리식각공정시 리본 현상이 발생하는 것을 방지하기 위한 사이드 월(35)을 형성한다.Subsequently, sidewalls 35 are formed to isolate the gate 34 and prevent a ribbon phenomenon from occurring during the subsequent poly etching process.

제2도 (나)에 도시한 바와같이 기판과 반대 도전형을 갖는 불순물을 기판(31)으로 이온 임플란트(36)시켜 소오스/드레인영역(37)을 형성한다.As shown in FIG. 2B, an impurity having a conductivity opposite to that of the substrate is implanted into the substrate 31 to form the source / drain region 37.

제2도 (다) 및 (라)에 도시한 바와같이 저온 산화막(38)과 스토리지노드용 제1폴리실리콘막(39)을 기판 전면에 순차 증착한다.As shown in FIG. 2 (C) and (D), the low-temperature oxide film 38 and the first polysilicon film 39 for the storage node are sequentially deposited on the entire substrate.

이어서, 제2도 (마)에 도시한 바와같이 스토리지노드와 액티브영역 즉 소오스/드레인영역(37)간의 접촉을 위한 콘택(41)을 형성한다.Next, as shown in FIG. 2E, a contact 41 for contact between the storage node and the active area, that is, the source / drain area 37 is formed.

즉, 폴리실리콘막(39)상에 포토레지스트막(40)을 도포하고, 패터닝하여 콘택이 형성될 부분의 포토레지스트막(40)을 제거한다.That is, the photoresist film 40 is coated on the polysilicon film 39 and patterned to remove the photoresist film 40 in the portion where the contact is to be formed.

포토레지스막(40)을 마스크로 노출된 폴리실리콘막(39)과 저온산화막(38)을 식각하여 배리드콘택(41)을 형성한다.The buried contact 41 is formed by etching the polysilicon film 39 and the low temperature oxide film 38 exposing the photoresist film 40 as a mask.

제2도 (바)에 도시한 바와같이 베리드콘택(41)과 포토레지스트막(40)상에 저온산화막(42)을 증착하고 제2도 (사)에 도시한 바와같이 블랭크 에치(Blank etch)를 하여 포토레지스트막(43)을 제거(strip)하면 배리드콘택(41)내의 측벽(43)사이의 엑티브영역인 소오스/드레인영역(37)이 노출한다.A low temperature oxide film 42 is deposited on the buried contact 41 and the photoresist film 40 as shown in FIG. 2 (bar), and blank etch as shown in FIG. When the photoresist film 43 is stripped, the source / drain regions 37 serving as the active regions between the sidewalls 43 of the buried contact 41 are exposed.

제2도 (아)에 도시한 바와같이 스토리지노드용 박막의 제2폴리실리콘막(Thin poly)(44)을 산화막 측벽(43)의 표면 및 베리드 콘택(41)내의 노출된 기판(31)상에 형성하고, 캐패시터 영역을 한정하고 제1폴리실리콘막(39)을 선택 식각하여 스토리지 노드를 형성한다.As shown in FIG. 2A, the second polysilicon film 44 of the storage node thin film is exposed to the surface of the oxide sidewall 43 and the exposed substrate 31 in the buried contact 41. On the substrate, the capacitor region is defined and the first polysilicon layer 39 is selectively etched to form a storage node.

따라서, 스토리지 노드는 제1폴리실리콘막(39) 및 제2폴리실리콘막(44)으로 이루어졌다.Therefore, the storage node is composed of the first polysilicon film 39 and the second polysilicon film 44.

제2도 (자)에 도시한 바와같이 고유전물질을 증착하여 캐패시터 유전체막(45)을 형성한 후 유전체막상에 폴리실리콘막을 증착하여 플레이트전극(46)을 형성한다.As shown in FIG. 2 (i), a high dielectric material is deposited to form the capacitor dielectric film 45, and then a polysilicon film is deposited on the dielectric film to form the plate electrode 46.

상기한 바와같은 본 발명에 따른 DRAM셀은 배리드 콘택을 셀프얼라인(self align)시켜 형성함으로써 마스킹 작업을 줄일 수 있으며, 배리드 콘택의 공정을 안정시킬수 있다.As described above, the DRAM cell according to the present invention can reduce the masking work by forming the buried contacts by self-aligning and can stabilize the buried contact process.

또한, 산화막 측벽을 이용하여 스토리지노드를 측벽 형태로 형성함으로써 스토리지 노드의 접촉면적을 증가시켜 고집적 메모리 소자에 요구되는 대용량의 캐패시턴스를 얻을 수 있는 효과를 갖게된다.In addition, by forming the storage node in the form of a sidewall using the oxide sidewall, the contact area of the storage node is increased to obtain a large capacitance required for a highly integrated memory device.

Claims (1)

반도체 기판(31)의 필드영역상에 필드산화막(32)을 형성하는 공정과, 게이트 산화막(33), 게이트(34) 및 사이드월(35)을 형성하는 공정과, 기판으로 기판과 반대 도전형의 불순물을 이온 주입하여 소오스/드레인영역(37)을 형성하는 공정과, 기판 전면에 제1산화막(38)과 스토리지노드용 제1폴리실리콘막(39)을 형성하는 공정과, 포토레지스트막(40)을 마스크로 하여 스토리지노드용 제1폴리실리콘막(39)과 제1산화막(38)을 식각하여 소오스/드레인영역(37)중 일영역에 베리드콘택(41)을 형성하는 공정과, 베리드콘택(41)의 포토레지스트막(40)의 측면에 제2산화막 측벽(43)을 형성하는 공정과, 제2산화막 측벽의 측면에 스트리지노드용 제2폴리실리콘 측벽(44)을 형성하는 공정과, 캐패시터영역을 한정하고 제1폴리실리콘막(39)을 선택적으로 식각하여 스토리지 노드를 형성하는 공정과, 스토리지노드의 노출된 표면에 유전체막(45)을 형성하는 공정과, 유전체막(45)위에 플레이트전극(46)을 형성하는 공정을 포함하는 것을 특징으로 하는 DRAM셀의 제조방법.Forming a field oxide film 32 on the field region of the semiconductor substrate 31, forming a gate oxide film 33, a gate 34, and a sidewall 35; Forming a source / drain region 37 by ion implantation of impurities, forming a first oxide film 38 and a first polysilicon film 39 for a storage node on the entire surface of the substrate; Etching the first polysilicon film 39 and the first oxide film 38 for the storage node using the mask 40 as a mask to form the buried contact 41 in one of the source / drain regions 37; Forming a second oxide film sidewall 43 on the side of the photoresist film 40 of the buried contact 41, and forming a second polysilicon sidewall 44 for the strip node on the side surface of the second oxide film sidewall. Forming a storage node by defining a capacitor region and selectively etching the first polysilicon film 39. Forming a dielectric film 45 on the exposed surface of the storage node; and forming a plate electrode 46 on the dielectric film 45. .
KR1019890012084A 1989-08-24 1989-08-24 Manufacture of dram cell KR0135174B1 (en)

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KR910005298A KR910005298A (en) 1991-03-30
KR0135174B1 true KR0135174B1 (en) 1998-04-25

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