JP3144089B2 - Method for manufacturing field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor, and more particularly, to a high electron mobility transistor (HEM).
T) such as a field-effect transistor having a so-called T-shaped gate.

[0002]

2. Description of the Related Art Conventionally, as a field-effect transistor of this type, a gate electrode is formed by a lift-off method as shown in FIG. That is, as shown in FIG. 14A, a first resist 2 is applied on the semiconductor layer 1, exposed and developed to form an opening 2a, and then wet-etched with an etching solution through the opening 2a. And a recess 3 is formed. Then, the second resist 4 is patterned on the first resist 2 as shown in FIG.

Next, a gate metal is deposited, and the gate metal on the second resist 4 is lifted off.
A T-shaped gate 5 is formed as shown in FIG. However, in this conventional example, since the upper wide portion 5A of the gate 5 is not held at all, the support portion 5
B was easily damaged and the mechanical strength was weak overall.

[0004] As a countermeasure against such a problem, FIG.
2. Description of the Related Art There is known a field effect transistor manufactured by the following method. In this method, first, as shown in FIG. 15A, an insulating film 6 is formed on the semiconductor layer 1 and the insulating film 6 is formed.
An opening 6a is formed at a predetermined position by using a known technique. The opening width of the opening 6a is set to the width of the column of the gate.

Next, the semiconductor layer 1 is formed through the opening 6a.
Then, the recess 3 is wet-etched. And FIG.
As shown in FIG. 15A, after patterning the resist 7, a gate metal is deposited, and the gate metal on the resist 7 is lifted off to form a gate 8A as shown in FIG. You. FIG. 16 shows a case where an etching method is used instead of the lift-off method. A resist pattern 9 is formed on the gate metal layer 8, and the gate metal layer 8 is dried using the resist pattern 9 as a mask. By etching, FIG.
A gate similar to that shown in FIG.

[0006]

However, the gate 8A of such a field effect transistor is not shown in FIG.
As shown in (B), the space under the wide portion 8a of the upper portion of the gate 8A is filled with the insulating film 6, so that the mechanical strength of the gate is increased, but the parasitic capacitance C is increased and the high frequency characteristics of the field effect transistor are reduced. There is a problem to lower.

In the above-described conventional example, since the width of the recess 3 is uniquely determined by the opening width of the first resist 2 or the insulating film 6, the width of the recess is smaller than the gate length (width of the gate pillar). There was a problem that the degree of freedom could not be obtained.

The present invention has been made in view of such a conventional problem, has the mechanical strength of a T-shaped gate, suppresses an increase in the parasitic capacitance of the gate portion, and An object of the present invention is to provide a method for manufacturing a field effect transistor in which controllability of a gate recess width is improved.

[0009]

[0010]

Accordingly, the present invention provides a semiconductor device comprising:
Sequentially forming a first insulating layer and a second insulating layer on the layer;
After forming a resist layer on the second insulating layer, the resist
A first opening in the layer, and the first opening in the second insulating layer.
Forming a first opening corresponding to
Using the opening as a mask, a second opening is formed in the first insulating layer.
Forming, and using the second opening as a mask
Etching the semiconductor layer to form a recess in the semiconductor layer
And forming the recess after forming the recess,
The width of the upper gate is approximately equal to the width of the upper wide part of the
(1) a step of etching the insulating layer .

[0011]

[0012]

In the present invention , by controlling the width of the opening of the first insulating layer, the width of the corresponding recess can also be controlled.

[0013]

BRIEF DESCRIPTION based on examples showing details of a field effect transistor capacitor method <br/> preparation according to the present invention with reference to the drawings.

FIG. 3 is a plan view of a chip pattern on which a field effect transistor manufactured by the manufacturing method of the present invention is formed, and FIG.
FIG. 2 is a cross-sectional view taken along the line B.

As shown in FIG. 1, the manufacturing method of the present invention
The epitaxial structure on which the fabricated field-effect transistor is formed is sequentially formed on a semi-insulating GaAs substrate 11.
A buffer layer 12 made of high-resistance non-doped GaAs, a channel layer 13 made of non-doped n ⁻ -InGaAs,
Electron supply layer 1 made of Si-doped n ⁺ -AlGaAs
4, cap layer 15 made of Si-doped n ⁺ -GaAs
Are formed.

For such a structure, a recess 16 is formed from the surface. The recess 16 has a structure in which the electron supply layer 14 is cut through the cap layer 15. A T-shaped gate 17 is erected at the bottom of the recess 16, and the lower surface of the upper wide portion 17 a of the T-shaped gate 17 is
The second insulating layer 19 is supported on the second insulating layer 19, and is formed on the first insulating layer 18 formed on the cap layer 15.

Further, the column 1 of the gate of the first insulating layer 18 is formed.
The end face 18a facing 7b is located away from the column 17b, and the vicinity of the column 17b is a hollow portion 20. A source electrode 22 and a drain electrode 23 are provided on both sides of the first and second insulating layers 18 and 19. In the figure, 21 indicates a two-dimensional electron gas, and 17A indicates a pad portion of a gate electrode.

As shown in FIG. 4, the hollow section 20 at the end of the gate is formed with a wide section 17 of the gate.
Since the second insulating layer 19 is sealed by abutting the lower surface of the end portion a, the vacuum is maintained during the later-described gate metal deposition.

FIG. 5 is a sectional view showing a state where the overcoat insulating film 24 is deposited.

In the field effect transistor having such a configuration, the T-shaped gate 17
The parasitic capacitance is reduced due to the difference in the dielectric constant between the vacuum and the insulator, and the mechanical strength of the T-shaped gate 17 is lower than that in the case where the lower portion of the upper wide portion 17a is completely filled with the insulator. It is strengthened because it is supported by the two insulating layers 19. In addition, according to the present embodiment, the vacuum sealing structure of the hollow portion 20 is also used when using a semiconductor material such as an AlInAs / GaInAs HEMT that easily forms a conductive layer at the interface between the recess bottom (AlInAs) and the passivation film. Therefore, the formation of the conductive layer can be prevented.

Next, a method of manufacturing the field-effect transistor of this embodiment will be described.

First, a buffer layer, a channel layer, an electron supply layer 14, and a cap layer 1 sequentially laminated on a GaAs substrate
On the cap layer 15 which is the uppermost layer of the composed epitaxial structure 5, the film thickness of SiO ₂ by CVD 0.1-0.2
.mu.m to form a first insulating layer 18, on which S
The second insulating film 19 is formed by depositing iN to a thickness of 0.1 to 0.2 μm by the CVD method. Next, after patterning the first and second insulating films 18 and 19 using photolithography technology and etching technology as shown in FIG. 6, on the surface of the cap layer 15 where no insulating layer is formed,
An ohmic metal having an AuGe / Ni structure is formed by using a known technique, and the source electrode 22 and the drain electrode 2 are formed.
Form 3 The first and second insulating layers 18 and 19
Is not limited to these as long as they satisfy the selectivity at the time of etching described later.

Next, as shown in FIG. 7, (EB: electron beam) positive resist (for example, SAL11 manufactured by Shipley Co., Ltd. )
0-PL1 ) 25 is formed to a thickness of 0.3 μm, and a negative resist (for example, RD2000 manufactured by Hitachi Chemical Co., Ltd.) is formed thereon.
N) 26 is coated to a thickness of １1 μm. Then, a pattern opening P (パ タ ー ン 1 μm) corresponding to the upper wide portion 17a of the T-shaped gate 17 (and a lead portion reaching the pad portion 17A shown in FIG. 3) is formed in the negative resist 26. At this time, since the negative resist 26 is opened, the positive resist 25 in the opening P is not exposed and remains. In addition, the types of both resists do not intersect at the time of coating, do not affect each other at the time of each development,
In addition, any material may be used as long as it has resistance during the etching of the insulating layers 18 and 19. Further, it is desirable that the cross-sectional shape of the opening of the negative resist is reversely tapered as shown in FIG.

Next, as shown in FIG. 8, an opening Q (〜0... 0) narrower than P is formed on the positive resist 25 in the opening P of the negative resist 26 by using an electron beam direct drawing or the like. 2 μm)
The second insulating layer 19 is opened using anisotropic dry etching such as reactive ion etching (RIE) using this as a mask.

Next, as shown in FIG. 9, the positive resist 25 in the opening of the negative resist 26 is removed by exposing and developing the entire surface. At this time, the negative resist 26
Is selected to absorb the photosensitive wavelength of the positive resist 25. If the opening cross-sectional shape of the negative resist 26 is not reverse tapered, the development time at this time is adjusted and an undercut is made as shown by a dotted line in FIG. .

Next, as shown in FIG.
The first insulating layer 18 is etched using the opening 9 as a mask. This etching is performed using buffered hydrofluoric acid (HF: NH
₃ F = 1: 9) using wet etching with such, by adjusting the amount of over-etching, it is possible to adjust the opening width of the first insulating layer corresponding to the width of the later-described recess 16.

Next, as shown in FIG. 11, the recess 16 reaching the electron supply layer 14 is recess-etched so as to obtain a predetermined threshold voltage of the field-effect transistor. In this etching, the semiconductor layer is made of GaAs, AlG
Since it is aAs, for example, H ₃ PO ₄ : H ₂ O ₂ : H ₂ O =
An etching solution such as 3: 1: 100 is used, but other etching or dry etching may be used.

Next, the etching of the first insulating layer 18 is performed again under the same conditions as the above-mentioned etching, and the opening width S of the first insulating layer 18 is set to be equal to the opening P of the negative resist 26 as shown in FIG. Spread the same. In this state, a gate Schottky metal is vapor-deposited and lifted off.
The structure shown in FIG. Actually, as shown in FIG. 5, an overcoat insulating film 24 is further deposited, and
Drain and source bonding pad metals are formed and completed.

According to the above manufacturing method, the cross section of the gate lead-out section BB in FIG. 3 is as shown in FIG.
In FIG. 8, if the positive resist 25 is opened only in the gate operation part, the gate metal other than the gate operation part will be formed on the second insulating layer 19, and the parasitic capacitance due to the gate lead part will be smaller than that of the semiconductor layer. It is reduced as compared with the case where it is formed in contact with the upper part.

Further, there is an advantage that the gate recess width can be controlled by adjusting the opening width of the first insulating layer 18.

As described above, the present invention relates to AlInAs / GaInA
Although the embodiment applied to the s-based HEMT has been described, the present invention can be applied to various field effect transistors using other semiconductor materials, and it goes without saying that various design changes are possible.

In the above embodiment, the processing is performed by using the lift-off method. However, the gate can be formed by using the etching method.

[0033]

As is apparent from the above description, according to the present invention, the effect of improving the mechanical strength of the T-shaped gate electrode of the field effect transistor and the effect of reducing the parasitic capacitance of the gate portion are obtained. There is. Since the recess portion can be vacuum-sealed, a passivation film in which a conductive layer is formed at the recess interface can be used.

Further, according to the present invention , the controllability of the gate recess width can be increased, and furthermore, since the gate metal other than the gate operating portion can be formed on the second insulating layer, the gate in contact with the semiconductor layer can be formed. This has the effect of greatly reducing the parasitic capacitance as compared with the conventional example in which metal is formed.

[Brief description of the drawings]

FIG. 1 shows a field effect transistor manufactured by applying the present invention .
AA sectional drawing of FIG. 3 which shows a star .

FIG. 2 shows a field-effect transistor manufactured by applying the present invention .
BB sectional drawing of FIG. 3 which shows a star .

FIG. 3 shows a field-effect transistor manufactured by applying the present invention .
Plan view of the register.

FIG. 4 is a sectional view taken along line CC of FIG. 3;

FIG. 5 is a cross-sectional view showing a completed state of a field-effect transistor manufactured by applying the present invention .

FIG. 6 is a sectional view showing a manufacturing process of the embodiment.

FIG. 7 is a sectional view showing the manufacturing process of the embodiment.

FIG. 8 is a cross-sectional view showing the manufacturing process of the example.

FIG. 9 is a sectional view showing the manufacturing process of the embodiment.

FIG. 10 is a sectional view showing the manufacturing process of the embodiment.

FIG. 11 is a sectional view showing the manufacturing process of the embodiment.

FIG. 12 is a sectional view showing the manufacturing process of the example.

FIG. 13 is a sectional view showing the manufacturing process of the example.

14A and 14B are cross-sectional views showing steps of a conventional example.

15A and 15B are cross-sectional views showing steps of a conventional example.

FIG. 16 is a sectional view of a conventional example using an etching method.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 13 ... Channel layer 14 ... Electron supply layer 15 ... Cap layer 16 ... Recess 17 ... T-shaped gate 17a ... Upper wide part 17b ... Support part 18 ... 1st insulating layer 19 ... 2nd insulating layer 20 ... Hollow part

──────────────────────────────────────────────────続 き Continuation of front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/338 H01L 29/778 H01L 29/812

Claims (1)

(57) [Claims] A first insulating layer and a second insulating layer on the semiconductor layer;
Forming a resist layer on the second insulating layer;
A first opening in the layer, and the first opening in the second insulating layer.
Forming a first opening corresponding to the first step, and forming a second opening in the first insulating layer using the first opening as a mask.
Forming an opening, and etching the semiconductor layer using the second opening as a mask.
Forming a recess in the semiconductor layer, and forming the recess after forming the recess,
The first insulating layer is etched to have a width substantially equal to the width of the upper wide portion.
A method of manufacturing a field-effect transistor, comprising: