JPH03147337A - Manufacture of schottky barrier gate type fet - Google Patents

Abstract

PURPOSE:To obtain a T-type gate electrode with a low gate resistance by eliminating a T-type dummy gate using etching, performing recess etching of a substrate layer of the remaining resist layer which is exposed to a mask, and then by forming a gate electrode at the recess-etched region by the lift-off method. CONSTITUTION:An ohmic metal 6 which becomes a source/drain electrode is formed by the lift-off method utilizing a resist layer 5 covering a T-type dummy gate 4 which is subjected to patterning in an inverse taper structure. Then, the resist layer 5 is eliminated, a resist 7 is coated over the entire surface to a thickness covering the dummy gate 4, the resist layer 7 is etched back by dry etching with oxygen for enabling the upper part of the T-type dummy gate 4 to be exposed. The exposed T-type dummy gate 4 is eliminated by etching using a buffered fluoric acid, an exposed substrate layer 1 is recess-etched, and a gate metal 8 is deposited onto the entire surface. Then, when an unneeded gate metal 8 is eliminated, the gate metal in T-type shape is formed on the recess-etched substrate layer.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a Schottky barrier gate type FET.

[Prior art] The electron mobility in n-type GaAs is much larger than that in SN, and in Schottky barrier junctions, rectifying characteristics are obtained by majority carriers, whereas in PN junctions, the electron mobility is dominated by minority carriers. It is not a given characteristic. From this, Schottky barrier gate FETs made of GaAs have excellent high-speed response, and by taking advantage of this high-speed response, they are suitable for devices in the microwave region and are also applied to ultra-highly integrated ICs. There is.

FIG. 3 shows an example of a method for manufacturing a conventional Schottky barrier gate type FET.

First, using a resist layer 5 patterned in a reverse tapered structure, an ohmic metal 6 for source/drain electrodes is formed on a semiconductor substrate 1 by a lift-off method [Fig.
)], next, a resist is applied to the entire surface, a resist layer 7 is formed as a mask for recess etching by phosphorography [Figure (b)], and recess etching is performed [Figure (C)].
)], and gate metal 8 is deposited [Figure (d).

When the gate metal 8 deposited on the recess-etched substrate layer and the gate metal 8 deposited on the resist layer 7 are lifted off and the resist layer 7 is removed, the unnecessary gate metal 8 is removed and the Schottky structure of the recessed structure is removed. A barrier gate type FET is obtained [Figure (C)]. 9 is a source electrode, 10 is a drain electrode, and 11 is a gate electrode.

[Problems to be Solved by the Invention] One of the parameters that affects the operating characteristics of an FET is the gate resistance R, and it is known that the lower the gate resistance R is, the better the operating characteristics of the FET will be.

Conventional manufacturing methods have had the problem that when the gate length of the gate electrode is shortened, the gate resistance R increases.

The present invention was made to solve the above problems.
It is an object of the present invention to provide a method that can lower gate resistance than conventional methods without changing the effective gate length.

[Means for Solving the Problems] The manufacturing method of the present invention first involves applying plasma C to a semiconductor tile board.
A plasma CVD silicon nitride film with a three-layer structure in which the etching rate decreases sequentially from the substrate side is formed by VD, and a T-shaped dummy gate with a two-stage structure is formed by reactive ion etching and wet etching.
Next, a resist is applied, the resist layer covering the T-shaped dummy gate is etched back to expose the upper part of the T-shaped dummy gate, the T-shaped dummy gate is removed by etching, and the remaining resist layer is used as a mask. The exposed substrate layer is recess-etched, a gate electrode is formed in the recess-etched region by a lift-off method, and a gate electrode with low gate resistance is formed.
This is a method to obtain a type gate electrode.

[Example] FIG. 1 shows an embodiment of the invention.

First, a silicon nitride film 2a having the highest etching rate is deposited on the semiconductor substrate 1 by plasma CVD,
Next, a silicon nitride film 2b having an intermediate etching rate is deposited on the silicon nitride film 2a by changing the plasma CVD conditions, and then a silicon nitride film 2b having the highest etching rate is deposited on the silicon nitride film 2b by changing the plasma CVD conditions. A small silicon nitride film 2c is deposited to form a three-layer plasma CVD silicon nitride film 2 [FIG. (a)].

Originally, it is difficult for a silicon nitride film formed by plasma CVD using SiH and N H3 gases to have a stoichiometric composition of S j 3N i. Generally, it is said to contain hydrogen in the form S 1 , N yHz.

Focusing on the fact that the film quality could be changed by adjusting the amount of hydrogen contained in the film, by changing the gas flow rate ratio of Si H4 and NH3, the plasma CVD silicon nitride film formed The film quality was changed by changing the hydrogen concentration.

FIG. 2 shows the relationship between the reaction gas flow rate ratio in plasma CVD and the etching rate and deposition rate of the plasma CVD silicon nitride film formed. SiH and NH3
It can be seen that when the reaction gas flow rate ratio is increased, the etching rate of the formed plasma CVD silicon nitride film increases.

Next, a vapor-deposited A41 layer 3 is formed on the entire surface, and this AΩ layer 3 is patterned into a predetermined pattern by photoetching [Figure (b)]. Using the pattern of the Al layer 3 as a mask, a plasma CVD silicon nitride film with a three-layer structure is formed. 2 is subjected to reactive ion etching [Figure (C)], the Al1 layer 3 is etched away, and then etched with buffered hydrofluoric acid to form a two-stage T-shaped dummy gate 4 using the difference in etching rate.
[Figure (d)].

Next, using the resist layer 5 covering the T-shaped dummy gate 4 patterned to have an inverted tapered structure, an ohmic metal 6 that will become the source-drain electrode is formed by a lift-off method [FIG. (e)].

Subsequently, the resist layer 5 is removed, resist is applied to the entire surface to a thickness that covers the dummy gate 4, and the resist layer 7 is etched back by dry etching with oxygen to expose the upper part of the T-shaped dummy gate 4. Figure (r)].

The exposed T-type dummy gate 4 is removed by etching with buffered hydrofluoric acid, the exposed substrate layer l is recessed and etched [Figure (g)], and gate metal 8 is deposited on the entire surface [Figure (
h)].

When the gate metal 8 deposited on the recess-etched substrate layer and the gate metal 8 deposited on the resist layer 7 are lifted off and the resist layer 7 is removed, the unnecessary gate metal 8 is removed.

On the other hand, the gate metal 8 deposited on the recess-etched substrate layer has a T-shape, the effective gate length is the same as that by the conventional method, and the gate resistance can be significantly reduced compared to the conventional method. .

[Effects of the Invention] As explained above, according to the present invention, the gate electrode has T
The gate resistance can be reduced with a short gate length, which greatly contributes to improving the FET operating characteristics.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram showing one embodiment of the present invention, FIG. 2 is a graph showing the relationship between the reactant gas flow rate ratio in plasma CVD and the etching rate and deposition rate of the plasma CVD silicon nitride film formed. The figure is an explanatory diagram showing an example of a method for manufacturing a conventional Schottky barrier gate type FET. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Plasma CVD silicon nitride film, 3... AJ7 layer, 4... T-type dummy gate, 5... Resist layer, 6... Ohmic metal, 7
...Resist layer, 8... Gate metal, 9... Source electrode, 10... Drain electrode, 11... Gate electrode. Note that the same reference numerals in the figures indicate the same or corresponding parts. Special r [Applicant: New Japan Radio Co., Ltd. Figure 1

Claims (1)

[Claims] A plasma CVD silicon nitride film having a three-layer structure in which the etching rate decreases layer by layer from the substrate side is formed by plasma CVD on a semiconductor substrate, and a vapor-deposited Al layer is formed on the silicon nitride film. , pattern the Al layer into a predetermined pattern by photo-etching, perform reactive ion etching on the plasma CVD silicon nitride film with the three-layer structure using the Al layer as a mask, remove the Al layer, and then pattern it with buffered hydrofluoric acid. A process of etching and forming a T-shaped dummy gate with a two-stage structure using the etching rate difference, and a source formed using a resist layer with an inverted tapered structure.
A resist layer is formed to cover the ohmic metal for the drain electrode and the T-shaped dummy gate, and the resist layer is etched back by dry etching using oxygen to expose the upper part of the T-shaped dummy gate. A method for manufacturing a Schottky barrier gate type FET, comprising the steps of etching away a type dummy gate, recess-etching an exposed substrate layer, and forming a T-type gate electrode on the recess-etched substrate layer by a lift-off method.