JPS62291070A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce an amount of scatter of FET threshold voltage and enhance a yield rate of GaAs IC by treating an insulated film through an etching process under low gas pressure and causing a semiconductor substrate to be exposed by increasing the gas pressure for etching. CONSTITUTION:An insulated film 4 is formed on the whole surface of semiconductor substrate 1 after forming an active layer 2 on the substrate 1. After an ohmic electrode 5 is formed, a gate electrode pattern 7 is formed according to a resist 6 and the above insulated film 4 is treated by etching after decreasing etching gas pressure through a reactive ion etching device and as a result, the insulated film 4 is left at a gate electrode opening part 8. And then, the reactive ion etching is carried out by increasing etching gas pressure and the insulated film 4 remained at the gate electrode opening part 8 is treated by etching and the treated film 4 allows the substrate 1 to be exposed, resulting in the formation of a gate electrode 10 at the gate electrode opening 9 where the substrate 1 is exposed. For instance, the formation of recessed part 8 of silicon nitriding film 4 necessitates CF4 gas pressure to have 10 Pa and the etching treatment is carried out under gas pressure of 30 Pa until a resultant substrate exposure.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device that reduces variations in threshold voltage of highly integrated GaAs field effect transistors. It is related to.

Conventional technology GaAs (dSi) has an electron mobility 5 to 6 times higher than that of dSi, and it is possible to obtain semiconductor devices with excellent high frequency characteristics.In particular, GaAs Schottky barrier field effect transistors (hereinafter referred to as MES-FETs) ) have excellent characteristics as ultra-high frequency or ultra-high speed elements, and integrated circuits using MES-FETs are expected to be used as ultra-high-speed ICs and microwave ICs, and active development is progressing.
The MES-FET process is not as stable as the Si process, and there is also large variation in the substrate itself, which is the cause of the low yield of GaAs ICs.

In order to improve the yield of GaAs ICs, it is essential to reduce variations in threshold voltage through process improvements.

FIG. 2 shows a conventional manufacturing method for forming a GaAs FET. An active layer 12 and a high concentration source/drain layer 13 are formed on the GaAs substrate 11 by ion implantation.
(a). Thereafter, a silicon nitride film 14 is formed on the entire surface of the GaAs substrate 11 (b), and then an ohmic electrode 15 is formed (C). After that, photoresist 1
d), the silicon nitride film 14 at the opening of the gate electrode pattern 17 is etched away by reactive ion etching, and G a A is formed.
Expose the s-substrate and form the gate electrode opening 18 (
e) Next, place the gate electrode 19 in the gate electrode opening 18.
to form a GaAs MES-FET (f).

Problems to be Solved by the Invention The method for manufacturing GaAs MES-FETs as explained in FIG. For example, reactive ion etching with sputtering properties at a pressure of about 10 Pa is used. However, if there are variations in reactive ion etching or variations in the thickness and quality of the insulating film, the etching time for exposed parts of the substrate will vary and some parts will be over-etched. Therefore, as shown in FIG. 3, the GaAs substrate 11 is slightly etched by reactive ion etching, and as a result, for example, in a normally-off type GaAs FET with a thin active layer, a small amount of etching has a large effect on the threshold voltage. This causes variations and causes a decrease in yield in highly integrated GaAs ICs.

Means for Solving the Problems In order to solve the above problems, the present invention provides a step of forming an active layer on a semiconductor substrate, a step of forming an insulating film on the entire surface of the semiconductor substrate, a step of forming an ohmic electrode, and a step of forming an ohmic electrode. -7 to the gate electrode pattern 5, etching the insulating film with a reactive ion etching device at a low etching gas pressure, and leaving the insulating film in the gate electrode opening, reducing the etching gas pressure. The method includes a step of exposing the semiconductor substrate by etching the insulating film remaining in the gate electrode opening by high-reactive ion etching, and a step of forming a gate electrode in the exposed gate electrode opening of the semiconductor substrate.

Function The present invention has the configuration described in section 2.
GaAs M
It becomes possible to improve the yield of GaAs IC using ES-FET.

Embodiment An embodiment of the method for manufacturing a semiconductor device according to the present invention is shown in FIG. In FIG. 1, 1 is a semiconductor substrate such as GaAs, 2 is an active layer, 3 is a high concentration source/drain layer, 4 is an insulating film, 5 is an ohmic electrode, 6 is a photoresist, and 7 is a gate electrode formation pattern. , 86 are four etched parts, 9 are gate electrode openings, and 10 are gate electrodes. An active layer 2 and a high concentration source/drain layer 3 are formed on a semiconductor substrate 1, for example, a GaAs substrate, by ion implantation (a) o At this time, the implantation conditions are as follows:
is 81 ions in 30 keys 6×1o12crn-2
For the source/drain high concentration layer 3, Si ions are implanted in 6×10 13 cIn-2 in 50 keys. Thereafter, capless annealing is performed at 820° C. for 20 minutes in an arsine atmosphere. Thereafter, an insulating film 4, for example, a silicon nitride film, is formed on the entire surface of the GaAs substrate 1 using a plasma CVD method.
Forming an ohmic electrode 6, for example, AuGe /N i /Au at 1300/40 using the zero-order lift-off method.
Form 0/1000 people (C). Next, photoresist 6
A gate electrode pattern 7 is formed (d). After that, C
Reactive ion etching is performed using F4 gas at a gas pressure of 10 pa to etch the silicon nitride film 4 by about 3,000 degrees to an extent that the GaAs substrate 1 is not exposed to form the recess 8 (e). Thereafter, the remaining silicon nitride film 4 on the four parts 8 is removed by reactive ion etching at a CF4 gas pressure of 3oPa to expose the G a A g substrate 1 and form the gate electrode opening 9 (f ). Then the gate metal, for example T i /P t /Au, is 1000/600/3.
A gate electrode 1o is formed by lift-off, and a GaAs MES-FET is formed.

In the embodiment of the present invention, reactive ion etching is used to form the gate electrode opening, and the etching gas (CF4) pressure is 10 Pa to form the four parts 8 of the silicon nitride film.
Then perform etching with enhanced sputtering properties, and then increase the etching gas pressure to 30°C until the substrate is exposed.
P a is used to weaken sputtering properties and suppress etching of the substrate, suppressing variations in threshold voltage due to variations in etching. FIG. 4 shows the etching rate of the silicon nitride film and GaAs when the CF4 gas pressure is changed. It can be seen from this that the etching rate of GaAs is large when the CF4 gas pressure is 1oPa or less, but almost no etching occurs when the pressure is Hespa or more.

Note that although a silicon nitride film is used as the insulating film in this embodiment, any insulating film such as a silicon oxide film may be used.

Further, the ohmic gate metal is not limited to this embodiment, and may be other metals. Furthermore, although a GaAs substrate is used in this embodiment, other semiconductor substrates may be used.

Effects of the Invention The method for manufacturing a semiconductor device of the present invention does not require side etching and can easily form electrode openings by etching the semiconductor substrate, thereby reducing variations in the threshold voltage of FETs. The yield of GaAs IC can be improved.

[Brief explanation of the drawing]

1a-q are cross-sectional views of the manufacturing process of a semiconductor device manufacturing method according to an embodiment of the present invention, FIGS. The cross-sectional view and FIG. 4 are graphs showing the relationship between notching gas pressure and etching rate. 1...Semiconductor substrate, 2...Active layer, 3
...Source/drain high concentration layer, 4...
・Insulating film, 6...Memic electrode, 6...
... Photoresist, 7 ... Ge 9 Vapor electrode formation pattern, 8 ... Insulating film recess, 9
. . . Gate electrode opening, 10 . . . Gate electrode. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Zuhiro/Main layer Figure 1 Figure 3? ,,3z Figure 2

Claims (2)

[Claims] (1) A step of forming an active layer on a semiconductor substrate, a step of forming an insulating film on the entire surface of the semiconductor substrate, a step of forming an ohmic electrode, a step of forming a gate electrode formation pattern with resist, and a step of forming the insulating film with reactive ions. Etching is performed by lowering the etching gas pressure using an etching device.
a step of leaving the insulating film in the gate electrode opening;
a step of exposing the semiconductor substrate by performing reactive ion etching with high etching gas pressure to etch the insulating film remaining in the gate electrode opening; and a step of forming a gate electrode in the exposed gate electrode opening of the semiconductor substrate. A method for manufacturing a semiconductor device, characterized in that: (2) Etching gas pressure in reactive etching that leaves the insulating film in the gate electrode opening is 10 Pa.
2. The method of manufacturing a semiconductor device according to claim 1, wherein the etching gas pressure in the reactive ion etching to expose the semiconductor substrate is set to 25 Pa or more.