JPS63248179A - Semiconductor device - Google Patents

Abstract

PURPOSE:To inhibit stress changes and stress concentration near a gate and the edge of an insulating film for a Schottky FET, etc., by applying the insulating film onto a semiconductor operating layer near a gate electrode. CONSTITUTION:When an insulating film 6 consisting of SiO2 is applied onto an operating layer near a Schottky gate 1 with the exception of the gate 1, stress changes and stress concentration near the gate and the edges of the insulating film are made smaller than there is the insulating film on the gate 1. Accordingly, the charge fluctuation of the operating layer is inhibited, thus preventing the generation of the alteration of the threshold of a Schottky FET, etc.

Description

[Detailed description of the invention] (Industrial application field) The present invention relates to a semiconductor device.

(Prior Art) Semiconductor devices, for example, 7 yota using gallium arsenide (GaAs) =? #Wall-type field effect transformer λ (hereinafter referred to as M
A structure as shown in FIG. 2 is known as an ESFET.

In Figure 2, IA is the gate electrode, 2a is the north electrode,
2b is a drain electrode, 3 is made of GaAs, 6 is an insulating film,
7 is the second layer metal.

Currently, high-speed integrated circuits using such MESFETs are being manufactured.

(Problems to be Solved by the Invention) When GaAs MESFETs are produced, it is currently difficult to obtain a desired FET threshold voltage, and therefore the yield rate of FETs or integrated circuits using FETs is low. The problem is that it is extremely low. One of the reasons for this is ℃,
It is thought that the stress of thin reflections of the gate electrode, insulating film, etc. formed on the compound atom body generates piezoelectric polarization within the compound atom body. Due to the piezoelectric polarization, the electric charge of the active layer provided inside the compound element 4 changes, so F
The threshold voltage of ET will change. Since the change in threshold voltage is very large in the short channel, this problem becomes particularly important in the development of imitation cords.

If the gate direction is perpendicular to (011,1 and (011)) on the (100) surface of the GaAs substrate, the sign of the extra piezoelectric charge is opposite, so when the piezoelectric charge is generated, the F in the circular direction
A phenomenon occurs in which the threshold voltages of ET differ. Therefore, when manufacturing an integrated circuit, it is difficult to arrange the FETs orthogonally, which causes a problem of lowering the degree of integration of the integrated circuit. In addition, it is thought that the trade area, the bulge, which occurs near the edge of the thin film is a temporary one from the viewpoint of the X:8i axis property.

One object of the invention is to provide a highly reliable semiconductor device in which stress changes and stress concentration near the edges of the gate and insulating film of a compound hand-wrapped field effect transistor are suppressed.

(Means for Solving Interference Points) The semiconductor device of the present invention has a gate electrode and an insulating film selectively disposed on a semiconductor active layer, and the insulating film covers the semiconductor near the gate electrode. It has a structure in which it is temporarily attached to the entire surface of the active layer, and there is no insulating film on the gate electrode.

(Function) It is known that in a zinc structure such as GaAs, polarization is induced when strain is applied to the crystal, and piezoelectric charges are generated by the polarization. In particular, stress concentration occurs near the edges of the gate electrode formed on the GaAs active layer and the insulating film coated with N on the semiconductor active layer, so that piezoelectric charges are extremely generated. Therefore, it is important to suppress this stress concentration.

As a result of numerical analysis and experiments investigating the relationship between stress concentration occurring near these edges with and without an insulating film on the gate electrode film, the present inventor, Shoji, found that the insulating film on the gate electrode film is It has become clear that when there is no insulating film on the gate electrode film, stress concentration is smaller than when there is an insulating film on the gate electrode film.

(Example) Next, an example of the present invention will be described together with a manufacturing method with reference to the drawings. FIG. 1 ta+ to te+ are cross-sectional views of a half-body TIG shown in the order of steps for explaining an embodiment of the present invention.

First, as shown in FIG.
Ions were implanted under the conditions of 1012 (m-2), and then heated at 800° C. for 20 minutes in an ASH3 atmosphere (to form a JAs active layer 3).

Next, as shown in FIG.
) was deposited to a thickness of 0.5 μm using the sprue method.

Next, the ~Si film was patterned into a predetermined shape by conventional photography and dry etching using carbon tetrafluoride to form a Schottky gate 1.

Next, as shown in FIG. 1 fc), using the s'M Udokey gate 1 as a mask, Si ions were heated at 150 keV.

Ion implantation was performed under the conditions of 5 x 10 cm, and further annealing was performed at 750°C for 20 minutes in an atmosphere of n+
Layers 4a and 4b were formed.

As shown in FIG. 1(d), a source electrode 2a and a drain electrode Q2b made of a metal layer of AuGe-Ni were formed face down. Next, as an insulating film, 5
The i02 film 6 was exposed to a thickness of 0.5 μm. Next, photoresist was applied to the entire 5i02 film 6 to a film thickness of 5 μm.
Baking at 00'O made the wafer surface flat. Next, the photoresist is etched by a dry etching method using CF, and 5iO on the gate electrode is etched.
zllll was removed.

Finally, as shown in FIG. 1(e), Ti is deposited on the Schottky gate 1, the source electrode 2a, and the drain electrode 2b.
A second layer cap region It7 made of -Pt-Au was formed.

For comparison, a conventional FE in which the insulating film on the gate electrode film was not removed by dry etching in the above process was also shown.
T was also formed.

The threshold voltage of FET with different structure is (OIIJ
Sword direction and direction 11] Measured in the sword direction. Table 1 summarizes the results. As is clear from Table 1, 5i02 on the gate electrode
In the FET without a film, the difference in threshold voltage VT between the (011) direction and the (011) direction is small, which indicates that stress concentration at the edge of the gate is small.

Table 1 In the above description, WSi was used as the gate electrode, but other materials such as aluminum (AI) may also be used. In addition to SIO, the insulating film is also silicone film (Si).
Other materials such as N) may also be used. In addition, although the explanation has been made using a compound semi-consolidated material made of GaAs, other semi-consolidated materials may also be used.

(Effects of the Invention) As explained above, in the present invention, by forming an insulating film on the semiconductor active layer over the gate electrode, it is possible to reduce the stress concentration generated near the edge of the gate electrode. Time! 11: Fluctuations can be suppressed. Therefore, the credibility of the Ushijintai device is the same as above.

[Brief explanation of the drawing]

FIGS. 1 fa) to TE) are cross-sectional views of a semi-2I chip shown in the order of steps for explaining an embodiment of the present invention, and FIG. 2 is a cross-sectional view of an example of a conventional MESFET. l...Schottky gate, IA...gate electrode, 2a...source electrode, 2b...
...Drain electrode, 3...Active layer, 4a, 4b
......n wll 5... Semi-insulating substrate, 6... Insulating film, 7... Second layer gold maple. Tsubo l bacteria

Claims (1)

[Claims] A semiconductor device having a gate electrode and an insulating film selectively disposed on a semiconductor active layer, wherein the insulating film is deposited on the entire surface of the semiconductor active layer except on the gate electrode. Device.