JPS59165466A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To enable to arbitrarily set accurately the threshold voltage of an FET by the externally applied voltage by providing a buffer region only directly under an active region which becomes a channel between source and drain regions formed in a compound semiconductor substrate. CONSTITUTION:To activate ion implanted layers 26, 27, 30 after removing a silicon nitrided film 22 and a photoresist 28, a heat treatment is performed. Thus, the layers 26, 27, 30 respectively become source, drain region and channel region. A silicon nitrided film 31 is then formed newly by a plasma CVD method, a photoresist pattern 32 is formed thereon, a hole 22 for forming a buffer layer is formed by a photographic step, and a P type region is formed as a buffer layer 34 by using an ion implantation method. Then, after removing the pattern 32, a heat treatment is executed to activate the layer 34. Photoresist is rotatably coated on the overall surface, the photoresist is opened as desired, and a necessary electrode material is deposited.

Description

[Detailed Description of the Invention] Industrial Application Field The present invention relates to a semiconductor device, particularly a field effect transistor (hereinafter abbreviated as FET) using a compound semiconductor material, and a method for manufacturing the same.Constitution of a conventional example and its problems Compound semiconductor When constructing a field effect transistor using this material, ME using a Schottky barrier as a gate
5FET is common. Depletion type FET (hereinafter referred to as D-FET) is a depletion type FET (hereinafter referred to as "1-normally-on type") in which a negative voltage is applied to the gate electrode to widen the depletion layer and control the active layer thickness.
(abbreviated as "1-normally-off type") and a double-hunched FET (hereinafter referred to as "E-FET"), whose active layer region is already depleted by Schottky's internal potential and whose active layer thickness is controlled by applying a positive voltage to the gate. ). In these D-FETs and E-FETs, the threshold voltage is determined by the thickness of the active layer directly under the Schottky interface in the gate portion of the FET, and therefore methods have been proposed to accurately reduce the thickness of the active layer.

The structure shown in FIG. 1 is a so-called "recessed structure" in which the thickness of the active layer directly under the gate is made thinner by means such as chemical etching in order to obtain a desired threshold voltage. In Figure 1, 1 is a semi-insulating GaAs substrate, 2 is an n-type G
aAs, 3, and 4 are ohmic electrodes that serve as source and drain electrodes. 6 becomes the gate electrode when the key is touched.

FIG. 2 shows another conventional example, in which a semi-insulating GaAs substrate 1
1, a high-concentration ion-implanted layer 12.13 that will become the source and drain regions and an active layer 14 that will become the gate region are formed by ion implantation in 1, and after activation, an ohmic electrode 15.1 is formed.
6 are formed to serve as source and drain electrodes. Reference numeral 17 is a Schottky contact, and a gate electrode is made of platinum (PT) as a metal. The Schottky interface 18 of the gate electrode is embedded into the active layer 14 by heat treatment to control the threshold value.

The structure shown in Figure 1 uses chemical etching, etc., so it is difficult to control the threshold voltage because the thickness of the active layer in the gate electrode part is insufficiently controlled, and it is not a planar structure. It is not appropriate to use it for

Figure 2 shows an electrode made of PT at the gate part.
Since it is embedded in aAs, the threshold voltage can be controlled by changing the heat treatment time if the temperature is held constant, but when forming an integrated circuit, it is difficult to make the threshold voltage uniform over a large area. Have difficulty. Since heat treatment is still generally carried out at around 380°C, the temperature cannot be raised above 380°C in subsequent steps, which limits the method of manufacturing FETs.

OBJECTS OF THE INVENTION The object of the present invention is to provide a new FET that eliminates the above-mentioned drawbacks and a method for manufacturing the same. SUMMARY OF THE INVENTION An object of the present invention is to obtain an FET whose threshold voltage can be arbitrarily and precisely set by an externally applied voltage.

Structure of the Invention In the present invention, a buffer region is provided only directly under an active region that becomes a channel between source and drain regions formed in a compound semiconductor substrate, and a channel current is controlled in this region. Then, in the manufacturing method of the present invention, a highly concentrated ion-implanted layer is formed on a compound semiconductor substrate to form source and drain regions, an active region that becomes a channel is formed by ion implantation, and a layer directly below the active region is formed. A desired buffer layer is formed by ion implantation, and a source electrode, a drain electrode, a gate electrode, and an electrode for applying a voltage to the buffer layer are formed to form an FET.

DESCRIPTION OF EMBODIMENTS The present invention will be described in detail using embodiments shown in the drawings. In Figure 3a, GaAs doped with chromium (Cr)
A silicon nitride film 22 having a thickness of, for example, 3,000 wafers is formed on a semi-insulating semiconductor substrate 21 by plasma CVD, and a seven-layer photoresist 23 is spin-coated thereon. Openings 24 and 25 for forming a drain region are formed in the photoresist 23 and the nitride film 22, and then silicon (Si ) to form a concentrated ion-implanted layer 26, 2 (FIG. 3a).

After removing the resist 23, a new photoresist 28 is applied by spin coating, and as shown in FIG. Energy 120KeV, dose 5
Silicon (St) is implanted as ×1o126n-2,
An active layer 3o is formed.

After removing the silicon nitride film 22 and photoresist 28, AsH3 was applied to activate the ion implantation layers 26, 27, and 30.
Heat treatment is performed in an atmosphere at a temperature of 850° C. for 20 minutes. In this way, the injection layers 26, 27, and 30 become source and drain regions and two channel regions, respectively.

As shown in FIG. 3c, a silicon nitride film 31 is newly formed to a thickness of, for example, 4000 nm by plasma CVD method.
A photoresist pattern 32 with a thickness of 1.2 μm is formed on the soil, and a photo process is used to form a buffer (hole 33 for forming a layer), and an acceleration energy of 170 KeV is applied using an ion implantation method. 2×10 m
Barium (Be) is then implanted to form a p-type region as the buffer 7 layer 34. Note that the amount of ions implanted into the active region 30 is increased by the amount compensated for by the ion implantation into the buffer layer 34.

Next, after removing the resist pattern 32, heat treatment is performed at a temperature of 700° C. for 20 minutes in an H2 atmosphere to activate the buffer layer 34.

Apply a photoresist (not shown) on the entire surface with a thickness of 1.2 μm, for example.
After spin-coating the photoresist to a thickness of , opening holes in the photoresist at desired locations, and depositing the necessary electrode material, the photoresist is dissolved with a solvent to form a metal film in the desired shape. Using a method called "lift-off method," the case, drain, gate electrode, and buffer layer electrode (shown in FIG. 4a) are formed as shown in FIG. 3d. In this case, after spin-coating photoresist to a thickness of 1.2 μm, 6'O0 of Ti as a metal material, 500 of PT on top of that, and 3000 of Au on top of the active region 35 were deposited using a lift-off method. A Schottky gate electrode 36 is formed by the following steps. Add photoresist to 1.2
After coating μm, an alloy of Au, Ge was used as the metal material.
A source electrode 39 and a drain electrode 40 are formed by depositing 250 OA of Au on the high-concentration ion-implanted layers 37 and 38 of the source and drain regions by a lift-off method.

After spin-coating a similar photoresist to a thickness of 1.2 .mu.m, 4,000 layers of 82 as a metal were vapor-deposited, and an ohmic contact was formed with the surface layer 34 using a lift-off method to form an electrode 41 of the buffer layer. FIG. 4a is a cross-sectional perspective view of the main part of the FET formed through the steps shown in FIG.
It is a sectional view taken along the line AA' in the figure.

FIG. 5 shows the depth just below the gate electrode 35, the carrier concentration curve 61 of the active region and the buffer layer, and the curve 52 in FIG. 3d. A p-n junction is formed between the buffer layer 34 and the active region 30 at a depth of approximately 0.3 μm. As shown in FIG. 4, the buffer layer 34
When a negative voltage is applied to the active region 3o and the buffer layer 34, a depletion layer spreads as a reverse bias occurs in the p-n junction.

This depletion layer allows the effective thickness d of the active region 30 to be reduced. For the sake of simplicity, if we assume that the carrier concentration Nd in the active region is constant at 2 × 10 m, the effective thickness de of the active region is p−n from the Schottky interface.
The distance d between the junction surfaces is calculated by subtracting the thickness of the depletion layer of the Schottky internal potential Vg, and d is generally expressed by the following equation.

Here, do is the thickness of the active region, ε is the dielectric constant of the substrate,
e is a unit charge, Vd is an applied voltage, and the direction of reverse bias is positive. Vd is the diffusion potential of the p-n junction.

Further, in this case, the threshold voltage th is expressed as shown in the second equation.

Therefore, from equation (1), by changing the voltage d applied to the buffer layer, the thickness d of the active layer directly under the Schottky can be
is uniquely determined, and from equation (2), the threshold voltage V. h
is decided. FIG. 6 shows the relationship between the applied voltage (8) and the threshold voltage (2). Curve 61 shows that relationship. By changing the voltage applied to the buffer layer in this way, the threshold voltage can be easily changed to create a D-FET.

E-FETs can be easily manufactured using the same process.

However, in the case of the present invention, the effective thickness of the active region can be controlled by an externally applied voltage, so compared to conventional FETs,
The thickness of the active region can be increased, which facilitates manufacturing. Furthermore, the advantage of the structure shown in Figure 1000 is that the buffer layer 3
By making the length of 4 equal to or shorter than the gate length of the Schottky electrode, the depletion layer due to the buffer layer does not expand near the source and drain regions.
The source resistance and drain resistance can be reduced, and the high frequency characteristics of the FET can be improved.

Although the present invention has been described above using GaAs as an embodiment, it goes without saying that it can be applied to shot 4 FETs using other semiconductor materials such as silicon, indium-arsenic-phosphorus mixed crystal, etc.

Effects of the Invention As explained in the examples, the present invention uses a normal semi-insulating compound semiconductor material to form a buffer layer directly under the active region of an E-FET, thereby easily and accurately adjusting the threshold voltage. Can be set, i.e. D-FET, E-F
ET can be freely changed by externally applied voltage.

[Brief explanation of the drawing]

Figure 1 is a structural diagram of a GaAs Schottky FET with a conventional recess structure, Figure 2 is a structural diagram of a conventional GaAs Schottky FET with a platinum-embedded gate, and Figures 3 a-d.
4A is a schematic diagram of the manufacturing process for explaining the structure of a GaAs Schottky FET according to an embodiment of the present invention, FIG. is a cross-sectional view showing the bias state of the same FET, FIG. 5 is a diagram showing the relationship between the depth just below the gate electrode and the carrier concentration of the Schottky FET of the present invention, and FIG. 6 is a diagram showing the relationship between the applied voltage of the buffer layer and the threshold voltage. It is a diagram showing the relationship. 21... Semi-insulating GaAs substrate, 22...
...Silicon nitride film, 23...Photoresist, 26.27...High concentration ion implantation layer, 28.
...Photoresist, 29...Opening part for active layer, 3o...Active layer, 31...Silicon nitride film, 32... Photoresist, 34
... Buffer layer, 36 ... Gate electrode, 39 ... Source electrode, 40 ... Drain electrode, 41 ... Back 7 layer electrode. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 3 Figure 4

Claims (4)

[Claims] (1) Forming a source and a drain region on a compound semiconductor substrate, an active region serving as a channel between the source and drain regions, forming a buffer region only directly under the active region, and forming a source electrode in the source and drain regions. . A semiconductor device, further comprising a drain electrode formed, a gate electrode formed on the active region, and a control electrode connected to the buffer region. (2) The semiconductor device 0 according to claim 1, wherein the length of the buffer layer is equal to or shorter than the gate length on which the Schottky electrode is formed. (3) The semiconductor device according to claim 1, wherein the channel current is made normally on or normally off by applying a voltage to the first buffer layer through the buffer layer electrode. (4) A step of forming a high concentration ion implantation layer that will become a north and drain region on a compound semiconductor substrate, a step of forming an ion implantation layer that will form an active region that will become a channel region on the semiconductor substrate, and a step of forming an ion implantation layer that will become an active region that will become a channel region on the semiconductor substrate. a step of forming an ion implantation layer serving as a buffer layer directly below the source region;
A method for manufacturing a semiconductor device 0 characterized by including the steps of forming an ohmic electrode in a drain region and a buffer layer, and forming a Schottky gate electrode in the active region.